{"paper":{"title":"SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware","license":"http://creativecommons.org/licenses/by/4.0/","headline":"A 10T SRAM cell with integrated full adders cuts routing complexity by half and raises area efficiency 2.67 times for binary neural network hardware.","cross_cats":[],"primary_cat":"cs.AR","authors_text":"Narendra Singh Dhakad, Santosh Kumar Vishvakarma","submitted_at":"2026-05-15T16:39:53Z","abstract_excerpt":"This paper presents a novel architecture utilizing a 10T SRAM cell for XNOR-based in-memory computing, aimed at mitigating the extensive routing challenges typically encountered in conventional in-memory computing systems. By integrating a full adder between in-memory multiplication cells, the proposed design achieves a 50% reduction in routing complexity. The architecture performs multiply-accumulate (MAC) operations using XNOR computation optimized for binary neural networks (BNNs). Additionally, a 14T-based full adder is employed to construct an N-bit ripple carry adder in the adder tree, s"},"claims":{"count":4,"items":[{"kind":"strongest_claim","text":"The proposed approach reduces the latency and area overhead, improving the overall hardware's area efficiency by 2.67x compared to the state-of-the-art.","source":"verdict.strongest_claim","status":"machine_extracted","claim_id":"C1","attestation":"unclaimed"},{"kind":"weakest_assumption","text":"The integration of the full adder between in-memory multiplication cells achieves the stated 50% routing reduction and area savings without introducing unaccounted overheads in yield, delay, or power in actual fabrication.","source":"verdict.weakest_assumption","status":"machine_extracted","claim_id":"C2","attestation":"unclaimed"},{"kind":"one_line_summary","text":"Proposes a 10T SRAM XNOR in-memory computing architecture with 14T full adders that reduces routing complexity by 50% and improves area efficiency by 2.67x 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