{"paper":{"title":"The ARAGORN front-end - An FPGA based implementation of a Time-to-Digital Converter","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["hep-ex"],"primary_cat":"physics.ins-det","authors_text":"Carl Schaffer, Florian Herrmann, Horst Fischer, Maximilian B\\\"uchele","submitted_at":"2017-02-22T09:09:14Z","abstract_excerpt":"We present the ARAGORN front-end, a cost-optimized, high-density Time-to-Digital Converter platform. Four Xilinx Artix-7 FPGAs implement 384 channels with an average time resolution of 165 ps on a single module. A fifth FPGA acts as data concentrator and generic board master. The front-end features a SFP+ transceiver for data output and an optional multi-channel optical transceiver slot to interconnect with up to seven boards though a star topology. This novel approach makes it possible to read out up to eight boards yielding 3072 input channels via a single optical fiber at a bandwidth of 6.6"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"1702.06713","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}