{"paper":{"title":"The ESS FPGA Framework and its Application on the ESS LLRF System","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["physics.acc-ph"],"primary_cat":"physics.ins-det","authors_text":"2), (2) Lund University, (3) Sigma Connectivity AB), A. J. Johansson (1, C. Amstutz (1), M. Donna (1), M. Mohammednezhad (3) ((1) European Spallation Source ERIC","submitted_at":"2018-03-24T02:40:58Z","abstract_excerpt":"The functions of the Low-Level Radio Frequency (LLRF) system at European Spallation Source (ESS) are implemented on different Field-Programmable Gate Array (FPGA) boards in a Micro Telecommunications Computing Architecture (MTCA) crate. Besides the algorithm, code that provides access to the peripherals connected to the FPGA is necessary. In order to provide a common platform for the FPGA developments at ESS - the ESS FPGA Framework has been designed. The framework facilitates the integration of different algorithms on different FPGA boards. Three functions are provided by the framework: (1) C"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"1803.09044","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}