{"paper":{"title":"Two FPGA Case Studies Comparing High Level Synthesis and Manual HDL for HEP applications","license":"http://creativecommons.org/licenses/by-nc-sa/4.0/","headline":"","cross_cats":["hep-ex"],"primary_cat":"physics.ins-det","authors_text":"T\\'etrault Marc-Andr\\'e","submitted_at":"2018-06-24T19:39:56Z","abstract_excerpt":"Real time data acquisition systems in nuclear science often rely on high-speed logic designs to reach the fast data rate requirements. They are mostly coded in a hardware description language (HDL). However, in recent years, high level synthesis (HLS) compilers have appeared, with the notable advantage that they rely on the widespread C/C++ syntax. This paper's aim is to outline differences between HDL and C/C++ HLS based designs for two real-time data acquisition modules used in nuclear science. The first module is a real-time crystal identification module, and the second is a compact event t"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"1806.10672","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}