{"paper":{"title":"A full-custom ASIC design of a 8-bit, 25 MHz, Pipeline ADC using 0.35 um CMOS technology","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":[],"primary_cat":"cs.AR","authors_text":"Affaq Qamar, Donatas Siaudinis, Imran Khan, Mikael Hogrud, Moslem Rashidi","submitted_at":"2010-11-18T09:12:50Z","abstract_excerpt":"The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of resolution where the only given ones. Although additional secondary goals such as low power consumption and small area were stated. The architecture is based on a 1.5 bit per stage structure utilizing digital correction for each stage [12]. A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200MHz ft is used for sampling and amplification in each stage [12]. Differential dynami"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"1011.4157","kind":"arxiv","version":2},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}