{"paper":{"title":"A 1.8-um pitch, 47-ps jitter SPAD Array in 130nm SiGe BiCMOS Process","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":[],"primary_cat":"physics.ins-det","authors_text":"Edoardo Charbon, Feng Liu","submitted_at":"2024-06-19T16:39:23Z","abstract_excerpt":"We introduce the world's first SPAD family design in 130 nm SiGe BiCMOS process. At 1.8um, we achieved the smallest pitch on record thanks to guard-ring sharing techniques, while keeping a relatively high fill factor of 24.2%. 4x4 SPAD arrays with two parallel selective readout circuits were designed to explore crosstalk and scalability. The SPAD family has a minimum breakdown voltage of 11 V, a maximum PDP of 40.6% and a typical timing jitter of 47 ps FWHM. The development of silicon SPADs in SiGe process paves the way to Ge-on-Si SPADs for SWIR applications, and to cryogenic optical interfac"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2406.13686","kind":"arxiv","version":2},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2406.13686/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}