{"paper":{"title":"Silicon Nanowires, Catalytic Growth and Electrical Characterization","license":"","headline":"","cross_cats":[],"primary_cat":"cond-mat.mtrl-sci","authors_text":"(2) Qimonda AG, 3), (3) Institute for Nanoelectronics, Andrew P. Graham (1), Caroline Cheze (1), Eugen Unger (2), Franz Kreupl (2) ((1) Qimonda Dresden, Georg S. Duesberg (1), Germany, Germany), Henning Riechert (2), Lutz Geelhaar (1), Maik Liebau (1), Neubiberg, Paolo Lugli (3), Technische Universitaet Muenchen, Walter M. Weber (1","submitted_at":"2006-09-13T07:33:33Z","abstract_excerpt":"Nominally undoped silicon nanowires (NW) were grown by catalytic chemical vapor deposition. The growth process was optimized to control the NWs diameters by using different Au catalyst thicknesses on amorphous SiO2, Si3N4, or crystalline-Si substrates. For SiO2 substrates an Ar plasma treatment was used to homogenize the catalyst coalescence, and thus the NWs diameter. Furthermore, planar field effect transistors (FETs) were fabricated by implementing 10 to 30 nm thin nominally undoped Si-NWs as the active region. Various silicides were investigated as Schottky-barrier source and drain contact"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"cond-mat/0609308","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}