{"paper":{"title":"Pulse Shaping to Mitigate the Impact of Device Imperfections in Field-Free Switching Using Combined Spin-Orbit and Spin-Transfer Torques","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"Shaping the STT pulse reduces write error rates and improves robustness in field-free SOT-STT switching of top-pinned devices.","cross_cats":["physics.app-ph"],"primary_cat":"cond-mat.mes-hall","authors_text":"Chlo\\'e Bouard, Gilles Gaudin, J\\'er\\'emie Vigier, Kuldeep Ray, Marc Drouard, Nicolas Lefoulon, Sylvain Martin","submitted_at":"2026-04-24T14:06:27Z","abstract_excerpt":"Combining spin-orbit (SOT) and spin-transfer torques (STT) provides a practical approach for field-free switching in spin-orbit torque magnetic random-access memory (SOT-MRAM), a prerequisite for industrial deployment, but can compromise reliability through phenomena such as backhopping, especially in top-pinned stacks commonly used for SOT-MRAM. We investigate the write error rate (WER) of combined SOT + STT switching in top-pinned devices that are not optimized for STT switching. Experiments reveal clear indications of STT-induced backhopping and a pronounced field-free SOT switching asymmet"},"claims":{"count":4,"items":[{"kind":"strongest_claim","text":"STT pulse shaping reduces WER and improves switching robustness in the presence of device imperfections.","source":"verdict.strongest_claim","status":"machine_extracted","claim_id":"C1","attestation":"unclaimed"},{"kind":"weakest_assumption","text":"The macrospin model using two coupled Landau-Lifshitz-Gilbert equations qualitatively reproduces the observed asymmetry and reveals an intermediate loss-of-determinism regime that guides effective mitigation.","source":"verdict.weakest_assumption","status":"machine_extracted","claim_id":"C2","attestation":"unclaimed"},{"kind":"one_line_summary","text":"Shaping the STT pulse reduces write error rates and improves robustness in field-free SOT+STT switching of imperfect top-pinned SOT-MRAM devices.","source":"verdict.one_line_summary","status":"machine_extracted","claim_id":"C3","attestation":"unclaimed"},{"kind":"headline","text":"Shaping the STT pulse reduces write error rates and improves robustness in field-free SOT-STT switching of top-pinned devices.","source":"verdict.pith_extraction.headline","status":"machine_extracted","claim_id":"C4","attestation":"unclaimed"}],"snapshot_sha256":"9927d9c7407f8f30808ff427be68d5d81bed12c411be846a516d3f954bd50858"},"source":{"id":"2604.22574","kind":"arxiv","version":1},"verdict":{"id":"00786ff6-131d-4d05-90fe-5dde02a7d0b5","model_set":{"reader":"grok-4.3"},"created_at":"2026-05-08T10:18:47.318537Z","strongest_claim":"STT pulse shaping reduces WER and improves switching robustness in the presence of device imperfections.","one_line_summary":"Shaping the STT pulse reduces write error rates and improves robustness in field-free SOT+STT switching of imperfect top-pinned SOT-MRAM devices.","pipeline_version":"pith-pipeline@v0.9.0","weakest_assumption":"The macrospin model using two coupled Landau-Lifshitz-Gilbert equations qualitatively reproduces the observed asymmetry and reveals an intermediate loss-of-determinism regime that guides effective mitigation.","pith_extraction_headline":"Shaping the STT pulse reduces write error rates and improves robustness in field-free SOT-STT switching of top-pinned devices."},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2604.22574/integrity.json","findings":[],"available":true,"detectors_run":[{"name":"ai_meta_artifact","ran_at":"2026-05-21T10:37:16.427541Z","status":"completed","version":"1.0.0","findings_count":0},{"name":"doi_compliance","ran_at":"2026-05-19T23:53:09.012733Z","status":"completed","version":"1.0.0","findings_count":0}],"snapshot_sha256":"215bef01e6915aa6eb96e9d095ef86d8bd3f6015f735122b8ec435ec4f3ebce2"},"references":{"count":4,"sample":[{"doi":"10.1109/tmscs.2015.2509963","year":2016,"title":"Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing","work_id":"508b6770-04f8-4b27-b11d-16b307c39331","ref_index":1,"cited_arxiv_id":"","is_internal_anchor":false},{"doi":"10.1088/0022-3727/46/7/074001","year":2013,"title":"Basic principles of STT-MRAM cell operation in memory arrays","work_id":"47e0142f-9274-4ac6-82df-899467297e06","ref_index":2,"cited_arxiv_id":"","is_internal_anchor":false},{"doi":"10.1109/iedm45741.2023.10413856","year":2023,"title":"Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling","work_id":"8a5f7074-c32a-4447-8e84-a3c275851ab5","ref_index":3,"cited_arxiv_id":"","is_internal_anchor":false},{"doi":"10.1063/1.4974885","year":2017,"title":"Seed Layer Impact on Structural and Magnetic Properties of [Co/Ni] Multilayers with Perpendicular Magnetic Anisotropy","work_id":"d39b6d42-8c6a-4390-8d89-6b182dd3e686","ref_index":4,"cited_arxiv_id":"","is_internal_anchor":false}],"resolved_work":4,"snapshot_sha256":"62ae0d569ee8dbd1e80eeb3919f07d34480dd7df8baaec00679c560894114b50","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}