{"paper":{"title":"Debug Like a Human: Scaling LLM-based Fault Localization to Processor Design via Block-Level Instruction-Oriented Slicing","license":"http://creativecommons.org/licenses/by/4.0/","headline":"BluesFL triples top-1 bug localization in large processor designs using block-level instruction slicing.","cross_cats":[],"primary_cat":"cs.SE","authors_text":"Deheng Yang, Guangda Zhang, Jiang Wu, Jianjun Xu, Jiayu He, Xiaoguang Mao, Yan Lei, Yihao Qin, Zizhen Liu","submitted_at":"2026-05-17T07:02:54Z","abstract_excerpt":"Fault localization in modern processor design code is a critical yet time-consuming step during processor verification. While recent advances in LLM-based techniques for module-level hardware design have shown promising results, automatically localizing bugs in large-scale, project-level processor designs remains challenging. In this paper, we present BluesFL, a novel block-level LLM-based fault localization framework for processor designs. Inspired by the way engineers debug processors, we first propose a dataflow-based code blockization approach to guide LLMs to focus on critical local code "},"claims":{"count":4,"items":[{"kind":"strongest_claim","text":"BluesFL correctly localizes 24 bugs at Top-1 on a real-world RISC-V processor core comprising 19K lines of SystemVerilog code, achieving 242.9% improvement over the existing state-of-the-art (7 bugs).","source":"verdict.strongest_claim","status":"machine_extracted","claim_id":"C1","attestation":"unclaimed"},{"kind":"weakest_assumption","text":"The dataflow-based blockization and Block-Level Instruction-Oriented Slicing (Blues) algorithm are assumed to provide the critical local context that enables LLMs to mimic human debugging reasoning effectively; this premise is invoked in the description of the approach but its validity rests on the specific implementation details and prompt engineering not visible in the abstract.","source":"verdict.weakest_assumption","status":"machine_extracted","claim_id":"C2","attestation":"unclaimed"},{"kind":"one_line_summary","text":"BluesFL uses block-level instruction-oriented slicing with LLMs to localize 24 bugs at Top-1 in a 19K-line RISC-V processor, a 242.9% gain over prior SOTA of 7 bugs.","source":"verdict.one_line_summary","status":"machine_extracted","claim_id":"C3","attestation":"unclaimed"},{"kind":"headline","text":"BluesFL triples top-1 bug localization in large processor designs using block-level instruction slicing.","source":"verdict.pith_extraction.headline","status":"machine_extracted","claim_id":"C4","attestation":"unclaimed"}],"snapshot_sha256":"f4f6755d882b2f3bdab0c196a419cad9e087be711477eb45cef2efd3bff43188"},"source":{"id":"2605.17290","kind":"arxiv","version":1},"verdict":{"id":"9d6b97b0-55ce-405d-a830-de9337e5ab56","model_set":{"reader":"grok-4.3"},"created_at":"2026-05-19T22:51:51.565150Z","strongest_claim":"BluesFL correctly localizes 24 bugs at Top-1 on a real-world RISC-V processor core comprising 19K lines of SystemVerilog code, achieving 242.9% improvement over the existing state-of-the-art (7 bugs).","one_line_summary":"BluesFL uses block-level instruction-oriented slicing with LLMs to localize 24 bugs at Top-1 in a 19K-line RISC-V processor, a 242.9% gain over prior SOTA of 7 bugs.","pipeline_version":"pith-pipeline@v0.9.0","weakest_assumption":"The dataflow-based blockization and Block-Level Instruction-Oriented Slicing (Blues) algorithm are assumed to provide the critical local context that enables LLMs to mimic human debugging reasoning effectively; this premise is invoked in the description of the approach but its validity rests on the specific implementation details and prompt engineering not visible in the abstract.","pith_extraction_headline":"BluesFL triples top-1 bug localization in large processor designs using block-level instruction slicing."},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2605.17290/integrity.json","findings":[],"available":true,"detectors_run":[{"name":"doi_compliance","ran_at":"2026-05-19T23:01:54.171489Z","status":"completed","version":"1.0.0","findings_count":0},{"name":"doi_title_agreement","ran_at":"2026-05-19T23:01:19.690436Z","status":"completed","version":"1.0.0","findings_count":0},{"name":"claim_evidence","ran_at":"2026-05-19T22:01:57.815423Z","status":"completed","version":"1.0.0","findings_count":0},{"name":"ai_meta_artifact","ran_at":"2026-05-19T21:33:23.766888Z","status":"skipped","version":"1.0.0","findings_count":0}],"snapshot_sha256":"a4861b773651adfcb4644fa1c78b17318ce5a5f84bae7a09cd8c46f1957dc581"},"references":{"count":30,"sample":[{"doi":"","year":2025,"title":"2025. CoreMark. https://github.com/lowRISC/ibex/tree/master/examples/sw/ benchmarks/coremark","work_id":"fbd947d5-7df2-4e14-abbe-76e0e1a91444","ref_index":1,"cited_arxiv_id":"","is_internal_anchor":false},{"doi":"","year":2025,"title":"2025. cva6. https://github.com/openhwgroup/cva6","work_id":"f7d5db88-20ae-4dae-9af8-d5bac16eb344","ref_index":2,"cited_arxiv_id":"","is_internal_anchor":false},{"doi":"","year":2025,"title":"2025. Ibex. https://github.com/lowRISC/ibex","work_id":"a676a20f-4318-4819-9386-caac772b3fef","ref_index":3,"cited_arxiv_id":"","is_internal_anchor":false},{"doi":"","year":2025,"title":"Rocket Chip Generator","work_id":"5f46f57e-7ae7-49ec-8a68-ca07961fc8f5","ref_index":4,"cited_arxiv_id":"","is_internal_anchor":false},{"doi":"","year":2025,"title":"2025. sv-parser. https://github.com/dalance/sv-parser","work_id":"e0980edf-bf55-451b-820c-0c99215235fb","ref_index":5,"cited_arxiv_id":"","is_internal_anchor":false}],"resolved_work":30,"snapshot_sha256":"296b4f94c8179da2967acabd9e9e0b4811273cf99e076072b1d7bfcbda9d9d95","internal_anchors":1},"formal_canon":{"evidence_count":2,"snapshot_sha256":"63a19878cc7a5d7c48200d26937cb594f8751fdc7f6e41503fad82f420676ea6"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}