{"id":"2e8ef742-56c3-45e1-b8bb-8a1eb9cd610c","arxiv_id":"1907.02968","paper_version":1,"verdict":"UNVERDICTED","confidence":"LOW","novelty_score":3.0,"correctness_risk":"low","formal_verification":"none","parameter_count":0,"one_line_summary":"Prototype data and clock transmission interface for LHAASO WCDA using White Rabbit switches achieves clock synchronization better than 50 ps and data throughput of 400 Mbps per FEE board.","lead":"The paper reports a prototype using White Rabbit switches to send clock signals, data, and commands over a single 400-meter fiber for the WCDA detector array. This meets the 0.5 ns timing and high-speed data needs of a large triggerless readout system.","discovery_kind":"new_application","skeptic_critique":{"model":"grok-4.3","headline":"Prototype tests with 1-4 boards over single 400 m links may not capture jitter or contention under full 3600-FEE triggerless load across distributed WR network.","rationale":"The reader's weakest assumption directly identifies the scaling gap; the full-text prototype results do not close it. This moves the verdict from UNVERDICTED to CONDITIONAL pending larger-scale validation, while preserving the low correctness risk on the prototype itself.","tokens_in":1794,"tokens_out":272,"duration_ms":14046,"concrete_test":"Re-run the reported sync and throughput tests with ≥16 FEE boards sharing uplink ports, multiple WR switches, and injected data at the expected WCDA triggerless rate; confirm whether sync remains <50 ps and throughput holds without degradation.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The central claims (clock sync <50 ps RMS; 400 Mbps single-board and 180 Mbps shared-port throughput) rest on laboratory measurements of a small prototype. The full WCDA requires 3600 PMTs/FEEs over 90,000 m² with continuous triggerless data, multiple WR switches, and realistic hit rates. No data are shown for multi-hop topologies, aggregate traffic scaling, or event-driven load that could degrade synchronization or saturate uplink ports.","agreement_with_reader":"agree"},"referee_report":{"model":"grok-4.3","summary":"The manuscript presents a prototype data and clock transmission interface for the WCDA component of LHAASO. It uses White Rabbit switches to distribute clock, data, and commands over ~400 m single-mode fiber links to FEE boards. Laboratory tests on 1–4 boards are reported to achieve clock synchronization better than 50 ps RMS and throughputs of 400 Mbps (single board) and 180 Mbps (four boards sharing an uplink), stated to exceed WCDA requirements for 0.5 ns RMS timing and triggerless readout of 3600 PMTs over 90 000 m².","tokens_in":1883,"tokens_out":501,"duration_ms":13637,"significance":"If the reported prototype performance holds under full-scale conditions, the design would provide a compact, fiber-based solution consistent with the rest of LHAASO that simultaneously satisfies the stringent timing and continuous high-rate data-transfer needs of a large water-Cherenkov array. The work directly addresses a practical engineering requirement for the experiment.","major_comments":[{"comment":"Abstract and test-results section: the central claim that clock synchronization precision is better than 50 ps RMS is stated without any description of the measurement method, reference clock source, calibration procedure, number of samples, or statistical treatment used to obtain the RMS value. This absence prevents independent assessment of the quoted figure.","section":"Abstract / test section"},{"comment":"Results on throughput and synchronization: all reported measurements use only 1–4 FEE boards on single 400 m links. No data, scaling analysis, or simulation are provided for the full 3600-board triggerless load, multi-hop WR topologies, or aggregate traffic that will exist across the 90 000 m² array; the extrapolation from the small prototype therefore remains untested.","section":"Results / performance tests"}],"minor_comments":[{"comment":"The manuscript should include a short table or paragraph listing the exact hit-rate assumptions and packet sizes used to calculate the 400 Mbps and 180 Mbps figures.","section":null},{"comment":"Figure captions and axis labels for any timing histograms or throughput plots should explicitly state the measurement conditions (fiber length, number of boards, data pattern).","section":null}],"recommendation":"major_revision","confidential_remarks":null},"author_rebuttal":{"model":"grok-4.3","summary":"We thank the referee for the constructive comments and the positive assessment of the work's significance. We respond to each major comment below.","responses":[{"response":"We agree that the abstract and test-results section lack a description of the measurement method, reference clock source, calibration procedure, number of samples, and statistical treatment for the 50 ps RMS figure. Although the performance tests section of the manuscript contains the relevant experimental setup, we will revise the manuscript to add a concise description of these details to the test-results section and update the abstract for clarity.","revision_made":"yes","referee_comment":"[Abstract / test section] Abstract and test-results section: the central claim that clock synchronization precision is better than 50 ps RMS is stated without any description of the measurement method, reference clock source, calibration procedure, number of samples, or statistical treatment used to obtain the RMS value. This absence prevents independent assessment of the quoted figure."},{"response":"The manuscript presents prototype results using 1–4 FEE boards, as stated in the test section. We do not provide data, scaling analysis, or simulation for the full 3600-board system or multi-hop topologies. The paper's scope is limited to validating the interface design and per-link performance against WCDA requirements; full-array deployment details are outside this prototype study. We can add a brief discussion of expected scaling based on White Rabbit specifications.","revision_made":"partial","referee_comment":"[Results / performance tests] Results on throughput and synchronization: all reported measurements use only 1–4 FEE boards on single 400 m links. No data, scaling analysis, or simulation are provided for the full 3600-board triggerless load, multi-hop WR topologies, or aggregate traffic that will exist across the 90 000 m² array; the extrapolation from the small prototype therefore remains untested."}],"tokens_in":1432,"tokens_out":414,"duration_ms":27946,"standing_objections":[]},"desk_editor":{"model":"grok-4.3","letter":"The main point is that the authors built and tested a data/clock interface using White Rabbit switches and single 400 m fibers for the LHAASO WCDA FEE boards. In their prototype runs the clock sync came in under 50 ps and throughput hit 400 Mbps single-board or 180 Mbps shared, which clears the experiment's requirements for 0.5 ns RMS timing and triggerless readout.","headline":"This reports a working White Rabbit prototype for WCDA timing and data that meets the stated specs in small-scale lab tests, but the scaling evidence is limited to 1-4 boards.","tokens_in":2358,"tokens_out":165,"would_cite":false,"duration_ms":13842,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":{"model":"grok-4.3","evidence":[],"headline":"Prototype WR-based clock/data interface for LHAASO WCDA detector readout; no RS machinery","alignment":"orthogonal","rationale":"Paper describes engineering implementation of White Rabbit clock synchronization (<50 ps RMS) and TCP/IP data transfer (400/180 Mbps) over 400 m fiber for 3600-PMT WCDA array. Central components (GTP SerDes, WRPC, SiTCP, PLL phase adjustment, DDR3 buffering) are standard detector electronics; no J-cost, φ-ladder, 8-tick periodicity, ratio-symmetric forcing, or parameter-free constant derivations appear. Matches none of the RS forcing chain (reality_from_one_distinction, AbsoluteFloorClosure, AlexanderDuality, Cost.FunctionalEquation, etc.). Domain is applied instrumentation; RS has no opinion.","tokens_in":46244,"confidence":"high","tokens_out":183,"duration_ms":4411,"cache_read_input_tokens":38528,"cache_creation_input_tokens":0},"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"grok-4.3","headline":"A prototype using White Rabbit switches achieves clock synchronization better than 50 ps and data throughput sufficient for the LHAASO WCDA detector array.","keywords":["White Rabbit","clock synchronization","data transmission","LHAASO WCDA","front end electronics","photomultiplier tubes","triggerless readout"],"falsifier":"A measurement showing clock synchronization worse than 50 ps or data throughput below requirements when the full complement of 3600 boards operates with realistic triggerless data traffic over the complete array.","tokens_in":2696,"feed_emoji":"","tokens_out":646,"duration_ms":22026,"temperature":0.7,"pith_summary":"This paper presents a data and clock transmission interface prototype for the Water Cherenkov Detector Array component of LHAASO. The design distributes a precise clock and handles high-speed data from 3600 photomultiplier tubes spread over 90,000 square meters using White Rabbit switches over single fibers. Laboratory tests demonstrate clock precision better than 50 picoseconds and data rates up to 400 megabits per second per front-end board. These results support the 0.5 nanosecond RMS timing requirement in a triggerless readout system. The approach simplifies the electronics by combining clock, data, and commands on one fiber while matching the broader LHAASO architecture.","feed_headline":"White Rabbit achieves sub-50 ps clock sync in LHAASO prototype","feed_subtitle":"Data rates hit 400 Mbps per board to support triggerless readout of 3600 PMTs","key_machinery":"White Rabbit switches used to transfer clock, data, and commands via a single fiber of about 400 meters.","core_discovery":"The prototype of the data and clock transmission interface achieves a clock synchronization precision better than 50 ps. The data transmission throughput reaches 400 Mbps for one FEE board and 180 Mbps for 4 FEE boards sharing one uplink port in the WR switch, exceeding the requirements of the LHAASO WCDA.","pith_inferences":["Performance in the full 3600-board deployment may differ from lab tests due to increased network load and fiber lengths.","This single-fiber synchronization method could apply to other distributed sensor arrays needing high timing precision.","TCP/IP protocol integration allows use of standard network tools for data management."],"forward_implications":["Precise clock distribution enables 0.5 ns RMS time measurements across the detector array.","High data throughput supports triggerless data acquisition from all PMTs.","Single fiber transmission reduces cabling complexity in the large area deployment.","The design maintains consistency with other LHAASO readout systems."],"fun_headline_variants":["Under 50 ps clock sync via White Rabbit in WCDA prototype","400 Mbps data transmission for single FEE in WCDA prototype","Clock and data over single 400 m fiber in LHAASO WCDA","Better than 50 ps timing with White Rabbit for LHAASO WCDA","180 Mbps data rate for four FEE boards on WR uplink"],"cache_read_input_tokens":2112,"weakest_assumption_plain":"The performance measured in laboratory conditions with single 400 m fiber links and a limited number of boards will hold when the system is scaled to 3600 PMTs and FEEs over the full 90,000 m2 area under actual triggerless data loads.","fun_headline_variants_meta":{"raw":{"variants":["Under 50 ps clock sync via White Rabbit in WCDA prototype","400 Mbps data transmission for single FEE in WCDA prototype","Clock and data over single 400 m fiber in LHAASO WCDA","Better than 50 ps timing with White Rabbit for LHAASO WCDA","180 Mbps data rate for four FEE boards on WR uplink"]},"model":"grok-4.3","cost_usd":0.008118,"raw_usage":{"total_tokens":3618,"prompt_tokens":688,"num_sources_used":0,"completion_tokens":93,"cost_in_usd_ticks":81178000,"prompt_tokens_details":{"text_tokens":688,"audio_tokens":0,"image_tokens":0,"cached_tokens":64},"completion_tokens_details":{"audio_tokens":0,"reasoning_tokens":2837,"accepted_prediction_tokens":0,"rejected_prediction_tokens":0}},"tokens_in":688,"tokens_out":93,"duration_ms":16814,"temperature":1.0,"reasoning_tokens":2837,"cache_read_input_tokens":64,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-05-25T02:00:30.319688+00:00","model_set":{"reader":"grok-4.3"},"falsifier":"A measurement showing clock synchronization worse than 50 ps or data throughput below requirements when the full complement of 3600 boards operates with realistic triggerless data traffic over the complete array.","supporting_citations":[],"review_version":1}