{"id":"c7e1bfa2-52d8-4643-b2c5-8e34cbadba9c","arxiv_id":"1908.01163","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"A 64-channel mixed-signal ASIC for high-capacitance gaseous detectors is fabricated and characterized, reaching a 400 fC range, 3500-electron noise at 100 pF, and about 4 ns jitter, with an unexplained noise offset.","lead":"This paper presents a fabricated 64-channel microchip that reads out signals from gas-based particle detectors with high capacitance. It reports electrical measurements showing wide programmable gain and a 400 fC input range, with some known mismatches to simulation.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Measured support for the 'hundreds of pF' headline stops at 100 pF; the 500 pF capability rests only on a simplified stability simulation, so the detector-capacitance claim of the abstract is not yet established by data.","rationale":"Good-faith reading: this is a standard ASIC characterization paper. The central claim is not merely that a chip was designed, but that the fabricated 64-channel chip is suitable for high-capacitance gaseous detectors. The measured results at 100 pF, the transistor-level design details, and the fabricated prototype are real evidence. However, the headline differentiator — operation 'up to hundreds of pF' — is the least supported part of the central claim. The paper explicitly reports the measurements only up to 100 pF. The high-C support consists of a simplified stability simulation, not measured performance, and the paper itself documents 20% noise excess and an unexplained jitter offset versus simulation in the measured range. A reader should therefore not take 'hundreds of pF' as an established measured capability. This is a scope-of-evidence concern, not an internal inconsistency or a suggestion of misconduct. The proposed test is a direct extension of the existing setup and would settle whether the high-C claim is quantitative fact or design aspiration. This does not move the reader's CONDITIONAL verdict; it reinforces it.","tokens_in":9676,"tokens_out":9470,"duration_ms":91036,"concrete_test":"Run the existing test-bench characterization (external capacitor in parallel with the input, same on-chip or C-R charge injection) at C_in = 200, 350, and 500 pF, and report ENC, timing jitter at 14 fC, and S&H INL at the lowest gain setting. If the 500 pF points follow the post-layout simulation and INL remains below 1% over the tested charge range, the 'hundreds of pF' claim is supported; if not, the conclusion should be softened to 'designed for hundreds of pF' pending further characterization.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The abstract and title claim suitability for detector capacitances 'up to hundreds of pF,' but the fabricated-chip data only cover C_in = 0-100 pF. ENC (Fig. 15), timing jitter (Fig. 16) and the Table 5 summary are all quoted at 100 pF; no measured ENC, jitter, gain, or INL is reported for 200, 350, or 500 pF. The only >100 pF evidence is Table 3, a stability simulation of a simplified schematic (Fig. 4) using A0=50, tau_R=2ns, Cgs1=1pF and an ideal current source. That is not a full post-layout verification. This matters because C_d enters the input pole directly (Eq. 3.9: tau_i=C_d/(A g_m1)) and the stability boundaries (Eqs. 3.15-3.16) are exactly the quantities that change at high C_d. Moreover, Section 6 reports measured noise 20% above post-layout simulation and an unexplained systematic jitter offset in the 0-100 pF range, so simulation-based extrapolation from 100 to 500 pF lacks an empirical anchor. The synthetic-pulse limitation is real but secondary; the missing high-C measurement is the load-bearing gap.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports the design and electrical characterization of a 64-channel mixed-mode ASIC for the readout of gaseous detectors (GEM, MicroMEGAS, MWPC). Each channel contains a regulated common-gate (RCG) preamplifier with programmable gain, a fast timing shaper with discriminator, a slow energy shaper, a TDC based on analog interpolation, and charge measurement by Sample-and-Hold or Time-over-Threshold. The authors derive the RCG transfer function and stability conditions, describe the shaper and digitizer circuits, and present test results from a fabricated 110 nm CMOS chip. Measured results include programmable gain from roughly 1.2 to 9.7 mV/fC, S&H INL below 1% up to 300 fC, ENC of about 3500 e- at 100 pF input capacitance, timing jitter of about 4 ns at 14 fC with 100 pF, and power consumption near 9 mW per channel. The paper claims suitability for detector capacitances up to hundreds of pF, based on circuit analysis and stability simulations up to 500 pF, while the direct measurements are limited to 0-100 pF.","tokens_in":9939,"tokens_out":4359,"duration_ms":43172,"significance":"If the stated results hold, this is a useful prototype front-end for high-capacitance gaseous detectors, and the architecture combines features (RCG input, dual shapers, TDC, S&H/ToT) that are relevant to the BESIII CGEM and similar upgrades. The strengths of the paper are that the key performance numbers (gain, ENC, jitter, INL, power) come from direct measurements of a fabricated chip, not from fitting parameters, and that the measured data are compared with post-layout simulations. The paper is also transparent about known discrepancies, such as the 20% noise excess and the unexplained jitter offset. However, the headline capability for \"hundreds of pF\" detector capacitance is not supported by measured data, and the minimum-gain setting that enables the 400 fC dynamic range shows significant gain mismatch and INL. These gaps are load-bearing for the main claims and should be addressed before acceptance.","major_comments":[{"comment":"The abstract and Table 1 claim operation with detector capacitance \"up to hundreds of pF\", but the electrical characterization in §6 is limited to input capacitances of 0–100 pF: ENC in Fig. 15, jitter in Fig. 16, and the Table 5 summary are all quoted at 100 pF. The 350 pF and 500 pF entries in Table 3 come from a stability simulation of the simplified schematic of Fig. 4 using an ideal current source and parameters A0=50, τ_R=2 ns, Cgs1=1 pF, not from post-layout simulation or from measurements. Because the measured noise exceeds post-layout simulation by 20% and the jitter model of Eq. (6.1) shows a systematic unexplained offset, a simulation-only extrapolation from 100 pF to 500 pF lacks an empirical anchor. Please provide measurements at 200 pF, 350 pF, or 500 pF, or revise the claim to state that the verified range is 0–100 pF with stability simulation only beyond that range.","section":"§6, Table 4"},{"comment":"The minimum-gain setting (set8), which is the setting that reaches the headline 400 fC dynamic range, has 12.03% gain mismatch and 2.78% INL, and the text attributes this to PMOS devices in the output stage entering the linear region. Since set8 is the setting that provides the largest charge range, the measured \"dynamic range up to 400 fC\" claim is currently supported only with a caveat that a design fix is required. The paper should report the offline-calibrated INL over the full 400 fC range, or explicitly state the dynamic range as the region where the uncalibrated INL remains below 1%.","section":"§6, Eq. (6.1)"},{"comment":"The jitter comparison in Fig. 16 shows a systematic offset of about 440 e- r.m.s. between measured and simulated timing jitter, and the authors state that the cause is not fully understood. Timing resolution is a central performance parameter (4 ns at 14 fC and 100 pF in Table 5), so the predictive model used to extrapolate to other operating points is not validated. Please provide a quantitative investigation of this offset (for example, discriminator threshold noise, digital interference, or time-walk effects) or report jitter with an explicit systematic-error band.","section":"§6"}],"minor_comments":[{"comment":"In the jitter discussion, the \"440 e− r.m.s.\" offset is dimensionally an input-referred charge noise, while Fig. 16 shows time jitter in ns; please clarify the quantity and how it is converted from time to charge units.","section":"§6"},{"comment":"Figure 15 contains duplicated χ²/ndf labels with two sets of fit parameters superimposed; please clean the figure so that only the correct fit results are shown.","section":"Table 4"},{"comment":"In Table 4, the columns \"Gain Test\" and \"Gain Simulated\" lack explicit units and a definition of the mismatch percentage; please specify the measurement method (fast-shaper peak amplitude per injected charge) and the mismatch formula.","section":"§5"},{"comment":"Reference [7] appears in the bibliography but is not cited in the text; the description of the four S&H buffers for event de-randomisation in §5 should cite it.","section":"Eqs. (3.15)-(3.16)"},{"comment":"The text says that complex-conjugate roots are avoided for very small or very large Cd, but complex-conjugate poles are not necessarily unstable; the phase-margin simulation in Table 3 is the more relevant stability metric, so the wording should be aligned.","section":"Abstract and Table 5"},{"comment":"The abstract states power consumption \"less than 9 mW/channel\", Table 5 reports \"9 mW/ch\", and Table 1 reports \"<10 mW/ch\"; please unify these values.","section":"§6"},{"comment":"Figures 17 and 18 report data from \"63ch\" and \"62ch\" without explanation; please state whether one or more channels were excluded from the analysis and why.","section":"§6"},{"comment":"The characterization uses injected test pulses rather than real gaseous-detector signals; please state explicitly how the C-R test-pulse injection represents the current-source-plus-capacitance detector model, since interconnection parasitics and the actual detector current waveform could affect the measured performance.","section":"§6"}],"recommendation":"major_revision","confidential_remarks":"The manuscript is within the scope of JINST as a prototype ASIC paper, and the authors are transparent about the TIGER IP reuse. The main obstacle is the mismatch between the abstract claim of \"hundreds of pF\" input capacitance and the measured 0–100 pF range; this can be fixed either by additional measurements or by a revised claim. The gain-mismatch and jitter-offset issues are also fixable with additional analysis or with a more cautious presentation. No concerns about citation patterns or novelty disclosure."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Read the ASIC paper. The bottom line is that this is a real engineering effort: a fabricated 64-channel front-end in 110 nm CMOS with a regulated common-gate preamp, two shapers, TDCs, ADCs, and S&H/ToT charge measurement modes. The electrical characterization is largely convincing: gain settings follow the expected pattern, INL is below 1% up to 300 fC, ENC at 100 pF is about 3500 e-, and the timing jitter is around 4 ns for 14 fC into 100 pF. The authors are also honest about the two clear defects—the 12% gain mismatch at the minimum gain setting and the INL degradation above 300 fC—and they propose a cascode fix. That is the right way to report a first prototype.\n\nThe soft spot is the abstract's 'high capacitance up to hundreds of pF' claim. Every measured point in the paper stops at 100 pF. The only support beyond that is a stability simulation of a simplified schematic (Table 3), and the transfer-function analysis shows exactly why that is not enough: the input pole and the stability boundaries depend directly on C_d. The measured noise also sits 20% above post-layout simulation, and the timing jitter shows a systematic offset that the authors do not fully explain. So a simulation-based extrapolation to 500 pF has no empirical anchor. The tests also used injected pulses with an external capacitor rather than a real gaseous detector, which is fine for an electrical characterization but does not establish detector compatibility.\n\nThis is not a fatal flaw. The chip works, the data are real, and the discrepancies are acknowledged. But the authors should either measure at a few hundred pF or soften the claimed input-capacitance range. If the 'hundreds of pF' statement stays in the abstract, it needs at least one measured point above 100 pF.\n\nI would send this to peer review. It is a prototype ASIC paper with reproducible measurements and a clear architecture, and the limitations are mostly stated. The referee should ask for the high-capacitance measurement or a revised claim, and for a comment on the unexplained offsets. I would not cite the high-C claim in my own work; the noise analysis is standard, and the measured 100 pF numbers are useful but not a result I need.","headline":"Real ASIC with solid 100 pF data; the 'hundreds of pF' headline is only supported by a simplified stability simulation.","tokens_in":10514,"tokens_out":2981,"would_cite":false,"duration_ms":30299,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A 64-channel CMOS chip reports under 1% charge nonlinearity to 300 fC, 3500-electron noise at 100 pF, and 4 ns jitter at 14 fC for high-capacitance gaseous detectors.","keywords":["regulated common-gate","mixed-signal ASIC","high dynamic range","high detector capacitance","gaseous detectors","time-to-digital converter","sample-and-hold","time-over-threshold"],"falsifier":"Mount the chip on a real GEM, MicroMEGAS, or MWPC detector and compare the reconstructed charge and timing for known deposited charges with the injected-pulse results at the same input capacitance; if the real-detector integral nonlinearity exceeds 1% or the jitter at 14 fC with 100 pF exceeds 4 ns, the synthetic current-pulse-plus-capacitor test model is missing something.","tokens_in":9477,"feed_emoji":"⚛️","tokens_out":10710,"duration_ms":96865,"temperature":0.7,"pith_summary":"The paper reports the design and electrical characterization of a 64-channel front-end chip for gaseous particle detectors whose capacitance can reach hundreds of picofarads. Each channel amplifies the detector current with a low-impedance regulated common-gate input, shapes it in fast and slow branches, and digitizes both the arrival time and the charge, so the chip delivers a fully digital event stream. The measurements show a programmable charge range up to 400 fC, an integral non-linearity below 1% up to 300 fC, an equivalent noise charge of about 3500 electrons at 100 pF input capacitance, and 4 ns timing jitter at 14 fC, at under 9 mW per channel. If these results carry over to real detectors, the chip is a plausible single-chip readout for GEM, MicroMEGAS, and MWPC detectors, saving external ADC and TDC circuitry.","feed_headline":"64-channel chip reads gas-detector charges up to 400 fC","feed_subtitle":"Prototype ASIC reports under 1% nonlinearity to 300 fC and 4 ns timing jitter at 14 fC.","key_machinery":"The load-bearing element is the regulated common-gate (RCG) current conveyor: a common-gate input transistor whose transconductance is boosted by a common-source amplifier of open-loop gain $A$. The input impedance becomes $Z_{in}=1/(A g_{m1})$, and the input pole is $\\tau_i=C_d/(A g_{m1})$, so the pole is $A$ times higher than in a plain common-gate stage, which is what makes very large detector capacitance manageable. A stability analysis of the second-order transfer function shows that the circuit avoids complex-conjugate poles for very small and very large $C_d$, the regime where a transimpedance amplifier can become unstable, so the RCG is presented as the reason the chip can be specified for detectors with tens to hundreds of picofarads of capacitance.","core_discovery":"The paper's central claim is that a regulated common-gate (RCG) pre-amplifier lets a CMOS front-end keep a stable, fast, low-noise response while the detector capacitance is large, tens to hundreds of picofarads, and that the rest of the chain, fast and slow shapers, discriminators, TDCs, ADCs, and two charge-measurement modes, fits in 64 parallel channels at under 9 mW per channel. The fabricated 110 nm CMOS chip was characterized by injecting test pulses through an external capacitor, and the measurements show a programmable range up to 400 fC, an integral non-linearity below 1% up to 300 fC, an equivalent noise charge of about 3500 electrons at 100 pF, and 4 ns r.m.s. timing jitter at 14 fC with 100 pF. The paper also reports a roughly 20% excess noise over simulation, a not-fully-understood systematic jitter offset, and a minimum-gain nonlinearity that it attributes to PMOS output-stage modulation and proposes to fix with a cascoded output stage. The intended application is a single-chip digital readout for GEM, MicroMEGAS, and MWPC detectors.","pith_inferences":["A direct measurement at 200–500 pF input capacitance would test the 'hundreds of pF' claim, which is currently supported only by stability simulations up to 500 pF.","The same RCG input stage could in principle be reused for other high-capacitance sensors, such as large-area silicon strip detectors, since the input-pole and stability arguments do not depend on gaseous detectors specifically.","Combining sample-and-hold below 300 fC with calibrated time-over-threshold above it could give one channel both linearity and the full 400 fC range."],"forward_implications":["Because each channel produces a fully digital payload with channel ID, time stamp, and charge, a detector readout built around this chip would not need separate external TDC and ADC boards.","The programmable gain and input impedance let one chip design serve GEM, MicroMEGAS, and MWPC detectors, whose capacitance and charge ranges differ.","The 40 ps TDC binning is small enough that the digitization contributes negligibly to the front-end's intrinsic time resolution at 50 fC.","The sample-and-hold path gives linear charge readout below 300 fC; the time-over-threshold path extends the usable range to 400 fC at the cost of a nonlinear calibration.","The RCG input's stability in the high-capacitance regime is what allows the 'hundreds of pF' operating point, which a conventional transimpedance amplifier could not reach without instability."],"supporting_citations":[{"why":"Defines the detector model as a current pulse in parallel with capacitance and is the reference for the transimpedance-amplifier instability comparison.","marker":"[2]"},{"why":"Documents the prior ASIC whose TDCs, DACs, and control logic are reused, providing the design baseline.","marker":"[5]"},{"why":"Supplies the analogue time-interpolation TDC architecture used in this chip.","marker":"[6]"},{"why":"Establishes the regulated common-gate topology that gives the low input impedance needed for high capacitance.","marker":"[8]"},{"why":"Provides the class-AB shaper output stage design and high-dynamic-range shaper methodology.","marker":"[9]"},{"why":"Reference shaper and discriminator front-end implementation for micropattern detectors that the shaper core follows.","marker":"[10]"},{"why":"Defines the baseline-holder circuit that sets the shaper output baseline.","marker":"[11]"}],"fun_headline_variants":["400 fC dynamic range in a low-power 64-channel ASIC","Detector chip: 100 pF capacitance, 1% nonlinearity","64-channel front-end: 400 fC range, 3500 e- noise","ASIC for gas detectors: 400 fC, 4 ns jitter at 14 fC"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The chip was characterized with synthetic test pulses injected through an external capacitor rather than with real gaseous-detector signals, so the quoted performance is assumed to transfer to actual detector events with their real current waveforms and parasitics.","fun_headline_variants_meta":{"raw":{"variants":["400 fC dynamic range in a low-power 64-channel ASIC","Detector chip: 100 pF capacitance, 1% nonlinearity","64-channel front-end: 400 fC range, 3500 e- noise","ASIC for gas detectors: 400 fC, 4 ns jitter at 14 fC"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001015,"raw_usage":{"total_tokens":4316,"prompt_tokens":1008,"completion_tokens":3308,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":624,"completion_tokens_details":{"reasoning_tokens":3218}},"tokens_in":624,"tokens_out":3308,"duration_ms":26614,"temperature":1.0,"reasoning_tokens":3218,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T15:21:45.699998+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Mount the chip on a real GEM, MicroMEGAS, or MWPC detector and compare the reconstructed charge and timing for known deposited charges with the injected-pulse results at the same input capacitance; if the real-detector integral nonlinearity exceeds 1% or the jitter at 14 fC with 100 pF exceeds 4 ns, the synthetic current-pulse-plus-capacitor test model is missing something.","supporting_citations":[{"cited_title":"CMOS: front-end electronics for radiation sensors[M]","cited_arxiv_id":null,"evidence_quote":"Defines the detector model as a current pulse in parallel with capacitance and is the reference for the transimpedance-amplifier instability comparison."},{"cited_title":"A custom readout electronics for the BESIII CGEM detector","cited_arxiv_id":null,"evidence_quote":"Documents the prior ASIC whose TDCs, DACs, and control logic are reused, providing the design baseline."},{"cited_title":"A pixel front-end ASIC in 0.13 um CMOS for the NA62 experiment with on pixel 100 ps time-to-digital converter","cited_arxiv_id":null,"evidence_quote":"Supplies the analogue time-interpolation TDC architecture used in this chip."},{"cited_title":"A low-noise CMOS front-end for TOF-PET","cited_arxiv_id":null,"evidence_quote":"Establishes the regulated common-gate topology that gives the low input impedance needed for high capacitance."},{"cited_title":"Shaper Design in CMOS for High Dynamic Range","cited_arxiv_id":null,"evidence_quote":"Provides the class-AB shaper output stage design and high-dynamic-range shaper methodology."},{"cited_title":"VMM1-AnASICforMicropatternDetectors","cited_arxiv_id":null,"evidence_quote":"Reference shaper and discriminator front-end implementation for micropattern detectors that the shaper core follows."},{"cited_title":"A CMOS Baseline Holder (BLH) for Readout ASICs","cited_arxiv_id":null,"evidence_quote":"Defines the baseline-holder circuit that sets the shaper output baseline."}],"review_version":1}