{"id":"c1bd54f9-640f-4376-93ab-a2b05d10244d","arxiv_id":"1908.01466","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"The authors integrate a parameterized posit FPU into a SHAKTI RISC-V core, claim the first posit-enabled RISC-V processor, and report accuracy benefits over IEEE-754 in selected applications.","lead":"This paper presents PERI, which integrates a posit floating-point unit into an open RISC-V core, and reports FPGA area and application results. It also adds run-time switching between two posit exponent sizes in the same hardware.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 'first Posit RISC-V core' claim rests on unpublished RTL whose dynamic es=2/3 switching and RoCC integration paths are never validated; this is the load-bearing gap.","rationale":"The reader's CONDITIONAL verdict is appropriate. The design is plausible, the pseudocode is detailed, and the synthesis numbers are concrete, so the paper deserves credit for a substantial implementation effort. However, the 'first posit RISC-V core' claim is an existence claim about a complete, working processor, and the evidence in §V-C only covers FPU operations at es=2 against SoftPosit plus special cases for both es values; dynamic switching and RoCC integration are asserted rather than demonstrated. No RTL or testbench is released, so the core-level and accelerator-level behavior cannot be independently checked. This is not a reason to reject the work; it is a reason to require artifacts and targeted tests before treating the integrated, run-time-switchable claim as established. My concern matches the reader's weakest assumption, so I agree with the reader and recommend leaving the verdict unchanged at CONDITIONAL.","tokens_in":21057,"tokens_out":7001,"duration_ms":74714,"concrete_test":"Require release of the BSV RTL and testbench; then run an end-to-end directed test: for a high-coverage set of bit patterns (including all special cases and random values), execute FCVT.ES in both es=2→3 and es=3→2 directions on the integrated core and compare against SoftPosit conversions, and repeat through the RoCC path with the Table IV instruction encodings. Also run one application from §VII (e.g., FFT) end-to-end and compare outputs with the SoftPosit reference. Any mismatch in these paths would show that the untested switching/accelerator claim fails.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's own verification section (§V-C) is narrower than the central claim. Random validation covers each operation only for es=2, with special cases for both es values; there is no reported test for FCVT.ES (Table V), for the es=2/3 datapath modifications in Eqs. (5)–(8), or for execution through the RoCC custom-opcode path (§III-B, §V-B). The §VII applications are claimed to run on the tightly-coupled core, but no simulation logs, testbenches, or RTL are provided, so the reader cannot distinguish module-level FPU correctness from full pipeline/integration correctness. Because the abstract's headline contribution is a complete RISC-V core with run-time es switching, the missing evidence for exactly those paths is the most load-bearing gap. If FCVT.ES or the custom-opcode routing is wrong, the integrated core is not what is claimed even if the es=2 FPU modules are correct.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes PERI, a posit-enabled RISC-V core built by integrating a parameterized Bluespec SystemVerilog posit FPU into the SHAKTI C-class core. The FPU implements the RV32F instruction set in posit form, supports dynamic switching between es=2 and es=3 at runtime via a new FCVT.ES instruction, and can be integrated either as a tightly coupled execution unit or as a RoCC coprocessor. The authors report SoftPosit-based verification for random inputs at es=2 and special cases at es=2 and es=3, application-level comparisons against IEEE-754 for image processing, transcendental series, FFT, and k-means, and FPGA synthesis results of 3507 slice LUTs, 1294 slice registers, and 100 MHz operation on an Artix-7-100T. The main claim is that this is the first complete posit-enabled RISC-V core with runtime es switching.","tokens_in":21194,"tokens_out":4190,"duration_ms":43318,"significance":"If the claims hold, PERI is a meaningful contribution: it provides a complete RV32F-compatible posit FPU, two integration paths into an open-source RISC-V core, and a hardware mechanism for switching between two exponent sizes. The paper's strengths include the explicit algorithms for posit decode/encode, FMA, division, square root, and conversions; the use of the SoftPosit reference library for arithmetic validation; and quantitative application results with confidence intervals. The synthesis numbers are also useful as a data point for posit FPU cost. However, the central 'first complete posit-enabled RISC-V core' claim rests on integration and dynamic-switching paths that are not validated by the experiments reported, and the application experiments depend on a manual software workaround that is presented with incorrect example encodings. With additional verification evidence and corrected software methodology, the paper would support its headline claim.","major_comments":[{"comment":"The verification reported in Section V-C is narrower than the central claim. Random inputs were checked against SoftPosit only for es=2 operations, with special cases for es=2 and es=3; there is no reported random or directed testing of the dynamic-switching datapath described in Section IV-K (Equations 5–8), of the new FCVT.ES instruction (Table V), or of the RoCC accelerator integration path of Section V-B. Because the abstract's headline contribution is a complete core with runtime es switching, these untested paths are load-bearing. The authors should provide simulation logs, testbenches, or RTL artifacts that cover FCVT.ES, the es=2/3 switching logic, and execution through both integration modes.","section":"§V-C, §IV-K, §V-B"},{"comment":"The software porting workaround is not reproducible as presented. In the code snippet of Section VI, the bit patterns assigned to f1pt5 and f1pt2 are 0x44000000 and 0x4199999A; these correspond to approximately 512.0 and 12.2 in IEEE-754 single precision, not to 1.5 and 1.2. Since all application experiments in Section VII use this memcpy-based approach, the reported application results cannot be reproduced from the paper. The authors should correct the encodings and provide the exact posit bit patterns used for each application constant, along with the conversion scripts or tables used to generate them.","section":"§VI, §VII-A"},{"comment":"The motivation for adding round-to-zero (RTZ) rounding to the posit-to-integer conversion is presented post hoc from the JPEG compression result, but the mechanism is underspecified. Algorithm 7 line 15 checks 'if (rm = 1)' without defining how the RISC-V rm field maps to this bit, and Section IV-G does not specify which rm encodings select RTZ versus round-to-nearest. This is a correctness-relevant detail because the RTZ path is claimed to be the reason posit JPEG sizes match IEEE-754. Please specify the exact rm decoding and provide a directed test for the RTZ conversion path.","section":"§IV-G, §VII-A"},{"comment":"The synthesis methodology is not fully clear. Table XI says each module was synthesized separately, but the row totals and the 15% dynamic-switching overhead are presented as characteristics of the complete FPU. If the totals come from summing separately synthesized modules rather than a single integrated synthesis, the area and frequency numbers may not reflect the actual integrated design. Please clarify whether the 3507 LUT / 1294 register totals come from a full integrated posit FPU synthesis and state the post-integration timing closure method.","section":"§VIII, Table XI"},{"comment":"The application experiments lack enough methodological detail to assess the numerical comparisons. For the trigonometric, exponential, and FFT results, the paper does not specify the series truncation, range-reduction strategy, data types used for intermediate computations, or whether the same C code was compiled with the same compiler flags for the IEEE-754 and posit versions. These details matter because the claimed accuracy advantage could be affected by how the power series is evaluated. Please provide the source code, input data, and a description of the execution environment, including how the posit mode was selected on the SHAKTI core.","section":"§VII"}],"minor_comments":[{"comment":"The notation 'k←(-ve)rc' is unclear; it should be written as 'k ← -rc' to match Equation 2.","section":"Algorithm 1, line 15"},{"comment":"The dynamic-switching modifications are presented as patch equations rather than integrated into Algorithms 1 and 2. It would be clearer to show the full modified decode/encode algorithms or state explicitly which lines are replaced by Equations 5–8.","section":"§IV-K, Equations 5–8"},{"comment":"The rounding-mode check 'if (rm = 1)' should be tied to the RISC-V instruction encoding, since the standard rm field is 3 bits; please specify the exact encoding used for round-to-zero versus round-to-nearest-even.","section":"§IV-G, Algorithm 7"},{"comment":"The confidence intervals are formatted ambiguously, e.g. '(1.20, 5.80) E-05'; this should read as '× 10^-5' or be converted to a consistent scientific notation.","section":"Tables VII and VIII"},{"comment":"The caption says 'Original Posit (RNE)' but the first row appears to be the original image size; please clarify what 'Original' refers to in each column.","section":"Table VI"},{"comment":"The number of random tests and the set of operations tested are not reported. Please state how many random inputs were used per operation and list the operations included in the random and special-case suites.","section":"§V-C"},{"comment":"The RoCC instruction mapping is described at the format level, but the paper does not specify how the posit register file is addressed when xs1/xs2 are clear or how the xd bit controls writes back to the integer register file. A short example of a complete RoCC posit instruction would improve clarity.","section":"§III-B"}],"recommendation":"major_revision","confidential_remarks":"The main risk is not the plausibility of the design but the scope of verification relative to the headline claim. The paper would be materially strengthened by releasing the BSV RTL and testbenches, or at least by reporting directed tests for FCVT.ES, dynamic switching, and the RoCC path. The incorrect bit patterns in the Section VI code snippet and the underspecified RTZ rounding should be corrected before acceptance. I do not see grounds for rejection: the algorithms and synthesis results are substantial, and the gaps appear addressable within the manuscript's scope."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is the first detailed account I know of a full posit FPU integrated into an open RISC-V core, and the ISA-level design is the real contribution. The verification is narrower than the headline: the dynamic es=2/3 switching path, which is the most distinctive piece, is not covered by the reported random tests, and no RTL or testbench is released. Treat it as an important architectural proposal with partial validation.\n\nWhat is actually new: the F-extension mapping (pcsr, es-mode, the FCVT.ES instruction), the RoCC custom-opcode mapping, and the parameterized BSV FPU with algorithms for all F-extension operations plus dynamic switching. Prior posit hardware generators like PACoGen provide arithmetic blocks, not a processor integration. The paper is also honest about the missing compiler stack and the memcpy workaround, and it sensibly refuses to draw unfair area comparisons between posit and IEEE FPUs. Synthesis tables give module-wise LUT/register numbers and cycle counts; application studies are checked against SoftPosit and IEEE double precision.\n\nThe soft spots are real but addressable. Section V-C says random tests were run for each operation at es=2, with special cases at es=2 and es=3. There is no reported test for FCVT.ES, for the Eq. (5)-(8) datapath modifications, or for execution through the RoCC custom-opcode path. That gap is load-bearing because the abstract's 'run-time es switching' claim rests on exactly those paths. The application section claims execution on the tightly-coupled core but provides no simulation logs; the favorable JPEG result depends on adding round-to-zero to posit-to-integer conversion, a post-hoc choice motivated by the result. These are not fundamental errors, but they are places where a referee should push for targeted tests and artifacts.\n\nBottom line: it deserves serious peer review. I would ask for the RTL/testbench or at least simulation traces covering FCVT.ES and both integration paths, and for the application claims to be reproducible. I would cite it as early work on RISC-V posit integration, with the verification caveat. The stress-test concern holds up on reading.","headline":"A full posit FPU in an open RISC-V core is a real first, but the runtime es-switch path is untested and the RTL is private—treat the headline as plausible, not verified.","tokens_in":21765,"tokens_out":3179,"would_cite":true,"duration_ms":36293,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper claims the first complete RISC-V core with a feature-complete, parameterized posit FPU that can switch exponent sizes at run time, and reports it working on an FPGA at 100 MHz.","keywords":["posit arithmetic","RISC-V","floating-point unit","IEEE 754","FPGA implementation","dynamic exponent size","RoCC accelerator","custom ISA extension"],"falsifier":"Implement the seven published algorithms in bit-accurate software or RTL, run random and corner-case inputs through every operation at es=3 and through FCVT.ES switching, and compare outputs with the software posit reference the paper used; a single mismatch in the es=3 or switching path would break the claim.","tokens_in":20840,"feed_emoji":"🧮","tokens_out":11167,"duration_ms":103385,"temperature":0.7,"pith_summary":"The paper proposes putting posit arithmetic, an alternative to IEEE 754 floating point, into a real RISC-V processor rather than leaving it as standalone arithmetic blocks. It claims PERI is the first complete RISC-V core with a feature-complete posit floating-point unit, integrated either as a normal execution unit or as an accelerator through the RoCC coprocessor interface. The unit is parameterized, and for 32-bit posits it can switch at run time between exponent sizes es=2 and es=3 so software can trade precision against dynamic range. Synthesis on an Artix-7 FPGA reports 3,507 slice LUTs, 1,294 slice registers, and a 100 MHz clock, and several small applications show accuracy or range benefits over IEEE 754 at the same bit width.","feed_headline":"RISC-V gains a posit-arithmetic core with runtime switching","feed_subtitle":"FPU fits in 3,507 LUTs on an Artix-7 and posts lower error than IEEE-754 in series and FFT tests.","key_machinery":"The load-bearing object is the parameterized posit FPU, built from a common posit decoder and encoder, a fused multiply-add block reused for add, subtract, and multiply, iterative non-restoring divider and square-root units, integer-to-posit and posit-to-integer converters, comparisons done with integer logic, sign injection, classify, plus an es-mode field in the posit control and status register and an FCVT.ES instruction for switching exponent sizes. The decoder/encoder pair is what makes switching cheap: a number is decoded under the source es and encoded under the target es, with only a few extra shifts needed to handle es=2 alongside es=3.","core_discovery":"The central claim is that a complete, parameterized posit FPU can be bolted onto the RISC-V 'F' extension with minimal change: the same instruction encodings and register file work if the control and status register carries an es-mode field, and the custom opcode space can host a wider posit coprocessor. The paper reports that both integration routes—tightly coupled execution unit and RoCC accelerator—work with the baseline in-order RISC-V core, that the FPU covers all F-extension operations in posit form, and that adding a second exponent size costs about 15% more LUTs and 8% more registers, enabling run-time switching through an FCVT.ES instruction that re-encodes a posit from one es value to another.","pith_inferences":["The most direct check that would settle the main claim is exhaustive bit-level comparison of every operation at es=3 and of FCVT.ES switching against a software posit reference, since the paper's reported random tests do not cover those paths.","If runtime es switching proves correct, the same decode-then-encode trick generalizes to other parameterized number formats controlled by a CSR mode field, suggesting a template for future arithmetic units.","The memcpy-and-hex-constant toolchain workaround will not scale; the real-world significance of PERI depends on compiler support and on a standard calling convention for posit data following.","The accuracy comparisons are on small kernels, so a stronger test would be an end-to-end application such as machine-learning inference or scientific simulation, where rounding errors accumulate over many operations."],"forward_implications":["A RISC-V core that already speaks RoCC can gain posit arithmetic without touching its pipeline, and IEEE-754 and posit units can coexist on the same chip.","Run-time switching between es=2 and es=3 lets one implementation cover high-precision and high-dynamic-range workloads, with software choosing the mode during computation.","The reported application results—lower mean percentage error in sine, cosine, exponential, and FFT calculations, and clustering that survives inputs where IEEE-754 overflows—suggest that 32-bit posit can carry more useful information than 32-bit IEEE-754.","The proposed instruction mappings and the FCVT.ES format give the RISC-V ecosystem a concrete starting point for compiler support, which the paper identifies as the missing piece."],"supporting_citations":[{"why":"Defines the posit number format, including regime encoding, the exponent-size parameter, and the 0/NaR exception model that the FPU implements.","marker":"[8]"},{"why":"Supplies the RISC-V ISA, the F extension instruction set, CSR semantics, and the custom opcode space that the paper modifies for posit.","marker":"[16]"},{"why":"Provides the baseline in-order RISC-V core and its FPU interface, into which the posit unit is dropped for the execution-unit integration.","marker":"[17]"},{"why":"Defines the RoCC coprocessor interface used for the accelerator-style integration of the posit FPU.","marker":"[23]"},{"why":"Serves as the software reference implementation used to verify the FPU outputs for random inputs.","marker":"[25]"}],"fun_headline_variants":["First RISC-V core with native posit arithmetic","Posit meets RISC-V: dual-exponent FPU does runtime switching","RISC-V posit FPU: 3507 LUTs, runtime es mode switch","Posit on RISC-V: run-time switch between accuracy and range","SHAKTI core gets a posit coprocessor with dynamic es"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The claim that PERI is the first complete posit-enabled RISC-V core rests on the untested assumption that the unpublished RTL correctly implements the es=3 and dynamic-switching paths, since the random verification reported in the paper covers es=2 only.","fun_headline_variants_meta":{"raw":{"variants":["First RISC-V core with native posit arithmetic","Posit meets RISC-V: dual-exponent FPU does runtime switching","RISC-V posit FPU: 3507 LUTs, runtime es mode switch","Posit on RISC-V: run-time switch between accuracy and range","SHAKTI core gets a posit coprocessor with dynamic es"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001083,"raw_usage":{"total_tokens":4595,"prompt_tokens":1079,"completion_tokens":3516,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":695,"completion_tokens_details":{"reasoning_tokens":3420}},"tokens_in":695,"tokens_out":3516,"duration_ms":24244,"temperature":1.0,"reasoning_tokens":3420,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T15:12:12.193876+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Implement the seven published algorithms in bit-accurate software or RTL, run random and corner-case inputs through every operation at es=3 and through FCVT.ES switching, and compare outputs with the software posit reference the paper used; a single mismatch in the es=3 or switching path would break the claim.","supporting_citations":[{"cited_title":"Beating floating point at its own game: Posit arithmetic,","cited_arxiv_id":null,"evidence_quote":"Defines the posit number format, including regime encoding, the exponent-size parameter, and the 0/NaR exception model that the FPU implements."},{"cited_title":"The risc-v instruction set manual. volume 1: User-level isa, version 2.0,","cited_arxiv_id":null,"evidence_quote":"Supplies the RISC-V ISA, the F extension instruction set, CSR semantics, and the custom opcode space that the paper modifies for posit."},{"cited_title":"An Introduction to the Rocket Custom Coprocessor Interface,","cited_arxiv_id":null,"evidence_quote":"Defines the RoCC coprocessor interface used for the accelerator-style integration of the posit FPU."},{"cited_title":"Softposit library,","cited_arxiv_id":null,"evidence_quote":"Serves as the software reference implementation used to verify the FPU outputs for random inputs."}],"review_version":1}