{"id":"36e27ad2-8b69-483d-9b6e-aa7e858ba1b4","arxiv_id":"1908.02656","paper_version":1,"verdict":"UNVERDICTED","confidence":"MODERATE","novelty_score":2.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"An invited review of silicon qubits, cryo-CMOS front-end electronics, and cryogenic MOSFET physics, containing a first observation of the kink effect in 28-nm bulk CMOS as its only new result.","lead":"This paper reviews silicon-based quantum computing and the cryogenic electronics needed to control qubits, with a focus on MOSFET behavior at very low temperatures. It is useful as an entry-level overview, but its only new data is a single qualitative measurement, and it contains a basic error in a quantum gate definition.","discovery_kind":"review","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The scalability claim rests on an unquantified 4-K power/thermal budget for cryo-CMOS; no system-level analysis is given, so co-integration is not established.","rationale":"The reader's weakest assumption identifies exactly the system-level power and thermal feasibility of cryo-CMOS at 4 K, and my reading agrees: the review asserts co-integration as the path to scaling but provides no quantitative budget, no heat-load analysis, and no demonstration of silicon qubits operating at 4.2 K. This is the most load-bearing gap because the entire QIC vision depends on it. Since the manuscript is an invited review rather than a research claim with a formal result, the appropriate verdict remains UNVERDICTED: the gap is real, but it does not convert a review into a rejected research paper. It does, however, weaken the strength of the 'highly promising' statement in the abstract. The review is otherwise a useful survey of silicon qubit types, cryogenic electronics, and MOSFET physics, with the new kink measurement being preliminary but not central to the review's argument. No independent verification exists in the manuscript, so the concern stands as a limitation rather than an error.","tokens_in":19629,"tokens_out":3085,"duration_ms":36368,"concrete_test":"Construct a first-order 4-K power budget for a 1000-qubit system using the cited cryo-CMOS blocks: sum per-qubit write power from the pulse modulator in [30] (<2 mW), readout LNA power, multiplexer and driver power, and estimated wiring heat load, using multiplexing ratios consistent with Section V. Compare the total with the 4-K cooling power of a commercial dilution refrigerator (about 1 W). If the total exceeds the available cooling power, the scalability claim in Section V is not supported by the cited evidence and should be downgraded from 'promising' to 'unproven'.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim (abstract; Section V) is that silicon qubits co-integrated with cryogenic CMOS front-end electronics can meet the scale-up challenge posed by the wiring bottleneck. The load-bearing premise is that the control and readout electronics can operate in the 4-K stage of a dilution refrigerator within its cooling power budget (typically of order 1 W at 4 K) while preserving qubit coherence and readout fidelity. Section V describes the required blocks (AWG, mixers, multiplexers, LNAs) and cites prototype demonstrations [23]-[30], but it never sums the power dissipation of a scaled system, does not account for the added heat load from cabling and multiplexing, and does not discuss how the dissipated heat is removed from the 4-K stage or whether it perturbs the 10-mK qubit stage. The text even proposes raising qubit operating temperature to 4.2 K as a future possibility, without citing a demonstrated silicon qubit with high-fidelity control and readout at that temperature. Thus the QIC vision in Section V depends on two unverified conditions: the cryo-CMOS power budget and 4.2-K qubit operation. The only new measurement, the 28-nm kink effect in Fig. 10, is presented without protocol, device statistics, or error bars, so it cannot underwrite the reliability claim either. This is not an internal inconsistency, but it is the point at which the central claim is least secure.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This invited review surveys silicon-based quantum computing, covering the basics of qubits and quantum gates (Section III), a comparison of qubit implementations with emphasis on silicon and CMOS-compatible qubits (Section IV), the concept of cryo-CMOS front-end electronics co-integrated with qubits to address the wiring bottleneck (Section V), and the device physics of MOSFETs at deep cryogenic temperatures (Section VI). The paper's thesis is that silicon qubits combined with cryogenic CMOS control and readout electronics form a credible path toward scalable quantum integrated circuits. It also reports, as a new observation, the kink effect in the output characteristics of a 28-nm bulk CMOS technology below 110 K (Figure 10).","tokens_in":19868,"tokens_out":2856,"duration_ms":31698,"significance":"If the co-integration vision in Section V is correct, the silicon/CMOS route offers a plausible industrial-scale path to quantum computing, and cryogenic MOSFET modeling becomes a critical enabling technology. The review usefully collects recent cryogenic device physics results, including the threshold-voltage behavior and the subthreshold-swing saturation explained by band-tail tunneling, and it provides a practical alert about the kink effect in advanced CMOS nodes. The strengths are the breadth of the survey and the explicit connection between qubit scaling and cryogenic electronics. However, the central scalability claim is not backed by quantitative system analysis, and the reliability of the cryogenic physics section rests largely on the authors' own prior publications without independent benchmarking. The new kink observation also lacks experimental detail. These gaps limit the review's current value as an authoritative assessment.","major_comments":[{"comment":"The CNOT matrix in Eq. (2) has an erroneous prefactor 1/sqrt(2); the correct CNOT gate is the 4x4 permutation matrix with a single 1 in each row and column and no prefactor, which is unitary. The printed matrix is not unitary and is therefore not a valid quantum gate. This is a fundamental error in a review whose purpose is to introduce quantum logic gates to readers, and it must be corrected.","section":"Section III-E2, Eq. (2)"},{"comment":"The central scalability claim that cryo-CMOS front-end electronics can be integrated in the 4.2-K stage to resolve the wiring bottleneck is asserted but not supported by any system-level power or thermal analysis. The text cites prototype demonstrations [23]-[30], but it does not quantify the total dissipated power of the AWG, mixers, multiplexers, and LNAs, the heat load added by cabling, the available cooling power at 4.2 K (typically of order 1 W), or the thermal isolation between the 4.2-K and 10-mK stages. The proposal to raise qubit operating temperature to 4.2 K is made without citing a demonstration of high-fidelity silicon qubit operation at that temperature. Because the abstract and Section V present co-integration as the paper's core promise, this missing analysis is a load-bearing gap.","section":"Section V, Figure 5"},{"comment":"The physical explanations of threshold-voltage increase and subthreshold-swing saturation are presented as established results, but they derive almost entirely from the authors' own references [53], [62], [79], and [81], with Figures 6-9 adapted from those works. No independent measurement or benchmark is provided in this review, and the text does not explicitly state that these are recent, still-debated results rather than settled textbook physics. For a review, reliance on the authors' own body of work is acceptable only if clearly framed as such; the current presentation risks overstating the consensus status of these cryogenic MOSFET models.","section":"Section VI, Figures 6-9"},{"comment":"The kink effect in 28-nm bulk CMOS at deep cryogenic temperatures is claimed as a first-time observation ('shown for the first time here in Fig. 10'), but no measurement protocol, device dimensions, number of devices tested, temperature steps, or error bars are reported. Without these details, the claim cannot be independently assessed, and the subsequent design advice to limit bias voltage around the kink lacks quantitative grounding. The authors should either provide measurement details or explicitly label this as a preliminary observation from ongoing work.","section":"Section VI, Figure 10"}],"minor_comments":[{"comment":"The phrase 'to factorize a number of N' should read 'to factorize a number N'.","section":"Section II"},{"comment":"The duplicated phrase 'RF reflectometry technique RF reflectometry technique' should be reduced to a single instance.","section":"Section IV-E"},{"comment":"The sentence 'we have to different situations' should be 'we have two different situations'.","section":"Section IV-E"},{"comment":"The word 'monolothically' is a typo for 'monolithically'.","section":"Section V"},{"comment":"The word 'nefast' is non-standard English; use 'detrimental' or 'harmful'.","section":"Introduction"},{"comment":"The statement that a π/2-pulse time is t = π/(2ω), with ω the driving-field angular frequency, conflates the driving frequency with the Rabi frequency; the pulse length depends on the Rabi frequency. This is a simplification that should be clarified or corrected.","section":"Section III-D"}],"recommendation":"major_revision","confidential_remarks":"This is an invited review from an active group in the field, and the heavy self-citation in Section VI is understandable given the authors' direct contributions to cryogenic MOSFET modeling. However, the review would benefit from a clearer separation between established results and the authors' ongoing research, as well as from an explicit system-level feasibility analysis of the cryo-CMOS co-integration claim. The CNOT matrix error, while easily fixed, is the kind of basic mistake that must be corrected before publication. The new kink observation, if kept, needs to be reported with the normal experimental rigor expected of a measurement claim."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Hi—\n\nIf you only read one thing, read Section VI and Fig. 10. The actually new content is the observation of the kink effect in 28-nm bulk CMOS at deep-cryogenic temperatures, which extends results that previously stopped at 180-nm nodes. The rest is a competent survey of silicon spin qubits, cryogenic front-end electronics, and MOSFET physics at 4 K, with the MOSFET part essentially summarizing the authors' own model. As a review, it is readable and well targeted; it would serve as a good entry point for someone starting in cryo-CMOS for quantum control.\n\nBut there are real soft spots. Eq. (2) gives a CNOT matrix with a spurious 1/sqrt(2) prefactor, which makes it non-unitary. That is a basic error in a review about quantum gates and will confuse newcomers. The Introduction's claim that D-Wave built the world's first quantum computer in 1999 is also wrong on the facts; D-Wave was founded in 1999 but its first commercial systems came later. The abstract and Section V sell the QIC vision, but the load-bearing premise — that cryo-CMOS can run at 4 K within the fridge power budget and still control/read qubits — is asserted, not analyzed. There is no system-level estimate of heat load, no discussion of how the 4-K stage is cooled, and the suggestion to raise qubit operation to 4.2 K is speculative and uncited. The stress-test note is right: this is where the central claim is least secure.\n\nThe kink figure itself needs more disclosure. We get one annotation that the kink appears below 110 K and above VDB = 0.9 V, but no device dimensions, test protocol, number of samples, or error bars. For a \"first time here\" claim, that is thin. I don't doubt the effect exists — kinks at cryogenic temperatures are well known in older nodes — but the paper should say enough for someone to reproduce it.\n\nThe reliance on self-cited works in Section VI doesn't bother me much. The authors are reporting their own model in a review format; that is how reviews in this field work. But it should be framed as \"our model,\" not as an independent consensus, and the current text blurs that line.\n\nWho is this for? Graduate students and engineers wanting a fast map of silicon qubit control and cryo-MOSFET physics. They will get a useful orientation, provided they ignore the CNOT prefactor and treat the scalability talk as a vision, not an established roadmap.\n\nRecommendation: this deserves peer review, not a desk reject, but it should be sent back for major revision. The authors need to fix the CNOT matrix, correct the D-Wave history, add measurement details for Fig. 10, and either quantify the cryo-CMOS power argument or explicitly mark it as an open question.","headline":"A readable review of silicon qubits and cryo-CMOS with one genuinely new kink-effect datapoint; the CNOT typo and unquantified scalability claims need fixing before it can be trusted.","tokens_in":20443,"tokens_out":2556,"would_cite":false,"duration_ms":26652,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This review argues that silicon qubits co-integrated with cryogenic CMOS control electronics are the credible route to scalable quantum computing, and that the missing physics for that route is band-tail tunneling in MOSFETs at 4 K.","keywords":["quantum computing","silicon qubits","cryo-CMOS","cryogenic MOSFET modeling","subthreshold swing saturation","band-tail tunneling","quantum integrated circuits","dilution refrigerator"],"falsifier":"Run a multi-qubit silicon array with cryo-CMOS front-end electronics at 4.2 K and measure both gate fidelity and total dissipated heat as qubits are added; if fidelity falls below the error-correction threshold once room-temperature wiring is eliminated, or if the electronics exceed the fridge's cooling power, the co-integration claim fails. For the MOSFET sub-claim, engineer devices with different band-tail widths and check whether the 4.2-K subthreshold swing follows $SS = mW_t \\ln 10$ rather than the Boltzmann limit $(k_BT/q)\\ln 10$.","tokens_in":19383,"feed_emoji":"❄️","tokens_out":8206,"duration_ms":82214,"temperature":0.7,"pith_summary":"The paper reviews the case for building scalable quantum computers on the silicon platform. It argues that the main obstacle is not the qubits themselves but the wiring: each qubit needs its own control line into a dilution refrigerator, and room-temperature electronics add latency, heat, and capacitance. The proposed fix is to move control and readout electronics inside the fridge using CMOS circuits operating at 4 K, and ultimately to co-integrate qubits and electronics on one chip as quantum integrated circuits. The review also claims that standard MOS transistor models fail below about 50 K and identifies the missing physics: a band-tail tunneling current that sets a new lower limit on the subthreshold swing. This points to silicon as a credible path to large-scale quantum computing built on the semiconductor industry's existing toolchain.","feed_headline":"Silicon and cryo-CMOS: route to scalable quantum computers","feed_subtitle":"Moving control chips into the 4 K fridge with silicon qubits can end the room-temperature wiring bottleneck.","key_machinery":"The load-bearing object is the quantum integrated circuit (QIC): silicon qubits and their FET-based control and readout electronics sharing the same CMOS platform, with the electronics lifted from room temperature to the 4.2-K stage of the dilution refrigerator. The MOSFET physics that carries the argument rests on two pieces: Poisson-Boltzmann electrostatics corrected for incomplete ionization of body dopants, which keeps the Maxwell-Boltzmann approximation valid and lowers the threshold voltage compared with the freezeout picture, and a band-tail tunneling (hopping) current in weak inversion that runs parallel to drift-diffusion. Its quantitative core is the revised subthreshold-swing identity $SS = mW_t \\ln 10$, where $W_t$ is the characteristic exponential band-tail extension in eV and $m$ is the slope factor including interface-trap density; this replaces the thermal limit $(k_BT/q)\\ln 10$ below about 50 K.","core_discovery":"On the paper's own terms, the central claim is that the silicon-based quantum-computing platform, built on CMOS-compatible spin qubits and deep-cryogenic FET electronics, is a credible route to the scale-up that superconducting platforms currently lack. The immediate obstacle is wiring: each qubit needs a dedicated control line from room temperature, and those lines bring thermal noise, capacitance, and latency. Moving the front-end electronics to the 4.2-K stage, and ultimately co-integrating qubits and transistors on one chip, would turn that obstacle into an integration problem that the semiconductor industry already knows how to solve. The review's specific physics claim is that MOSFETs at deep cryogenic temperatures cannot be modeled by simply extending room-temperature compact models: a band-tail tunneling (hopping) current flowing in parallel with drift-diffusion sets a new subthreshold-swing floor $SS = mW_t \\ln 10$, and dopant freezeout in the channel is not what raises the threshold voltage. This is what a sympathetic reader would take the paper to be establishing.","pith_inferences":["The review does not provide a system-level power budget, heat-load calculation, or yield analysis for a quantum integrated circuit, so the scalability claim should be read as a research direction rather than a demonstrated engineering result.","If band-tail tunneling is the true floor for the subthreshold swing, the same limit should appear in other disordered-channel transistor technologies at deep cryogenic temperatures, and a cross-technology measurement would test the mechanism beyond silicon.","A natural next experiment is a full cryo-CMOS-controlled multi-qubit array that measures gate fidelity and total dissipated power together, since both must clear the error-correction and cooling thresholds simultaneously.","The threshold-voltage argument, that freezeout does not explain the rise in $V_{th}$, suggests simple corrections to existing compact models rather than a completely new transport model for strong inversion."],"forward_implications":["If the co-integration vision is right, the wiring bottleneck disappears: control and readout electronics sit centimeters from the qubits, cutting latency and accumulated capacitance that otherwise cap algorithm complexity.","Cryogenic MOSFET models must be rebuilt rather than extrapolated, because industry compact models that work at 77 K fail at 4.2 K, and QIC design needs DC, AC, RF, and noise models that include the cryogenic mechanisms.","Qubits could move from the roughly 10-mK stage to 4.2 K, where cooling power is orders of magnitude higher, letting more electronic functionality live near the qubits.","MOS-gate-only control via electric dipole spin resonance, especially with hole spin qubits, removes per-qubit wires and is a necessary step toward one-chip quantum integrated circuits.","Because silicon qubits are fabricated in CMOS-compatible processes, the existing semiconductor manufacturing toolchain can be leveraged directly, lowering the barrier to producing many qubits."],"supporting_citations":[{"why":"Demonstrates a CMOS silicon spin qubit, giving the silicon platform a foundry-compatible qubit.","marker":"[18]"},{"why":"Shows a 28-nm bulk-CMOS pulse modulator operating at the 4-K stage, evidence that cryo-CMOS front-end electronics can talk to qubits.","marker":"[30]"},{"why":"Provides a silicon CMOS architecture for a spin-based quantum computer, the structural basis for the quantum-integrated-circuit vision.","marker":"[29]"},{"why":"Supplies the cryogenic MOS transistor model and the Poisson-Boltzmann electrostatics starting point used throughout the MOSFET physics section.","marker":"[53]"},{"why":"Explains the cryogenic threshold-voltage increase through bandgap widening and Fermi-Dirac statistics rather than dopant freezeout.","marker":"[62]"},{"why":"Proposes band tails to describe cryogenic subthreshold-swing saturation, the phenomenon the review reinterprets with a tunneling current.","marker":"[79]"},{"why":"Provides the band-tail tunneling current and the revised subthreshold-swing limit $SS = mW_t \\ln 10$ that carries the paper's main physics claim.","marker":"[81]"},{"why":"Shows a silicon CMOS platform for quantum information processing, supporting the claim that existing silicon processes can host qubits.","marker":"[44]"}],"fun_headline_variants":["Silicon qubits plus cryo-CMOS: end the wiring bottleneck","Cryo-MOSFET physics: key to scaling silicon quantum computers","Co-integrate spin qubits and cryo-CMOS to beat the wiring wall","Deep-cryo MOSFETs: the missing piece for silicon qubit scale-up"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The entire quantum-integrated-circuit vision rests on the assumption that CMOS control and readout circuits can operate at 4 K inside a dilution refrigerator within its cooling-power budget while preserving qubit fidelity above error-correction thresholds.","fun_headline_variants_meta":{"raw":{"variants":["Silicon qubits plus cryo-CMOS: end the wiring bottleneck","Cryo-MOSFET physics: key to scaling silicon quantum computers","Co-integrate spin qubits and cryo-CMOS to beat the wiring wall","Deep-cryo MOSFETs: the missing piece for silicon qubit scale-up"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000185,"raw_usage":{"total_tokens":1290,"prompt_tokens":879,"completion_tokens":411,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":495,"completion_tokens_details":{"reasoning_tokens":328}},"tokens_in":495,"tokens_out":411,"duration_ms":4854,"temperature":1.0,"reasoning_tokens":328,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T14:39:12.212523+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run a multi-qubit silicon array with cryo-CMOS front-end electronics at 4.2 K and measure both gate fidelity and total dissipated heat as qubits are added; if fidelity falls below the error-correction threshold once room-temperature wiring is eliminated, or if the electronics exceed the fridge's cooling power, the co-integration claim fails. For the MOSFET sub-claim, engineer devices with different band-tail widths and check whether the 4.2-K subthreshold swing follows $SS = mW_t \\ln 10$ rather than the Boltzmann limit $(k_BT/q)\\ln 10$.","supporting_citations":[{"cited_title":"A 28nm Bulk-CMOS 4-to-8 GHz < 2mW Cryogenic Pulse Modulator for Scalable Quantum Computing,","cited_arxiv_id":null,"evidence_quote":"Shows a 28-nm bulk-CMOS pulse modulator operating at the 4-K stage, evidence that cryo-CMOS front-end electronics can talk to qubits."},{"cited_title":"Silicon CMOS architecture for a spin-based quantum computer,","cited_arxiv_id":null,"evidence_quote":"Provides a silicon CMOS architecture for a spin-based quantum computer, the structural basis for the quantum-integrated-circuit vision."},{"cited_title":"Cryogenic MOS Transistor Model,","cited_arxiv_id":null,"evidence_quote":"Supplies the cryogenic MOS transistor model and the Poisson-Boltzmann electrostatics starting point used throughout the MOSFET physics section."},{"cited_title":"Cryo- genic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening,","cited_arxiv_id":null,"evidence_quote":"Proposes band tails to describe cryogenic subthreshold-swing saturation, the phenomenon the review reinterprets with a tunneling current."},{"cited_title":"Revised theoretical limit of subthreshold swing in field-effect transistors","cited_arxiv_id":"1811.09146","evidence_quote":"Provides the band-tail tunneling current and the revised subthreshold-swing limit $SS = mW_t \\ln 10$ that carries the paper's main physics claim."},{"cited_title":"Si CMOS platform for quantum information processing,","cited_arxiv_id":null,"evidence_quote":"Shows a silicon CMOS platform for quantum information processing, supporting the claim that existing silicon processes can host qubits."}],"review_version":1}