{"id":"4bbfff85-2fc1-462c-badc-dff7038fbeaa","arxiv_id":"1908.03653","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"Devito-generated acoustic and TTI seismic kernels run at comparable single-socket speed on ARM ThunderX2 as on Intel Xeon for memory-bound workloads.","lead":"This paper benchmarks Devito, a domain-specific language for finite-difference solvers, on ARM ThunderX2 processors and compares it with Intel Xeon chips. It shows ARM can match Intel on memory-bound seismic imaging kernels, which is relevant for choosing cheaper, competitive HPC hardware.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Generalizing from single-socket stencil kernels to 'seismic inverse problems' is the main risk; a full RTM/FWI end-to-end test would settle it.","rationale":"The reader's weakest_assumption is essentially the same generalization concern I identify: the paper moves from two single-socket stencil benchmarks to 'seismic inverse problems' broadly, and the compiler environment differs across architectures. I focus on the generalization because it is the more load-bearing of the two: even if the compiler versions were identical, the central claim would still rest on the unstated assumption that the two stencil kernels dominate real inverse-problem runtime. The compiler mismatch is real and worth controlling, but it is secondary because the workload is memory-bound and the reported bandwidth difference is large. A full RTM/FWI benchmark directly tests the generalization, and also removes the compiler-version confound if implemented with a common toolchain. I do not see a reason to reject the paper; the data support the more modest claim that Devito generates efficient code for these stencil kernels on ARM. The conditional verdict already reflects the need for caveats, so I recommend no change to the reader's verdict.","tokens_in":3663,"tokens_out":9846,"duration_ms":115010,"concrete_test":"Implement a representative 3D RTM or FWI benchmark in Devito (e.g., the 3D isotropic overthrust model) including source injection, receiver recording, absorbing boundaries, and checkpointing, and run it end-to-end on one ThunderX2 node and one Xeon Gold 6126 node using the same Devito version and, where possible, the same compiler version. Record total wall time and profile the fraction of time spent in the pure stencil kernels versus all other phases. If ARM's full-node total time remains within roughly 20% of the Xeon's, the Section 4 claim is supported; if ARM loses by a larger margin or the non-stencil fraction dominates, the claim should be narrowed to stencil kernels.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section 4's central claim ('Arm based processors are capable of delivering performance similar to state-of-the-art Intel Xeon processors for the execution of seismic inverse problems') goes beyond the evidence presented: the experiments cover two stencil kernels (acoustic and TTI) run on a single socket, with no end-to-end inverse problem such as RTM or FWI, and no multi-node or communication measurements. Production seismic inverse problems also include source injection, receiver interpolation, absorbing boundary conditions, I/O, checkpointing, and parallel communication, none of which are benchmarked here. These non-stencil phases tend to have lower arithmetic intensity and more serial or low-parallel components; Table 2 shows ARM's single-thread acoustic time is 288.1s versus 85.9s on the Xeon Gold 6126, so ARM's full-socket parity comes almost entirely from having 32 cores and higher memory bandwidth rather than from per-core efficiency. If any significant fraction of a real inverse problem runs in these phases, the observed stencil parity may not translate to the stated general claim. The comparison is further complicated by asymmetric software stacks: ARM used GCC 8.2 and CCE 8.7.9, while Intel used only GCC 7.4. The generalization to 'seismic inverse problems' is therefore the least secure link in the argument.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This manuscript reports a single-socket performance study of the Devito finite-difference DSL on a Marvell ThunderX2 ARM processor, comparing execution times and achieved GFLOP/s against two Intel Xeon Gold processors (5120 and 6126) for two seismic stencil kernels: the acoustic wave equation and the TTI wave propagator. Experiments vary thread count, grid size, space order, compiler (GCC 8.2 and CCE 8.7.9 on ARM; GCC 7.4 on Intel), and Devito optimisation mode. The headline finding, stated in Section 4, is that ARM processors are capable of delivering performance similar to state-of-the-art Intel Xeon processors for seismic inverse problems, and that Devito can generate efficient code for ARM without architecture-specific tuning. The paper is a short empirical note that presents no new algorithmic or systems contribution beyond the measurement data itself.","tokens_in":3926,"tokens_out":2484,"duration_ms":27977,"significance":"If the reported results are taken at face value, the manuscript provides useful evidence that ARM server processors can reach competitive single-socket performance on memory-bound seismic stencil kernels when the full socket is used, and that a high-level DSL such as Devito can target ARM without manual refactoring. The strengths of the paper are that it uses real HPC hardware (Isambard/ThunderX2), reports a substantial sweep of kernel/grid/optimization combinations, and follows a deterministic thread-pinning and single-thread-per-core configuration that aids reproducibility. The main weakness is that the evidence does not support the broad concluding claim about 'seismic inverse problems', since no end-to-end inversion (RTM or FWI) or multi-node/communication phase is measured. The paper also does not provide the code, exact FLOP-count formulas, or complete compiler details needed to independently verify the GFLOP/s numbers. These issues are fixable in revision either by narrowing the claims or by supplying missing methodological detail.","major_comments":[{"comment":"The last processor column is labeled 'Xeon Gold 6128' while the hardware table and the text refer to 'Xeon Gold 6126'. This is likely a typo, but it affects the reproducibility of the data; the label should be corrected and checked against the machine configuration.","section":"Table 2, column header"}],"minor_comments":[{"comment":"The text says 'Recent studies compared the single node performance and multi-node scalability of Arm systems [3–5]', but reference [5] is Zhang et al., a geophysics paper on TTI reverse time migration, not a performance study of ARM systems; the citation range should be corrected to avoid implying that the TTI paper contains single-node performance data.","section":"Section 1, references"},{"comment":"The paper states that memory bandwidth was measured with STREAM and that 'for the Arm we used CCE' while GCC was used for the Intel processors, but does not give the STREAM version, array sizes, or number of trials; adding these details would make the Table 1 bandwidth figures reproducible.","section":"Section 3, STREAM measurement"},{"comment":"The labels 'ideal' and 'linpack' in Figure 1 are not defined in the text or caption. The 'linpack' point presumably refers to the measured HPL value from Table 1, but the reader should be told what the 'ideal' curve represents and how the percentage values are computed relative to it.","section":"Section 3, Figure 1"},{"comment":"The sentence 'The results shown for the Arm processor were produced by GCC, which presented slightly better performance compared to CCE' gives no quantitative comparison between GCC and CCE on ARM; a single sentence with representative execution times would make the compiler choice more transparent.","section":"Section 3, compiler comparison"},{"comment":"The phrase 'a pipeline of compilers and libraries' is vague; the paper would benefit from naming the specific components of the Devito lowering pipeline (e.g., SymPy, code generation, OpenMP/MPI backends) that are relevant to the experiments, so that readers know what 'integrated with other compilers' means in Section 3.","section":"Section 2, Devito description"}],"recommendation":"major_revision","confidential_remarks":null},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Here's my take.\n\nThe useful nugget: a clean single-socket measurement showing Devito-generated acoustic and TTI stencil kernels run at parity on Marvell ThunderX2 against Intel Xeon Gold 5120/6126 when all cores are used. The ARM chip gets there with 32 cores and high memory bandwidth; single-thread it is about 3x slower. That is a real, narrow data point for ARM HPC procurement and for Devito's portability. What makes the paper credible is the method: 288 runs per configuration set, replicated three times, <1% variance reported, grid sizes through 1024^3, space orders 4-16, STREAM bandwidth reported, and compiler flags and thread pinning specified.\n\nNow the soft spots, in order of size. First, the claim in the abstract and Section 4 that ARM executes 'seismic inverse problems' at Xeon-like performance goes beyond the evidence. The paper contains no inverse problem. It contains two stencil kernels. A production RTM or FWI includes source injection, receiver interpolation, boundary conditions, I/O, and multi-node communication, none of which are benchmarked. The stress-test note is right: if any meaningful fraction of the runtime sits in those phases, the stencil parity may not transfer. The fix is easy: either run a real RTM/FWI end-to-end case or reword the claim to say 'two common seismic finite-difference kernels'.\n\nSecond, the compiler asymmetry is real. ARM ran GCC 8.2 and CCE 8.7.9; Intel ran only GCC 7.4. Two years of compiler improvements on the ARM side could partly explain the parity. The authors should either rerun Intel with a matching compiler or include a sensitivity note. Third, Table 2 reports single measurements with no error bars; the 'negligible variance' remark applies to the later 288-run experiment, not necessarily to Table 2. Fourth, no code or data artifacts are provided, so the GFLOP/s arithmetic cannot be independently checked. Minor: the table caption says Xeon Gold 6128 while the text and Table 1 say 6126—probably a typo.\n\nNone of these sink the narrow claim. The paper is honest about the memory-bound explanation, about the single-thread deficit, and about the fact that no architecture-specific tuning was needed; that last claim is well supported and is the most interesting result in the paper.\n\nWho should read it: anyone making single-node hardware choices for seismic imaging workloads, and people working on portable stencil DSLs. It deserves a proper peer review, provided the authors are asked to tighten the generalization, address the compiler mismatch, and add error bars or artifacts. I would accept it for review.","headline":"A clean, narrow ARM-vs-Xeon stencil benchmark whose 'seismic inverse problems' claim overreaches the two kernels actually measured.","tokens_in":4417,"tokens_out":3490,"would_cite":false,"duration_ms":37152,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"ARM ThunderX2 matches Intel Xeon on seismic imaging kernels","keywords":["Devito","ARM ThunderX2","finite-difference stencil","seismic imaging","TTI","memory-bound performance","HPC benchmarking","domain-specific language"],"falsifier":"Run the same acoustic and TTI kernels with one common compiler (or matched optimisation levels) on a fully loaded ThunderX2 socket and a Xeon Gold socket at $768^{3}$ and $1024^{3}$ grids, and also in a multi-node MPI configuration; if the ARM wall-clock time grows to, say, more than 1.5 times the Xeon time on these larger production-sized runs, the claim of competitive performance on seismic inverse problems would be refuted.","tokens_in":3522,"feed_emoji":"⚡","tokens_out":6192,"duration_ms":60259,"temperature":0.7,"pith_summary":"This paper asks whether ARM processors can run realistic seismic imaging codes without a performance penalty. It uses Devito, a domain-specific language for finite-difference stencils, to generate code for two industrial kernels — acoustic wave propagation and tilted transverse isotropy (TTI) reverse time migration — on a 32-core ARM ThunderX2, and compares single-socket results against two Intel Xeon Gold processors. The workload is memory-bound, so the ARM chip's extra cores and memory bandwidth compensate for slower single-core vector performance, and at full socket utilisation the two architectures land within the same range. The authors conclude that ARM processors are a credible platform for seismic inverse problems and that Devito needs no architecture-specific tuning to reach that level.","feed_headline":"ARM ThunderX2 matches Intel Xeon on seismic imaging kernels","feed_subtitle":"Memory-bound stencil code from the Devito DSL closes the gap when all cores are busy.","key_machinery":"The central object is Devito, a domain-specific language and compiler for finite-difference stencils, which turns symbolic equations into C++ code through a lowering pipeline. It applies several optimisation passes — the paper names basic, aggressive, and DSE modes — that handle cache reuse, register pressure, and loop structure. This machinery matters because the TTI stencil has high arithmetic intensity and high register pressure, while the acoustic kernel is memory-bound; Devito's job is to generate code that lets the ARM's 32 cores and high memory bandwidth express themselves without hand tuning. The paper's comparison therefore tests the combination of a portable DSL and an emerging hardware architecture, not just raw processor speed.","core_discovery":"On the paper's own terms, the discovery is that a first-generation HPC-optimised ARM processor, the Marvell ThunderX2, delivers performance comparable to state-of-the-art Intel Xeon Gold processors when running Devito-generated finite-difference kernels for seismic imaging. At a $512^{3}$ grid with fourth-order stencils, the ThunderX2 executes the acoustic kernel in 11.0 seconds with 32 threads, against 14.7 seconds on a Xeon Gold 5120 and 13.6 seconds on a higher-clocked Xeon Gold, and runs the TTI kernel in 67.3 seconds versus 69.2 and 61.4 seconds. The ARM chip reaches 157.7 GFLOPS on acoustic and 212.3 GFLOPS on TTI, close to the Intel results, because the kernels are memory-bound and the ThunderX2 provides roughly double the measured memory bandwidth of the Intel sockets. The achieved fraction of peak performance falls from 63% to 25% as the acoustic space order rises from 4 to 16, confirming that memory bandwidth, not compute, sets the ceiling.","pith_inferences":["If the single-socket pattern extends to multi-node runs, ARM-based systems could offer comparable seismic throughput per dollar, but the paper's data do not cover MPI scaling, so that extension is unproven.","The compiler mismatch (GCC 8.2 and CCE on ARM, GCC 7.4 on Intel) means part of the measured balance could reflect compiler maturity rather than hardware; a matched-compiler experiment would separate the two.","The memory-bound explanation predicts that a compute-bound variant of the same kernels, or a smaller grid that fits in cache, would swing the comparison back toward the Xeons; that is a direct, testable consequence of the paper's mechanism.","The paper tests only single-socket performance; on a production system the interconnect and MPI overheads could change the ranking, so the broad 'seismic inverse problems' claim is a hypothesis at node level."],"forward_implications":["A system with many ARM cores can match a Xeon socket on memory-bound stencil workloads, so core count and memory bandwidth can substitute for per-core vector throughput.","Devito's generated code is portable: the same high-level equations compile into efficient code on both x86 and ARM without architecture-specific rewrites.","Seismic imaging workloads of the acoustic and TTI type can run on ARM-based HPC nodes with wall-clock times competitive with current Intel servers.","Because the kernels are memory-bound, the ARM advantage should be largest when the working set saturates memory bandwidth; increasing space order reduces achieved efficiency on both platforms.","The measured GFLOPS values remain far below peak (63% at SO=4 down to 25% at SO=16), indicating that further gains must come from improving memory access patterns rather than raw floating-point capability."],"supporting_citations":[{"why":"defines the two benchmark models, their finite-difference schemes, and the Devito implementations used in the experiments.","marker":"[1]"},{"why":"describes Devito's architecture and the optimisation techniques the DSL applies to generate the code under test.","marker":"[2]"},{"why":"supplies the comparative benchmarking methodology and the baseline showing ARM competitive on HPC workloads on the same system.","marker":"[3]"},{"why":"provides the broader performance analysis of first-generation HPC-optimised ARM processors that the paper builds on.","marker":"[4]"},{"why":"gives the stable TTI reverse-time-migration formulation that is the paper's production-representative second benchmark.","marker":"[5]"}],"fun_headline_variants":["ARM ThunderX2 rivals Intel Xeon in seismic stencil codes","Devito on ARM matches Intel in seismic imaging","ARM chip equals Xeon on memory-bound seismic kernels","ThunderX2 holds its own against Xeon Gold in Devito"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The conclusion depends on two single-socket kernel benchmarks on one ARM processor standing in for production seismic inverse workloads, and on the different compiler versions used on each architecture not biasing the comparison.","fun_headline_variants_meta":{"raw":{"variants":["ARM ThunderX2 rivals Intel Xeon in seismic stencil codes","Devito on ARM matches Intel in seismic imaging","ARM chip equals Xeon on memory-bound seismic kernels","ThunderX2 holds its own against Xeon Gold in Devito"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000566,"raw_usage":{"total_tokens":2607,"prompt_tokens":793,"completion_tokens":1814,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":409,"completion_tokens_details":{"reasoning_tokens":1745}},"tokens_in":409,"tokens_out":1814,"duration_ms":13607,"temperature":1.0,"reasoning_tokens":1745,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T14:06:06.268703+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same acoustic and TTI kernels with one common compiler (or matched optimisation levels) on a fully loaded ThunderX2 socket and a Xeon Gold socket at $768^{3}$ and $1024^{3}$ grids, and also in a multi-node MPI configuration; if the ARM wall-clock time grows to, say, more than 1.5 times the Xeon time on these larger production-sized runs, the claim of competitive performance on seismic inverse problems would be refuted.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"defines the two benchmark models, their finite-difference schemes, and the Devito implementations used in the experiments."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"supplies the comparative benchmarking methodology and the baseline showing ARM competitive on HPC workloads on the same system."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"provides the broader performance analysis of first-generation HPC-optimised ARM processors that the paper builds on."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"gives the stable TTI reverse-time-migration formulation that is the paper's production-representative second benchmark."}],"review_version":1}