{"id":"709931d5-4214-4faa-b083-023b8953b29c","arxiv_id":"1908.03925","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"Splitting a chip into two stacked 3D tiers and obfuscating the vertical connections protects against both IP theft and targeted hardware-Trojan insertion with moderate PPA overhead.","lead":"This paper proposes making computer chips harder to copy or sabotage by manufacturing them as two stacked halves, with the vertical wires between the halves randomized and disguised. A trusted facility adds those hidden connections, so neither the chip factory nor a later reverse engineer can easily reconstruct the full design.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 0.25% HT-insertion claim for b19 depends on an unvalidated assumption that 3D partitioning does not leak which tier holds the target; Table 10 and Table 12 even report inconsistent k values.","rationale":"The reader's conditional verdict is reasonable, and the BEOL/Mg-MgO trust premise they flag is a genuine limitation. However, the single most load-bearing gap for the central quantitative claim is the HT-prevention security level. The paper's 0.25% figure for b19 is computed from a k value whose definition changes between Table 10 and Table 12, and the preservation of k-security under 3D partitioning is asserted rather than demonstrated. The threat model gives the attacker both tier layouts and the complete netlist, so the relevant question is whether the visible tier split can be used to reduce the candidate set for a targeted structure. The authors' own proximity attack work shows that partial structural matching against layouts is feasible, and no analogous experiment is run for the HT scenario. This does not prove the scheme is broken, but it makes the headline probability an unresolved empirical claim rather than a supported guarantee. The proposed concrete test would settle whether the per-tier/per-structure candidate count remains at or above the claimed k. If the test confirms candidate counts at least as large as reported, the concern is resolved and the conditional verdict can stand. The reader's identified Mg/MgO assumption remains a secondary but real threat to the IP-protection half; the two concerns together justify keeping the paper conditional rather than unconditional acceptance.","tokens_in":30743,"tokens_out":22732,"duration_ms":230994,"concrete_test":"Reproduce the b19 3D flow, then simulate an attacker who has the final netlist and both tier layouts: solve a maximum-common-subgraph / partial matching problem to assign netlist structure instances to physical instances using only intra-tier routed edges, and for every vulnerable target compute the number of physical instances remaining consistent with the observed tier placement and connectivity. If the minimum residual candidate count over targets falls below the claimed k=400, the 0.25% probability is optimistic; if the count remains at least 400 for all targets, the concern is resolved. Report the full distribution of residual counts across vulnerable gates.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The HT-prevention guarantee in Sec. 8 rests on the security level k=400 for b19, yielding the headline 0.25% success chance (1/400). Table 12 defines k as the sum of the least-occurring structures in the bottom and top tiers, and Sec. 7.3 asserts that the timing-aware/randomized partitioning maintains the k-security notion of [10] because 'the attacker cannot understand which isomorphic instances in the bottom/top tier relate to which in the netlist.' That assertion is the load-bearing step. The attacker under the strong threat model holds the complete final netlist and both tier layouts, and the tier assignment is physically visible. The paper provides no analysis showing that the observable intra-tier connectivity cannot be matched against the netlist to determine the tier of a target structure, thereby pruning the candidate set below k. The cited formal k-isomorphism result [45] concerns anonymized graph publication, not this setting where the original netlist is given and the tier partition is partially observed. The internal numbers are also not reconciled: Table 10 reports k=1,221 for b19 after iteration 5, while Table 12 reports k=400 for the 3D flow, despite Sec. 8.2 saying the levels are the same as in 2D. If the attacker can infer the tier, the per-tier candidate count (potentially about 200) already doubles the claimed success probability, and additional structural hints could reduce it further. The 0.25% figure is therefore not backed by a validated security analysis.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a security-driven CAD and manufacturing flow for face-to-face 3D integrated circuits that combines split manufacturing (SM) and layout camouflaging (LC). The design netlist is partitioned into two tiers, the vertical interconnects between tiers are randomized and obfuscated using redistribution layers (RDLs) with Mg/MgO vias and switchboxes, and a trusted BEOL facility performs the stacking. Two variants are developed: one for IP protection against untrusted fabs and malicious end-users, and one for hardware-Trojan prevention under a strong threat model where the attacker already holds the complete gate-level netlist. The latter uses a security-driven synthesis stage to create many isomorphic structures and applies k-security notions from prior work. Experiments on DRC-clean layouts of ITC-99, ISCAS-85, DARPA CEP, and OpenCores JPEG benchmarks report PPA overheads, attack results from a newly proposed proximity attack and SAT-based attacks, and a headline claim that for benchmark b19 the attacker has only a 0.25% chance of successful targeted Trojan insertion.","tokens_in":31079,"tokens_out":6582,"duration_ms":73241,"significance":"If the security claims hold, this is a substantial systems contribution: it is one of the first end-to-end flows to combine SM and LC in 3D ICs, applies k-security to multi-million-gate benchmarks for the first time, provides DRC-clean layouts with an industrial tool, reports distributions over randomized runs, and publicly releases the 3D split-manufacturing attack. These are concrete, reproducible strengths. However, the central Trojan-prevention guarantee and the IP-protection claim both rest on security arguments that are asserted rather than demonstrated, and one of the two headline probabilities is tied to an internal inconsistency in the reported security levels. The work is therefore promising but requires substantial additional analysis before the main claims can be accepted.","major_comments":[{"comment":"The claim that the proposed 3D partitioning preserves the k-security notion of [10] is the load-bearing step for the 0.25% HT-insertion figure (b19, Table 12: k=400). The text in Sec. 7.3 asserts that 'the attacker cannot understand which isomorphic instances in the bottom/top tier relate to which in the netlist,' but no analysis or experiment supports this assertion. Under the strong threat model, the attacker holds the complete final netlist and both tier layouts, and the tier assignment is physically visible. Because all gates of a decomposed structure are kept in one tier, the attacker can observe which physical structures lie in which tier and can match their visible intra-tier connectivity against the netlist. The cited k-isomorphism result [45] concerns anonymized graph publication, not a setting where the original netlist is given and the tier partition is partially observed. A concrete test would be to implement the attacker's candidate-set computation: for each target structure, count how many physical structures remain viable after matching tier membership and visible intra-tier nets, and report the minimum as the effective k. Without such an analysis, the 1/k probability does not follow from the presented data.","section":"Sec. 7.3 / Sec. 8.2 / Table 12"},{"comment":"The reported security levels are not reconciled. Table 10 lists k=1,221 for b19 after five synthesis iterations and k=576 for b18, while Table 12 lists k=400 for b19 and k=345 for b18, despite Sec. 8.2 stating that 'The levels in 3D are the same as in 2D.' The headline probability of 0.25% is exactly 1/400, so readers need to know which k is operative and why the 3D flow changes it. If Table 12's footnote definition (sum of least-occurring structures in the bottom and top tiers) is intended, the paper must justify why this sum equals the attacker's inverse success probability per target; that is not immediate from the k-security definition in [10], which uses the minimum number of isomorphic instances in the FEOL layout. This inconsistency directly affects the paper's central quantitative claim.","section":"Table 10 vs. Table 12 / Sec. 8.2"},{"comment":"The IP-protection half of the paper rests on physical assumptions that are not validated in the manuscript. The RDL obfuscation assumes Mg/MgO vias remain indistinguishable during reverse engineering, citing [40] without additional physical validation or sensitivity analysis for the proposed switchbox implementation, and the layouts model F2F vias as regular M6/M10 vias (an 'optimistic assumption' stated in Sec. 6.1). If the RDL can be imaged or the switchbox connectivity distinguished, the claimed resilience against malicious end-users is not established. The paper should either provide a validation path for these assumptions or clearly frame the security results as conditional on them; as it stands, the security evaluation is conducted on an idealized model of the RDL.","section":"Sec. 4.2 / Sec. 5.3 / Sec. 6.1"}],"minor_comments":[{"comment":"The phrase 'entering the third dimension is eminent' appears to be a typo; 'imminent' or 'imperative' would be more appropriate.","section":"Abstract"},{"comment":"The footnote reads 'least occuring structures'; this should be 'least occurring structures.'","section":"Table 12"},{"comment":"The statement that 'only our work can readily protect against both threats' is stronger than the evidence presented, since the end-user protection relies on the unvalidated Mg/MgO assumption and the fab-based protection relies on the unproven preservation of k-security; consider softening the claim or adding a comparison table with the assumptions required by each scheme.","section":"Sec. 1"},{"comment":"The phrase 'few if any proper attacks on k-security are available yet' is vague; the authors should cite the specific known attacks or explain why existing attacks are inapplicable.","section":"Sec. 7.1.2 / Sec. 8.2"},{"comment":"The y-axis label 'Norm. Distance for F2F Vias' would be clearer with an explicit statement of what distance is normalized by (e.g., pitch or die dimension) and for which benchmark the distribution is shown.","section":"Fig. 8"}],"recommendation":"major_revision","confidential_remarks":"The paper is a credible CAD/systems contribution with reproducible tooling and DRC-clean experiments, but the HT-prevention guarantee is not yet supported: the k-security preservation argument in Sec. 7.3 is an assertion, and Tables 10 and 12 report different k values for the same benchmarks. These issues are addressable with additional formal analysis or an attacker experiment, so I do not see grounds for rejection, but the paper should not be accepted in its current form. The physical assumptions underlying the IP-protection claim (Mg/MgO vias, F2F via parasitics) also need to be stated more prominently and, if possible, validated or bounded."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The security-driven synthesis stage is the genuinely new piece, and it is well executed: it scales k-security to multi-million-gate designs, reports DRC-clean layouts from a real toolchain, tests against a public attack, and gives the designer control over which structures get protected. That is a meaningful advance over the ICCAD'18 precursor and over the prior k-security work. The experiments are extensive and the PPA trade-off studies are honest, including the fact that some random partitionings beat the 2D baseline. Credit where due: this is solid engineering work with reproducible artifacts.\n\nThe soft spot is the HT-prevention security analysis, and it is load-bearing. The headline 0.25% success probability for b19 comes from k=400, but Table 12 defines k as the sum of the least-occurring structures in the bottom and top tiers, while Table 10 reports k=1,221 for the same benchmark after the 2D synthesis stage. The text says the 3D levels are \"the same as in 2D\" without reconciling the numbers. More importantly, the claimed k-security after 3D partitioning rests on the assertion that an attacker \"cannot understand which isomorphic instances in the bottom/top tier relate to which in the netlist.\" Under their own threat model, the attacker has the complete final netlist and both tier layouts; the tier assignment is physically visible. The paper provides no argument that intra-tier connectivity cannot be matched against the netlist to determine which tier a target sits in. If the attacker can localize the tier, the candidate set drops to roughly 200, doubling the success probability to about 0.5%, and further structural hints could reduce it further. The cited formal k-isomorphism result [45] is about anonymized graph publication, not about this setting where the original netlist is given and the tier partition is partially observed.\n\nThe other concerns are real but less severe. The F2F vias are modeled as regular M6/M10 vias, which the authors acknowledge is optimistic. The Mg/MgO RDL camouflage is inherited from [40] without physical validation. The different-foundries scenario rests on an explicitly unproven belief that black-box attacks would be very challenging. All of these are worth flagging, but the k-security gap is the one that changes the conclusion.\n\nThis paper deserves a serious referee: the engineering contribution is real and the experiments are carefully done. But the HT-prevention half needs major revision before the security claims are publishable as stated. If the authors can fix the k accounting and either prove the tier-localization resistance or weaken the claim accordingly, the paper becomes solid. For now, I would cite it for the 3D SM flow and the synthesis idea, but not for the 0.25% figure.","headline":"The 3D split-manufacturing flow is a real engineering contribution, but the HT-prevention guarantee is not backed up: the reported k is defined as a sum across tiers and the paper never shows an attacker can't localize a target to one tier, which would double the claimed success probability.","tokens_in":771,"tokens_out":875,"would_cite":true,"duration_ms":54814,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper claims that splitting a chip into two stacked tiers and hiding the vertical connections with camouflaged vias can protect designs from both untrusted foundries and reverse-engineering end-users.","keywords":["3D IC","split manufacturing","layout camouflaging","hardware Trojan","IP protection","vertical interconnects","k-security","face-to-face bonding"],"falsifier":"Delayering a protected face-to-face stack and imaging the redistribution layer with a material-sensitive method, such as electron microscopy with elemental analysis, would show whether real Mg vias can be distinguished from MgO dummies. If an attacker can reliably label which vias conduct, the switchbox mappings become known and the reported correct-connection and netlist-recovery rates would be much higher than the paper's security analysis claims.","tokens_in":30556,"feed_emoji":"🧩","tokens_out":5868,"duration_ms":62104,"temperature":0.7,"pith_summary":"Split manufacturing hides a chip's layout from an untrusted foundry, while layout camouflaging hides it from a reverse-engineering end-user; each alone covers only one adversary. This paper claims that both protections can be achieved in a single flow by splitting the design across two face-to-face stacked tiers and obfuscating the vertical interconnects, so that the untrusted foundry sees two tier layouts but not the wiring that gives the design its function. The paper develops a security-driven CAD flow that randomizes and camouflages the redistribution layer between tiers, and reports DRC-clean layouts for multi-million-gate designs with moderate power, performance, and area cost. For Trojans, it adds a synthesis stage that multiplies vulnerable structures into many indistinguishable copies, making targeted insertion a matter of chance even when the attacker already holds the full netlist. If the claims hold, design houses can use advanced but untrusted foundries while protecting both their IP and their chips from malicious modification.","feed_headline":"Splitting chips across stacked tiers foils IP theft and Trojans","feed_subtitle":"A trusted back-end layer of camouflaged vertical vias lets one 3D flow protect designs from both fabs and end-users.","key_machinery":"The obfuscated vertical interconnect is the mechanism that carries the IP-protection argument: randomized F2F via placement, embedded switchboxes that map any of four drivers to any of four sinks, and Mg/MgO vias that oxidize into visually indistinguishable dummies. For Trojan prevention, the load-bearing mechanism is security-driven synthesis: vulnerable structures are re-expressed as custom cells, replicated until many isomorphic copies exist, marked as don't-touch so tools cannot alter them, then decomposed back into standard gates, lifting k-security from a post-layout heuristic to a design-time guarantee.","core_discovery":"The central claim is that \"3D splitting\" is the natural way to combine split manufacturing with layout camouflaging. The design is partitioned into two tiers fabricated by untrusted foundries and later bonded face-to-face; a trusted back-end facility grows a redistribution layer whose vertical vias realize the inter-tier connections. Randomizing the via locations destroys the proximity cues that make 2D split manufacturing attackable, while Mg/MgO vias that become indistinguishable from dummy vias under reverse engineering hide the connectivity from end-users. The same 3D infrastructure, without the camouflage, is used to prevent hardware Trojans: a security-driven synthesis stage creates many isomorphic instantiations of vulnerable gate structures, so a fab-based attacker holding the complete netlist cannot uniquely identify the target, with reported success probabilities as low as 0.25% for benchmark b19.","pith_inferences":["If the trusted-BEOL assumption holds, the flow could be adopted incrementally by packaging houses already offering face-to-face bonding, since no change to the FEOL process is required.","A direct test of the weakest assumption would be to build a small F2F test chip with Mg/MgO vias and run a standard delayering and imaging reverse-engineering flow to measure how often real vias are misclassified as dummies.","The paper's proximity attack assumes the attacker resolves all driver-sink pairings except within switchboxes; a natural next question is whether a learning-based attacker using both tier layouts and routing patterns could do better, which would tighten or weaken the reported security margins.","The same 3D-splitting idea could be extended to protect against physical attacks such as invasive probing and side-channel leakage, a direction the paper names as future work."],"forward_implications":["Design houses can fabricate at advanced but untrusted foundries while protecting new-version IP from both fabs and end-users, without relying on tamper-proof memories as logic locking does.","Targeted hardware Trojan insertion becomes probabilistically difficult even under the strong assumption that the attacker holds the complete gate-level netlist.","The reported power, performance, and area costs are often comparable to or better than conventional 2D split manufacturing and layout camouflaging, with footprint savings on large designs.","k-security, previously limited to small benchmarks, becomes scalable to multi-million-gate designs through synthesis-level replication and 3D partitioning.","SAT-based reverse-engineering attacks time out on the larger protected designs, and even a successful functional recovery of the vertical connections does not give the structural equivalence needed to place Trojans."],"supporting_citations":[{"why":"Defines k-security, the formal guarantee for Trojan insertion that this paper scales to large designs.","marker":"[10]"},{"why":"Provides the vulnerability analysis and simultaneous wire-lifting and cell-insertion framework that the security-driven synthesis stage builds on and improves.","marker":"[11]"},{"why":"Supplies the design-aware partitioning approach that inspires the 3D CAD flow's partitioning step.","marker":"[13]"},{"why":"Introduces the proximity attack on 2D split manufacturing, the baseline threat that randomization of vertical vias must defeat.","marker":"[15]"},{"why":"Proposes security-aware 2.5D split manufacturing with cut-based security, the closest prior scheme for comparison of cut sizes and PPA.","marker":"[21]"},{"why":"Supplies a representative layout-camouflaging scheme whose overheads are compared against the proposed 3D approach.","marker":"[24]"},{"why":"Provides the SAT-based reverse-engineering attack used to test the post-manufacturing security of the switchboxes.","marker":"[29]"},{"why":"Demonstrates Mg/MgO transformable interconnects that become indistinguishable under reverse engineering, the physical basis of the RDL camouflage.","marker":"[40]"},{"why":"Is the paper's own released 3D split-manufacturing attack used to measure correct connection rate, netlist recovery, and Hamming distance.","marker":"[42]"}],"fun_headline_variants":["3D splitting and via camouflage thwart IP theft and Trojans","Stacked chips with hidden vias protect against IP and Trojan attacks","3D IC split fabrication: one flow for IP and Trojan defense","Camouflaged vertical vias in 3D ICs stop IP and Trojan threats","Two attacks, one 3D split: IP and Trojan prevention"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The scheme assumes the back-end-of-line facility that grows the obfuscated redistribution layer is trustworthy and that the Mg/MgO vias really are indistinguishable after reverse-engineering delayering; if either fails, the IP-protection claim collapses.","fun_headline_variants_meta":{"raw":{"variants":["3D splitting and via camouflage thwart IP theft and Trojans","Stacked chips with hidden vias protect against IP and Trojan attacks","3D IC split fabrication: one flow for IP and Trojan defense","Camouflaged vertical vias in 3D ICs stop IP and Trojan threats","Two attacks, one 3D split: IP and Trojan prevention"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000275,"raw_usage":{"total_tokens":1661,"prompt_tokens":984,"completion_tokens":677,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":600,"completion_tokens_details":{"reasoning_tokens":592}},"tokens_in":600,"tokens_out":677,"duration_ms":7721,"temperature":1.0,"reasoning_tokens":592,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T13:58:16.451160+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Delayering a protected face-to-face stack and imaging the redistribution layer with a material-sensitive method, such as electron microscopy with elemental analysis, would show whether real Mg vias can be distinguished from MgO dummies. If an attacker can reliably label which vias conduct, the switchbox mappings become known and the reported correct-connection and netlist-recovery rates would be much higher than the paper's security analysis claims.","supporting_citations":[{"cited_title":"Jiang et al., ``A provable key destruction scheme based on memristive crossbar arrays,'' Nature Electronics, vol","cited_arxiv_id":null,"evidence_quote":"Defines k-security, the formal guarantee for Trojan insertion that this paper scales to large designs."},{"cited_title":"Imeson, A","cited_arxiv_id":null,"evidence_quote":"Provides the vulnerability analysis and simultaneous wire-lifting and cell-insertion framework that the security-driven synthesis stage builds on and improves."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the design-aware partitioning approach that inspires the 3D CAD flow's partitioning step."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Introduces the proximity attack on 2D split manufacturing, the baseline threat that randomization of vertical vias must defeat."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Proposes security-aware 2.5D split manufacturing with cut-based security, the closest prior scheme for comparison of cut sizes and PPA."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies a representative layout-camouflaging scheme whose overheads are compared against the proposed 3D approach."},{"cited_title":"Patnaik, M","cited_arxiv_id":null,"evidence_quote":"Provides the SAT-based reverse-engineering attack used to test the post-manufacturing security of the switchboxes."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Demonstrates Mg/MgO transformable interconnects that become indistinguishable under reverse engineering, the physical basis of the RDL camouflage."},{"cited_title":"Uhlig et al., ``Progress on carbon nanotube BEOL interconnects,'' in Proc","cited_arxiv_id":null,"evidence_quote":"Is the paper's own released 3D split-manufacturing attack used to measure correct connection rate, netlist recovery, and Hamming distance."}],"review_version":1}