{"id":"75158cb5-ece6-4588-a2d2-84b8aa655c75","arxiv_id":"1908.04610","paper_version":1,"verdict":"ACCEPT","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"The paper derives an incremental form of discrete-time ADRC, adds rate and magnitude limiting with anti-windup, and provides formulas for bumpless controller enabling and parameter changes.","lead":"This paper gives practical recipes for implementing active disturbance rejection control on digital controllers, including the ability to limit how fast the control signal changes and to switch controllers or parameters without jumps. It introduces an incremental version of ADRC and shows with simulations that these features work without the usual windup problems.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Sect. V-C.3 omits updating control-law gain w when b0 changes for non-transformed ADRC; following the text as written produces a control step.","rationale":"The reader's weakest assumption concerned the carry-over term in Eq. (22) accumulating or destabilizing the loop during prolonged saturation. I checked this first: with the initialization in Eq. (27), the desired pre-limiter signal w(k) satisfies w(k)=w(k-1)+Delta u_NI(k), so the incremental implementation reconstructs the non-incremental unlimited control law u_NI(k)=K_p/b0 r(k)-w^T xhat(k). Thus the carry-over is not an independent integrator that winds up; it is a state reconstruction, and the anti-windup behavior is the standard observer-fed-by-limited-input scheme. That weakens the reader's nominated concern. The more concrete problem is in Sect. V-C.3: when b0 is changed, the non-transformed control-law gain w is never updated, although w in Eq. (5) contains 1/b0. Since the paper promises detailed guidelines for all four ADRC variants (non-incremental/incremental, standard/lag-reduced), this missing step directly undermines the bumpless parameter-change claim for the standard non-transformed variants. This is a specific, checkable omission rather than an absence of formal stability theory, so I recommend a conditional acceptance pending correction or explicit clarification.","tokens_in":11991,"tokens_out":23011,"duration_ms":226849,"concrete_test":"Simulate the first-order non-transformed ADRC (Eqs. 7-9) on any stable plant at steady state r=y, with initial b0_old. At time k apply a b0 change by factor 2 exactly as Sect. V-C.3 states: scale B_d/B_ESO by 2 and x2 by 2 (Eq. 31), but leave w in (5) unchanged. Compute u(k+1) via (9); it will equal 2u(k), a clear bump. Repeat the same change after recomputing w with b0_new; the control value remains u(k). This single experiment isolates whether the missing w-update is the cause.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The load-bearing gap is in the bumpless b0-change recipe, not in the rate-limiter carry-over. In Sect. V-C.3 the paper scales B_d and B_ESO by b0/b0^old (Eq. 29) and rescales the last observer state (Eq. 31), but for the non-lag-reduced variants of Sect. II-B/C the control law (9) uses w^T explicitly containing 1/b0: w^T=(K_p,1)/b0 (first order) or (K_p,K_D,1)/b0 (second order). The section never says to recompute w with the new b0. If the instructions are followed literally, a stationary-state analysis gives u' = -x2_new/b0_old = (b0_new/b0_old)u, so the control signal jumps by the b0 ratio immediately after the change. The transformed/lag-reduced treatment handles this through T^{-1} (Eqs. 14-15), but the non-transformed non-incremental and incremental variants are left incomplete. Because the paper's strongest claim is that all steps for all four ADRC implementations are described, this omission is decisive for that claim.","agreement_with_reader":"disagree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents practical implementation recipes for discrete-time active disturbance rejection control (ADRC), covering an incremental formulation, magnitude and rate limiting, and bumpless transfer between manual/automatic modes and during parameter changes. The new contributions are the incremental ADRC equations (16)-(19), the carry-over term in Eq. (22) for limited incremental control, and the bumpless parameter-change formulas in Section V-C. The claims are supported by a buck-converter simulation study in Section VI.","tokens_in":12218,"tokens_out":4698,"duration_ms":44764,"significance":"If the recipes are correct, the paper fills a genuine gap for practitioners by turning standard ADRC into an implementation-oriented package with explicit step-by-step instructions, including the rarely treated rate limiting. The incremental formulation and the carry-over term are plausibly new and practically useful. The derivations are largely algebraic and consistent with established anti-windup practice (Aström and Rundqvist, Ref. [20]). However, the completeness claim that 'all steps are described' for all four ADRC variants is weakened by an omission in the b0-change recipe for the non-lag-reduced variants.","major_comments":[{"comment":"The recipe for changing b0 does not state that the control-law gain vector w^T in Eq. (5)/(9) must be recomputed for the non-transformed (standard) ADRC variants. Since w^T contains an explicit 1/b0 factor, following the text literally leaves w with the old b0. In a stationary state with r=y, the control signal after the change scales as u' = (b0_new/b0_old) * u_old, producing a jump whenever b0 changes, which contradicts the paper's bumpless-transfer claim. The transformed/lag-reduced variant avoids this through the rescaling in Eq. (30), but the non-transformed non-incremental and incremental variants are left incomplete. The fix is a one-sentence instruction to recompute w^T with the new b0, and similarly to use the new w in Eq. (27) when reinitializing Δu(k-1); as written, the paper's strongest claim is not met for these variants.","section":"Sect. V-C.3, Eqs. (29)-(31)"}],"minor_comments":[{"comment":"The simulation study does not include an example of a b0 change as described in Sect. V-C.3, despite b0 changes being one of the three parameter-change categories; adding such an example would increase confidence in the recipe.","section":"Sect. VI-D"},{"comment":"The sentence 'changing b0 only results in a scaling factor (T^{-1} · T_old = b0_old / b0)' is easy to misread; the intended factor is the ratio b0^old/b0, and the notation should be made explicit, e.g., using a superscript 'old' throughout.","section":"Sect. V-C.3"},{"comment":"Ref. [20] spells the second author's name 'Rundqwist'; the correct spelling is 'Rundqvist'.","section":"References"},{"comment":"The phrase '400 % increased closed-loop settling time' is ambiguous; it should state the old and new settling times explicitly (e.g., 'from 2 ms to 10 ms').","section":"Fig. 14 caption"},{"comment":"A brief intuitive explanation of why the carry-over term prevents stationary error during limiting would be helpful; currently the anti-windup rationale is implicit.","section":"Sect. IV, Eq. (22)"}],"recommendation":"major_revision","confidential_remarks":"The issue raised in Major Comment 1 is genuine and was not identified in the reader's report. It directly affects the paper's core claim of providing complete instructions for all four ADRC variants, and it should be corrected before publication. The rest of the paper is a solid practical contribution well within the journal's scope."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is a genuinely useful practical paper, and the incremental ADRC plus the carry-over term are real contributions. But the bumpless b0-change recipe for the non-transformed variants has a hole that the paper's own conclusion overstates.\n\nThe incremental formulation in Sect. III is a clean algebraic repackaging of the observer/controller equations, and Eq. (22) is a sensible anti-windup carry-over for the incremental case. The paper is also honest about its assumptions: steady state at transfer time, no formal stability proof for the limited loop. For what it claims to be—implementation guidelines for drives and power electronics—it is largely sound. The simulations are simple but support the qualitative claims. The citation pattern is reasonable; [17] is the right source for the lag-reduced form.\n\nThe soft spot is Sect. V-C.3. For the transformed/lag-reduced variants the recipe works because the state transform absorbs b0 and w stays all-ones. For the standard non-transformed variants of Sect. II-B/C, the control law (9) uses w^T=(Kp,1)/b0 (or (Kp,Kd,1)/b0). When b0 changes, the text rescales B_d, B_ESO, and the last observer state, but never says to recompute w (or the Kp/b0 feedforward term) with the new b0. Following the instructions literally, a stationary-state calculation gives the control signal scaled by b0_new/b0_old immediately after the change—exactly the bump the section is supposed to prevent. The incremental variants partly dodge this because (27) is recomputed with the updated b0 and w, but the non-incremental standard variant is left incomplete. That is a genuine gap, and it is in one of the three headline contributions, not a side remark.\n\nIs it fatal? No. It is a missing line in an otherwise careful recipe, and the fix is obvious: recompute w and the feedforward coefficient with the new b0 before applying (31). The observer rescaling logic is otherwise consistent. The paper's central claim—'all steps are described for all four implementations'—is too strong as written, but the core material is worthwhile.\n\nI'd send it to a serious referee; the incremental form and the carry-over term deserve scrutiny, and a referee can flag the b0 recipe. It is not a desk reject. But the author should be asked to fix V-C.3 before final.","headline":"Useful practical ADRC implementation paper with a real hole in the bumpless b0-change recipe for non-transformed variants.","tokens_in":12732,"tokens_out":4061,"would_cite":true,"duration_ms":38598,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper gives step-by-step ADRC implementations that switch control modes without signal bumps and survive magnitude and rate limits.","keywords":["active disturbance rejection control","ADRC","incremental algorithm","bumpless transfer","rate limitation","anti-windup","extended state observer","discrete-time control"],"falsifier":"Let the incremental ADRC from Eq. (22) act on a plant with a known pole at the origin, drive the reference so that the rate limiter stays active for many closed-loop time constants, and record the accumulated carry-over term: if $|\\Delta u(k-1)-\\Delta u_{\\mathrm{lim}}(k-1)|$ grows without bound or the output shows a limit cycle, the anti-windup claim fails. Equivalently, an analytical stability test of the saturated loop with the carry-over term would settle the question.","tokens_in":11796,"feed_emoji":"⚙️","tokens_out":4699,"duration_ms":44430,"temperature":0.7,"pith_summary":"Active disturbance rejection control (ADRC) is attractive because it treats model error and real disturbances as one generalized disturbance to be estimated and cancelled. The paper's claim is that ADRC can be made fully practical: it gives a discrete-time recipe in which the controller can be run in incremental form, its output can be limited in magnitude and rate without windup, and it can be switched on, switched between controllers, or have its parameters changed without jumps in the control signal. The three load-bearing additions are an incremental ADRC update law, a carry-over term in the incremental limiter, and a set of state-reinitialisation formulas for bumpless parameter changes. The paper demonstrates all of it on a simulated current-mode buck converter.","feed_headline":"Bumpless switching and rate limits now fit into ADRC loops","feed_subtitle":"Discrete-time ADRC can switch modes and change parameters without jumping the control signal.","key_machinery":"The machinery is the discrete-time extended state observer (ESO), which estimates output, derivatives, and the generalised disturbance in one update, plus a controller that uses the estimated states to cancel that disturbance. On top of this, the paper builds an incremental variant in which the controller outputs an increment of the control signal, and a magnitude/rate limiter that clips both the absolute level and the step size of that increment. The load-bearing part is the carry-over term in Eq. (22), $\\Delta u(k-1) - \\Delta u_{\\mathrm{lim}}(k-1)$, which feeds the clipped control effort back into the next increment so the controller keeps aiming at the value it would have chosen without the limiter. Bumpless transfer is carried by the state initialisation and parameter rescaling formulas in Sect. V.","core_discovery":"The central claim is a complete implementation scheme for discrete-time ADRC with the practical features an industrial loop needs. For the incremental form, Eq. (22) adds the difference between the desired and the actually applied control increment at the previous step to the current increment, so the forgotten control effort is not lost when saturation or rate limiting clips the command. For bumpless transfer, the paper gives explicit formulas: initialise the observer state from the measured output and last control value (Sect. V-A), initialise the incremental term from the previous reference and limited control value when enabling the controller (Sect. V-B), and rescale the state vector and observer matrices according to the changed controller, observer, or plant-model parameter (Sect. V-C). With these steps, switching modes or changing parameters at steady state produces no visible bump in output or control signal, as the simulations in Sect. VI confirm.","pith_inferences":["The promise of bumpless parameter changes is stated for steady state with $r = y$; a natural extension the author leaves implicit is a formal derivation of the state rescaling for changes during transients, where the formulas would need to account for the current tracking error.","The carry-over term in Eq. (22) is an integral-like memory of clipped control effort; this suggests the incremental ADRC with limiter has a natural connection to classical conditional-integration anti-windup schemes, and could be compared against them on the same benchmark.","A hardware test on a real converter or servo drive would be the next step beyond simulation; the paper's noise example already hints that rate limiting can double as a noise filter, which is worth quantifying separately.","One could test whether the same bumpless formulas extend to adaptive or nonlinear ADRC variants, since the observer-state rescaling logic does not depend on the linear bandwidth parameterisation."],"forward_implications":["A practitioner can implement ADRC in either non-incremental or incremental form, with or without magnitude and rate limiting, using only the equations collected in the paper.","Rate limiting becomes a practical tool for ADRC: it bounds how fast the control signal can rise after reference or disturbance steps and also attenuates measurement noise in the control signal.","Incremental ADRC can share a common limiting integrator with other incremental controllers, so switching between, say, incremental PI control and incremental ADRC is done without jumps.","Controller and observer parameters can be changed online while the loop is running, provided the state vector is rescaled according to Sect. V-C and the change is made at steady state with $r = y$.","The anti-windup property of feeding the limited control signal into the observer is preserved for both magnitude and rate limits."],"supporting_citations":[{"why":"Supplies the ADRC structure, the lag-reduced observer form, and the observation that feeding the saturated control signal into the observer avoids windup.","marker":"[17]"},{"why":"Provides the bandwidth-parameterisation tuning rule used to set the closed-loop and observer poles.","marker":"[18]"},{"why":"Supplies the discrete-time current-observer implementation of the extended state observer that the paper builds on.","marker":"[19]"},{"why":"Contributes the anti-windup principle of re-feeding the limited control signal into the controller state.","marker":"[20]"},{"why":"Provides the current-mode buck converter model used in the simulation examples.","marker":"[21]"}],"fun_headline_variants":["ADRC gets bumpless switching and rate limits","Bumpless transfer and rate limiting for ADRC loops","Practical ADRC: Bumpless, rate-limited, incremental","Discrete ADRC with smooth switching and safe rate limits","Incremental ADRC: smooth mode changes and rate clamps"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The anti-windup and bumpless behaviour rests on the assumption that feeding the limited control signal back into the observer keeps the observer's internal model consistent with the real plant, and that the carry-over term in Eq. (22) stays bounded and does not destabilise the loop during prolonged saturation; this is shown in simulation, not proven analytically.","fun_headline_variants_meta":{"raw":{"variants":["ADRC gets bumpless switching and rate limits","Bumpless transfer and rate limiting for ADRC loops","Practical ADRC: Bumpless, rate-limited, incremental","Discrete ADRC with smooth switching and safe rate limits","Incremental ADRC: smooth mode changes and rate clamps"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000247,"raw_usage":{"total_tokens":1480,"prompt_tokens":821,"completion_tokens":659,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":437,"completion_tokens_details":{"reasoning_tokens":577}},"tokens_in":437,"tokens_out":659,"duration_ms":6680,"temperature":1.0,"reasoning_tokens":577,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T13:36:51.290355+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Let the incremental ADRC from Eq. (22) act on a plant with a known pole at the origin, drive the reference so that the rate limiter stays active for many closed-loop time constants, and record the accumulated carry-over term: if $|\\Delta u(k-1)-\\Delta u_{\\mathrm{lim}}(k-1)|$ grows without bound or the output shows a limit cycle, the anti-windup claim fails. Equivalently, an analytical stability test of the saturated loop with the carry-over term would settle the question.","supporting_citations":[{"cited_title":"A simulative study on active disturbance rejection control (ADRC) as a control tool for practitioners,","cited_arxiv_id":null,"evidence_quote":"Supplies the ADRC structure, the lag-reduced observer form, and the observation that feeding the saturated control signal into the observer avoids windup."},{"cited_title":"Scaling and bandwidth-parameterization based controller tun- ing,","cited_arxiv_id":null,"evidence_quote":"Provides the bandwidth-parameterisation tuning rule used to set the closed-loop and observer poles."},{"cited_title":"Discrete implementation and generalization of the extended state observer,","cited_arxiv_id":null,"evidence_quote":"Supplies the discrete-time current-observer implementation of the extended state observer that the paper builds on."},{"cited_title":"Integrator windup and how to avoid it,","cited_arxiv_id":null,"evidence_quote":"Contributes the anti-windup principle of re-feeding the limited control signal into the controller state."},{"cited_title":"A new, continuous-time model for current-mode control,","cited_arxiv_id":null,"evidence_quote":"Provides the current-mode buck converter model used in the simulation examples."}],"review_version":1}