{"id":"681c970d-9746-4c94-8b65-9b716ed2d6b9","arxiv_id":"1908.05853","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A 200 nm recessed-gate AlGaN/GaN MOS-HEMT on Si reaches VTH above 5 V and on-current near 0.5 A/mm, a combination absent from the cited comparison table.","lead":"Recessed-gate GaN transistors on silicon were made with a threshold voltage above 5 V and an on-current near 500 mA/mm. The result is a useful data point in the effort to build safe, high-current, normally-off power switches.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The headline VTH value is ambiguous: the paper uses 5 V, >5 V, and +5.1 V without a defined extraction method, so the central simultaneous VTH/on-current claim is not yet pinned down.","rationale":"The reader's weakest_assumption already identifies the same issue, and I agree with it. The strongest claim in Section III is a quantitative record claim, and the two numbers that define it come from one set of transfer and output curves. No statistical support is given, and the paper does not define the VTH extraction convention. The inconsistency between 5 V, >5 V, and +5.1 V is not cosmetic: fixed-charge shifts from annealing can move the linear-extrapolation intercept by volts, and a threshold that appears above 5 V under one convention could be below 5 V under another. The measured curves are internally consistent and the fabrication sequence is detailed enough to be reproduced, so the work is a plausible engineering demonstration rather than an invalid one. The correct disposition remains the reader's CONDITIONAL verdict: accept the demonstration as a single-device report, but require raw transfer data, a defined extraction method, and multi-device statistics before the title-level claim is treated as established. My read does not move the verdict, hence UNCHANGED.","tokens_in":5579,"tokens_out":6499,"duration_ms":64445,"concrete_test":"Digitize or obtain the raw ID(VG) data behind Fig. 3(C) and Fig. 5(B); fix a published convention (x-intercept of the linear fit at maximum gm over VGS = 6-10 V) and recompute VTH. Then repeat the transfer and output sweeps on three to five nominally identical Device III dies from the same wafer and report mean ± spread. If the recomputed threshold falls below 5 V, or if the die-to-die spread covers 5 V, the title-level \"VTH > 5 V\" claim is not supported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim in Section III is that Device III exhibits \"excellent on-current (500 mA/mm) and VTH (>5 V) combinations reported till date.\" This claim rests on a threshold-voltage number that the paper never defines: the title says VTH > 5 V, the abstract says VTH = 5 V, Table I says +5.1 V, and the text says \">5 V\" after PMA. A linear-extrapolation VTH changes with the chosen tangent window, the drain bias, and the sweep direction; for an enhancement-mode device, the difference between 4.9 V and 5.1 V is exactly the entire claim. The only supporting data are one transfer curve at VDS = 5 V (Fig. 3(C)) and one output family (Fig. 4(C)). No second device, no optical or electrical yield data, and no error bars are reported. For the record claim to land, the quoted threshold must be a reproducible, convention-defined result, not a single-curve artifact. That condition is not established.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports the fabrication and characterization of a normally-off (enhancement-mode) AlGaN/GaN MOSFET on a silicon substrate, using a 200 nm gate recess with 124 nm recess depth and a 30 nm Al2O3 gate dielectric. Three device variants with different recess depths and post-dielectric-anneal temperatures are compared; the optimized Device III shows a threshold voltage above 5 V and an on-current near 500 mA/mm. The authors also present three-terminal breakdown measurements and use Silvaco TCAD simulations to argue that residual electric-field penetration into the recess region limits the breakdown voltage of deeply scaled recess-gate devices.","tokens_in":5773,"tokens_out":3145,"duration_ms":30883,"significance":"If the reported data are reproducible, the paper provides a useful data point for normally-off GaN power devices: a simple 200 nm recess process on a silicon substrate achieving simultaneously a linear-extrapolation threshold voltage above 5 V and an on-current near 0.5 A/mm. The comparison table in Table I directly situates the result against prior work. The paper's central experimental claim is grounded in measured transfer and output characteristics rather than in simulation, and the TCAD analysis, while not fully matching the device geometry, represents a reasonable qualitative attempt to explain the observed limited breakdown. The main weaknesses are the absence of device statistics and the ambiguity in the definition and reporting of VTH, both of which affect the strength of the headline claim.","major_comments":[{"comment":"The threshold-voltage value defining the headline claim is not consistently reported: the title says VTH > 5 V, the abstract says VTH = 5 V, Table I lists +5.1 V, and Section III (after Fig. 3(C)) says VTH was found to be '>5 V' after PMA. Because '>5 V' appears to be a display limit rather than an extracted value, and because no linear-extrapolation window or current-criterion is specified, the exact VTH of the reported device is ambiguous. Please define the extraction method precisely, report the extracted value for the measured device, and state whether 5.1 V is the extracted number used in Table I.","section":"Title, Abstract, Section III, Table I"},{"comment":"The central claim of on-current 500 mA/mm and VTH > 5 V rests on a single transfer curve and a single output family for Device III. No device-to-device statistics, error bars, or number of measured devices are reported, so it is not possible to determine whether the quoted values are representative of the process or a favorable single-device result. Please provide data from multiple devices and report the spread in VTH and on-current.","section":"Section III, Figs. 3(C) and 4(C)"},{"comment":"The TCAD simulations use a recess depth of 35 nm (25 nm AlGaN + 10 nm GaN), whereas the fabricated Device III has a recess depth of 124 nm. The simulated electric-field profiles therefore do not represent the geometry of the device whose breakdown was measured, and the conclusion that residual field penetration into the recess causes premature breakdown is not directly supported. Please either simulate a 124 nm deep recess or justify explicitly why the 35 nm case captures the relevant physics for Device III.","section":"Section III, TCAD discussion and Fig. 6"}],"minor_comments":[{"comment":"The text 'samples were placed at an angle of 10 °C from the horizontal' should read '10°', since the unit is a degree of angle, not Celsius.","section":"Section II"},{"comment":"Reference [11] lists the journal as 'ACS Appl. Electrosn. Mater.'; the correct abbreviation is 'ACS Appl. Electron. Mater.'.","section":"References"},{"comment":"The symbol 'Lfp' is used in the Fig. 3 caption without being defined in the text; please define it.","section":"Fig. 3 caption"},{"comment":"The sentence 'The device III exhibited excellent on-current (500 mA/mm) and VTH (>5V) combinations reported till date' is grammatically incomplete; it should read '... the best combination of on-current and VTH reported to date'.","section":"Section III"},{"comment":"In the Conclusion, 'residuals electric fields' should be 'residual electric fields'.","section":"Conclusion"},{"comment":"The material parameter sets 'kp.set2' and 'pol.set2' used in Silvaco ATLAS are not described; please provide references or parameter values so the simulation can be reproduced.","section":"Section III, TCAD paragraph"},{"comment":"The SEM image in Fig. 2 has no scale bar; please add one to allow the gate length and recess geometry to be verified.","section":"Fig. 2"}],"recommendation":"major_revision","confidential_remarks":"The paper is a short device-demonstration letter. The core measured claim is plausible and well aligned with the journal's scope, but the ambiguity in VTH reporting and the absence of device statistics need to be resolved before the headline numbers can be accepted. The TCAD section is the weakest part because it does not use the fabricated device geometry; this should be acknowledged or corrected. Refs. [12]–[14] are authored by co-authors, but they are used for the fixed-charge explanation and are appropriate in that context."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Read this if you care about normally-off GaN power switches. The fabricated device is real: recess length 200 nm, depth 124 nm, PDA/PMA at 500 C, and the transfer and output curves in Figs. 3C and 4C do show threshold around 5 V and on-current near 500 mA/mm. In Table I, that combination beats the cited prior work on both axes simultaneously, which is a legitimate engineering data point. The paper is also honest about the ~40 V breakdown and does not oversell the TCAD part; the simulation is used only to suggest a qualitative breakdown mechanism, not to derive the headline numbers. That is worth something.\n\nThe soft spots are real but not fatal. The threshold voltage is quoted three ways: title says >5 V, abstract says 5 V, Table I says +5.1 V, and the text says >5 V after PMA. No extraction method is given — no linear-extrapolation window, no drain-bias convention, no sweep direction. For an enhancement-mode device, the difference between 4.9 V and 5.1 V is the entire claim. Second, the headline rests on a single device. There are no error bars, no device statistics, no yield data. That is typical for a process demonstration but it means the \"best reported\" claim is not yet pinned down. Third, the TCAD breakdown study uses a 35 nm recess depth while the fabricated device has 124 nm; the authors acknowledge the geometry mismatch, but it does weaken the mechanism attribution. None of these undermine the basic observation, but together they mean the paper is a plausible demonstration, not a fully verified process.\n\nThe citation pattern is fine. The self-citations to refs 12-14 support the interface fixed-charge explanation, which is a known mechanism, and the comparison table is useful even if the extraction methods in different references may not be exactly aligned.\n\nWho gets value: anyone working on recessed-gate GaN MOSFETs or threshold-voltage engineering. It is a competent engineering report, not a breakthrough. A serious referee should see it, mainly to make the authors define VTH and show a second device. That is a heavy-revision request, not a reject.\n\nMy recommendation: send it to peer review, conditional on the VTH extraction and device-to-device reproducibility being clarified.","headline":"A genuine, incremental device demonstration with the best VTH/on-current combination in its own comparison table, held back by an undefined VTH extraction and single-device support.","tokens_in":6382,"tokens_out":1070,"would_cite":false,"duration_ms":12243,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A recessed-gate AlGaN/GaN MOSFET on silicon achieves a threshold voltage above 5 V with an on-current of 500 mA/mm, a combination the paper says is the best reported so far for normally-off GaN devices.","keywords":["AlGaN/GaN","normally-off HEMT","recessed-gate MOSFET","threshold voltage","on-current","post-metal anneal","enhancement-mode","power electronics"],"falsifier":"Fabricate multiple devices with the same recess and anneal recipe, extract VTH with a fixed linear-extrapolation rule, and plot the distribution of threshold against on-current; if the typical device does not reach above 5 V while sustaining 500 mA/mm, the record-combination claim is falsified. A more targeted check is a wafer-scale VTH map: large spatial variation would show that the single Device III result is not process-representative.","tokens_in":5389,"feed_emoji":"⚡","tokens_out":6132,"duration_ms":55663,"temperature":0.7,"pith_summary":"This paper reports a normally-off AlGaN/GaN transistor on a silicon substrate in which a 200 nm-long, 124 nm-deep recess etched under the gate removes the two-dimensional electron gas at zero bias, making the device enhancement-mode. By varying recess depth and post-deposition annealing conditions, the authors tuned the threshold voltage and obtained an optimized device with threshold voltage above 5 V and on-current of about 500 mA/mm. These two numbers together, the paper argues, are the best normally-off combination reported among the devices it tabulates. The result matters because normally-off GaN transistors with high threshold and high current are desired for fail-safe power switching, and most prior devices traded one against the other. The paper also identifies a limitation of the deeply recessed gate: destructive breakdown near 40 V, which 2D-TCAD simulations attribute to residual electric field penetrating the short recess region.","feed_headline":"Deep gate recess beats 5 V and 500 mA/mm in GaN","feed_subtitle":"A 200 nm recessed gate makes an enhancement-mode AlGaN/GaN MOSFET on silicon with record normally-off current.","key_machinery":"The key object is the gate recess: a 200 nm trench etched through the AlGaN barrier and into the GaN channel (124 nm total depth), so that under the gate the two-dimensional electron gas is removed and the device turns off at zero gate bias; an ALD-grown Al2O3 layer of 30 nm then separates the gate metal from the etched GaN. The second control is the post-deposition and post-metal anneal at 500 C in forming gas, which shifts VTH positive by reducing interface fixed charge, moving Device III from about 2 V before anneal to above 5 V after. A field plate extends over the access region. The combination of a deep recess (high VTH) and a short gate length (high current) carries the claimed performance, while the 2D-TCAD electric-field simulation explains why the short recess leaves residual electric field across most of the recess and leads to early breakdown.","core_discovery":"The central claim, made for the device labelled Device III, is that a recessed-gate AlGaN/GaN MOSFET with a 124 nm recess depth, a 30 nm ALD-grown Al2O3 gate dielectric, and a 500 C post-metal anneal achieves simultaneous normally-off operation (threshold voltage above 5 V by linear extrapolation, listed as +5.1 V in Table I) and a drain current of 500 mA/mm at gate and drain biases of 10 V and 5 V. The paper states that this is the best on-current and VTH combination among normally-off devices reported to date, comparing against prior recessed-gate, fluorine-implanted, and p-GaN/p-AlGaN devices whose thresholds and currents range from about +1 V at 200 mA/mm to +7.6 V at 355 mA/mm. The positive threshold shift after post-metal annealing is attributed to a reduction of fixed charge at the Al2O3/GaN interface.","pith_inferences":["If the 500 mA/mm and above-5 V combination reproduces across devices, a natural next step is a longer recess or graded recess to push breakdown voltage upward while retaining high threshold, a direction the authors themselves suggest.","The threshold-voltage comparison across Table I assumes a consistent linear-extrapolation convention; a constant-current definition such as 1 mA/mm could shift VTH by a volt or more, so the 'best combination' claim is sensitive to the extraction rule.","The TCAD-based residual-field explanation implies a testable relationship: breakdown voltage should increase monotonically with recess length in otherwise identical devices, which a simple recess-length series could verify.","Because the claimed performance depends on the Al2O3/etched-GaN interface, interface-trap characterization of the recess sidewall would indicate whether the positive threshold is stable under bias and temperature stress."],"forward_implications":["A 200 nm recess with 124 nm depth is sufficient to deplete the 2DEG and maintain enhancement-mode operation with threshold voltage above 5 V.","Post-metal annealing in forming gas at 500 C can raise VTH by several volts, providing a process lever for threshold control in recessed-gate GaN devices.","The same process on a silicon substrate can deliver on-current near 0.5 A/mm, comparable to many normally-on HEMTs and removing one practical objection to enhancement-mode GaN power switches.","The deep short recess limits three-terminal breakdown to roughly 40 V, so the demonstrated device is not suitable for power blocks above that voltage without a longer recess or improved etched-GaN interface."],"supporting_citations":[{"why":"A recessed Al2O3/GaN MOSFET with 7.6 V threshold: the highest-VTH comparison entry the paper's device must beat.","marker":"[3]"},{"why":"A 600-V normally-off fluorine-implanted MIS-HEMT with 3.6 V threshold and 430 mA/mm: the closest on-current among the tabulated entries.","marker":"[4]"},{"why":"An early recessed MIS-gate HFET demonstrating high-threshold normally-off operation, used as a baseline in the comparison table.","marker":"[5]"},{"why":"A fully recessed AlGaN/GaN MOSFET on a silicon substrate, another comparison point for threshold and current.","marker":"[6]"},{"why":"A 6.5 V threshold MIS-HEMT using a fluorinated gate stack: the prior entry combining high VTH with moderate current that this work extends.","marker":"[10]"},{"why":"Interface charge engineering for enhancement-mode GaN MIS-HEMTs; supplies the mechanism behind the VTH shift attributed to fixed interface charge.","marker":"[12]"},{"why":"Interface trap study in similar MOS-HEMT structures used to interpret the Al2O3/GaN interface behavior reported here.","marker":"[13]"},{"why":"A study of an alternative high-k dielectric on InAlN/GaN providing background on interface properties and annealing effects.","marker":"[14]"},{"why":"A leakage-current study in GaN pn diodes invoked to support the explanation of field-induced carrier transport through interfaces.","marker":"[15]"},{"why":"A report of robust SiN/AlGaN interfaces in passivated GaN HEMTs, cited as evidence that interface leakage is a known concern in III-nitride devices.","marker":"[16]"}],"fun_headline_variants":["GaN MOSFET hits 5 V threshold and 0.5 A/mm current","Recessed gate GaN on Si: 5 V threshold, 500 mA/mm","Deep recess makes GaN e-mode with 5 V and 0.5 A/mm","200 nm gate recess yields GaN e-mode, 5 V, 0.5 A/mm","Normally-off GaN on Si achieves 5 V and 0.5 A/mm"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The headline numbers come from single-device measurements of one fabricated device, shown in one transfer curve and one output curve, with no device-to-device statistics and no explicit statement of the threshold-voltage extraction rule; if that device is not representative of the process, or if its threshold is measured differently from the comparison table, the 'best reported combination' claim does not hold.","fun_headline_variants_meta":{"raw":{"variants":["GaN MOSFET hits 5 V threshold and 0.5 A/mm current","Recessed gate GaN on Si: 5 V threshold, 500 mA/mm","Deep recess makes GaN e-mode with 5 V and 0.5 A/mm","200 nm gate recess yields GaN e-mode, 5 V, 0.5 A/mm","Normally-off GaN on Si achieves 5 V and 0.5 A/mm"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000707,"raw_usage":{"total_tokens":3167,"prompt_tokens":907,"completion_tokens":2260,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":523,"completion_tokens_details":{"reasoning_tokens":2154}},"tokens_in":523,"tokens_out":2260,"duration_ms":15083,"temperature":1.0,"reasoning_tokens":2154,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T13:03:29.451463+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Fabricate multiple devices with the same recess and anneal recipe, extract VTH with a fixed linear-extrapolation rule, and plot the distribution of threshold against on-current; if the typical device does not reach above 5 V while sustaining 500 mA/mm, the record-combination claim is falsified. A more targeted check is a wafer-scale VTH map: large spatial variation would show that the single Device III result is not process-representative.","supporting_citations":[{"cited_title":"7.6 V Threshold Voltage High-Performance Normally-Off Al 2 O 3 /GaN MOSFET Achieved by Interface Charge Engineering,","cited_arxiv_id":null,"evidence_quote":"A recessed Al2O3/GaN MOSFET with 7.6 V threshold: the highest-VTH comparison entry the paper's device must beat."},{"cited_title":"600-V Normally Off SiNx AlGaN/GaN MIS- HEMT With Large Gate Swing and Low Current Collapse,","cited_arxiv_id":null,"evidence_quote":"A 600-V normally-off fluorine-implanted MIS-HEMT with 3.6 V threshold and 430 mA/mm: the closest on-current among the tabulated entries."},{"cited_title":"AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications,","cited_arxiv_id":null,"evidence_quote":"An early recessed MIS-gate HFET demonstrating high-threshold normally-off operation, used as a baseline in the comparison table."},{"cited_title":"Performance of Fully Recessed AlGaN/GaN MOSFET Prepared on GaN Buffer Layer Grown With AlSiC Precoverage on Silicon Substrate,","cited_arxiv_id":null,"evidence_quote":"A fully recessed AlGaN/GaN MOSFET on a silicon substrate, another comparison point for threshold and current."},{"cited_title":"6.5 V High Threshold Voltage AlGaN/GaN Power Metal-Insulator-Semiconductor High Electron Mobility Transistor Using Multilayer Fluorinated Gate Stack,","cited_arxiv_id":null,"evidence_quote":"A 6.5 V threshold MIS-HEMT using a fluorinated gate stack: the prior entry combining high VTH with moderate current that this work extends."},{"cited_title":"Interface charge engineering for enhancement-mode GaN MISHEMTs,","cited_arxiv_id":null,"evidence_quote":"Interface charge engineering for enhancement-mode GaN MIS-HEMTs; supplies the mechanism behind the VTH shift attributed to fixed interface charge."},{"cited_title":"Interface traps at Al 2 O 3 / InAlN / GaN MOS- HEMT -on- 200 mm Si,","cited_arxiv_id":null,"evidence_quote":"Interface trap study in similar MOS-HEMT structures used to interpret the Al2O3/GaN interface behavior reported here."},{"cited_title":"Study on leakage current of pn diode on GaN substrate at reverse bias,","cited_arxiv_id":null,"evidence_quote":"A leakage-current study in GaN pn diodes invoked to support the explanation of field-induced carrier transport through interfaces."}],"review_version":1}