{"id":"39b887ca-568f-4220-838a-d119e8404748","arxiv_id":"1908.06841","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A comparison of ternary and binary CNTFET circuits shows that ternary arithmetic requires far more than 1.58 times the transistors of binary, so binary remains the practical radix.","lead":"The paper challenges the classic claim that ternary logic is the ideal base for computing, arguing that a corrected cost model and real carbon-nanotube transistor counts make binary logic the better choice. It is a useful reality check for designers and researchers weighing multivalued logic for future chips.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Section II.C's Eq. (2) is an unproved cost-model assumption that bakes in R=2; the abstract's 'disproved' overstates, though the transistor-count comparison remains a credible narrower result.","rationale":"The reader's weakest_assumption correctly identifies Section II.C's Eq. (2) as the load-bearing theoretical step. I read the entire manuscript in good faith: the empirical sections provide a concrete, useful comparison of published CNTFET circuits, and the author is appropriately cautious about transistor count being only an estimate and about not running simulations. The multiplier comparison is particularly explicit (5x5 ternary: 6190 transistors vs 8x8 binary: 2382). However, the theoretical 'disproof' of Hurst's e-optimality result does not follow from replacing the original cost model with an unproved R(R-1) scaling. The paper itself flags the step as an assumption ('Let's assume'), and no derivation or fit to published multi-valued circuit complexity is provided. This matters because the abstract's headline claim is that the e-radix demonstration 'is disproved', not merely that a different cost model favors binary. The empirical data can support a narrower, engineering conclusion; they cannot validate the chosen cost model retroactively. I agree with the reader that the appropriate resolution is to keep the paper conditional: soften the 'disproved' language and scope the conclusion to the compared designs. No verdict change is needed beyond the reader's conditional recommendation.","tokens_in":9588,"tokens_out":8643,"duration_ms":86976,"concrete_test":"Test the scaling in Eq. (2) against the paper's own circuit data. Using Table II and Fig. 4, compute a fixed-information per-digit cost C(R) from inverter transistor counts normalized by log2 R: R=2 uses 2 transistors; R=3 uses 3, 6, or 8; R=4 uses 10. Fit whether C(R) is better described by R(R-1)/ln R, (R-1)/ln R, or R/ln R. If the R(R-1) form is not the best fit, Eq. (2) is not an independent disproof, and the original e-optimality result remains unfalsified under its stated assumptions.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The weakest load-bearing step is Section II.C. Equation (2) replaces Hurst's C = k R log N / log R with C = k R (R-1) log N / log R, introduced by the phrase 'Let's assume that the hardware complexity is proportional to R-1'. The R-1 factor is never derived from a circuit model; it is a hypothesis chosen so the optimum moves from e to 2. The 4-valued inverter example (Fig. 4) shows threshold count matters for one inverter family, but it does not establish that total system cost scales as R(R-1) across gates, adders, multipliers, and memories. Consequently the abstract's claim that Hurst's demonstration 'is disproved' is not supported by the theoretical section: the paper changes the model's assumption rather than refuting the original derivation. The empirical transistor-count portion is more robust---even conservative binary adders have lower counts---but it supports the narrower claim that the selected ternary arithmetic circuits are not competitive, not a mathematical disproof of the e-radix optimum. Since the overclaim is central to the stated contribution, Eq. (2) should be presented as one plausible cost model, with the disproof claim softened accordingly.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper challenges the widely cited argument that radix e ≈ 2.718 (rounded to 3) is the optimal radix for computation. After reviewing Hurst's cost model C = k R log N / log R, the paper proposes a revised model C = k R (R-1) log N / log R, which makes R = 2 optimal. The bulk of the paper is an empirical comparison of ternary and binary circuits in MOSFET-like CNTFET technology, using published ternary designs, with transistor counts for inverters, NAND gates, half/full adders, multipliers, D flip-flops, and SRAM cells. The paper finds that only the 3-transistor inverter approach of [8] achieves a transistor-count ratio below the information ratio log(3)/log(2) ≈ 1.58, and only for basic gates and inverter-based circuits; arithmetic circuits are claimed to be always outperformed by binary counterparts.","tokens_in":9774,"tokens_out":6049,"duration_ms":56685,"significance":"The empirical transistor-count comparison is a useful and clearly presented data point that quantifies the circuit-level overhead of several published ternary designs relative to binary ones. The observation that the 1.58 information-ratio bound is rarely met is instructive and may be of interest to the multiple-valued logic community. However, the paper's central theoretical claim—that the e-radix demonstration is 'disproved'—rests on an unverified cost-model assumption rather than on a rigorous refutation. The strength of the stated conclusions therefore exceeds what the evidence supports. If the overclaims are softened and the cost model is presented as one plausible hypothesis, the paper could still be a meaningful contribution, but in its current form the central claim is not established.","major_comments":[{"comment":"The replacement of Hurst's cost model C = k R log N / log R by C = k R (R-1) log N / log R is introduced by the assertion that hardware complexity is proportional to R-1, the number of threshold levels. No derivation from a concrete circuit model is provided, and the factor R-1 is not shown to hold across different gate types, arithmetic structures, or memories. Because the optimum of Eq. (2) is R=2 by construction, the 'disproof' of the e-radix result is not a refutation of Hurst's derivation but a demonstration that a different cost model yields a different optimum. The abstract and conclusion state that the demonstration 'is disproved'; this overstates what the paper actually shows. The contribution should be reframed as a sensitivity analysis of the cost model, or the disproof claim should be removed.","section":"Section II.C, Eq. (2)"},{"comment":"The comparison of ternary and binary arithmetic circuits uses a single design style for the ternary adders (the decoder/encoder approach from references [6] and [7]) and a single 1-trit multiplier design. The paper does not survey the broader space of published ternary adder and multiplier implementations, which may include pass-transistor or direct gate-level designs with different transistor counts. Consequently, the strong conclusion in the Abstract and Section V that 'for arithmetic circuits such as adders and multipliers, the ternary circuits are always outperformed by the binary ones' is not justified by the evidence presented. The claim should be restricted to the designs actually considered, or the paper should demonstrate that the selected designs are representative of the best available ternary implementations.","section":"Section IV.B and IV.C"}],"minor_comments":[{"comment":"The phrase 'e=2.718 rounded to 3' is imprecise: Hurst's demonstration concerns the continuous optimum at e, and the rounding to an integer radix is a separate step. Clarify the relationship between the continuous result and the integer radix.","section":"Abstract"},{"comment":"The row 'Ratio 3/2 1 1/3.67 1/7.3' is difficult to parse; the ratios should be written explicitly as 3.67 and 7.3, or as fractions 66/18 and 66/9, to avoid confusion.","section":"Table VII"},{"comment":"The URL 'http://dx.doi.org/10;1016/j.mejo.2015.09;018' uses semicolons instead of periods; this appears to be a typographical error.","section":"Reference [5]"},{"comment":"The phrase 'Let's assume' should be replaced by a clear statement that Eq. (2) is presented as a hypothesis or alternative cost model, so that the reader immediately understands the conditional nature of the subsequent argument.","section":"Section II.C"}],"recommendation":"major_revision","confidential_remarks":"The paper has a substantial empirical section that is worth preserving, but the theoretical 'disproof' is not defensible as stated. The authors should be encouraged to revise the paper to present Eq. (2) as one possible cost model, to soften the dismissive language about Hurst's argument, and to restrict the circuit-comparison conclusions to the designs examined. With these changes the paper could make a credible, if narrower, contribution."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Let me give you my read on Etiemble's ternary paper. The title and abstract promise a disproof of the e-radix optimality argument, but that disproof doesn't hold. The real value is in the circuit comparison.\n\nWhat's new: the paper assembles transistor counts from published CNTFET designs for ternary inverters, NANDs, adders, multipliers, flip-flops, and SRAM cells, and compares them against binary counterparts using an information ratio of log(3)/log(2) ≈ 1.58. These tables are concrete and internally consistent. For arithmetic blocks, the ternary designs are consistently 3x to 15x more expensive, which is a useful data point for anyone working on multiple-valued logic. The author is also honest about the caveats: transistor count isn't area or power, and the binary counterparts include some non-restoring pass-transistor logic.\n\nThe soft spot is the theoretical section. Equation (2) replaces Hurst's C = kR log N / log R with C = kR(R-1) log N/log R by assuming hardware complexity scales with the number of threshold levels. That may be plausible for some circuit families, but it is an assumption, not a derivation. Under Hurst's original model, R=e is still the optimum. So calling the e-radix result 'disproved' is an overstatement. The author should reframe this as: under a more realistic cost model that accounts for threshold levels, the optimum shifts to binary. That would be a legitimate contribution, but it's a different claim.\n\nThere's also a selection issue. The ternary circuits come from a handful of papers, mostly using standard decoder-encoder implementations, while the binary set includes optimized 3T XOR and 8T full adders. The author does present conservative binary versions, and the conclusion doesn't depend on the fancy ones, but the 'always outperformed' language is broader than the evidence.\n\nWho gets value: researchers in MVL and circuit design who want a quick transistor-count reality check. The theoretical discussion is a useful cautionary tale about cost models, though not a knockout punch.\n\nWould I accept it for review? Yes, with the expectation of revision. The empirical comparison deserves an outlet, and a good referee can push the author to soften the claims and scope the conclusions. I'd read the revised version again.","headline":"Useful transistor-count tables for ternary vs binary CNTFET circuits, saddled with an overclaimed theoretical refutation that rests on an unproven cost model.","tokens_in":10326,"tokens_out":2480,"would_cite":false,"duration_ms":25155,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The claim that radix 3 beats radix 2 fails when per-digit hardware cost is counted.","keywords":["ternary logic","optimal radix","CNTFET","transistor count","multiple-valued circuits","binary arithmetic","radix economy","e-radix argument"],"falsifier":"A CNTFET ternary full adder with a transistor count at or below 1.58 times a binary full adder (roughly 28 transistors if the binary baseline is 18), built without an additional power supply and without a static dc path, would disprove the claim that ternary arithmetic circuits are always outperformed by binary ones.","tokens_in":9323,"feed_emoji":"⚙️","tokens_out":6187,"duration_ms":55459,"temperature":0.7,"pith_summary":"This paper attacks the long-standing argument that the number e = 2.718, rounded to 3, is the most economical radix for computation. It first shows that the classical cost model C = k R log N / log R omits how much harder each digit is to build at larger radices; adding the number of threshold levels R - 1 as a cost factor makes R = 2 the optimum. It then compares ternary and binary circuits in the same MOSFET-like carbon-nanotube FET (CNTFET) technology, using transistor count as the yardstick and log(3)/log(2) = 1.58 as the information-advantage ratio. Across inverters, NAND gates, adders, multipliers, flip-flops, and SRAM cells, the ternary transistor count is almost always more than 1.58 times the binary count; the only exception is a basic-gate style that needs an extra power supply and suffers a transistor conflict. The paper concludes that ternary arithmetic circuits are always outperformed by binary ones, so the e-radix argument should be abandoned.","feed_headline":"Radix 3 loses to binary once hardware cost is counted","feed_subtitle":"Adding threshold levels to the cost model and counting transistors overturns the e = 2.718 optimal-radix argument.","key_machinery":"The load-bearing object is the refined cost equation C = k R(R - 1) log N / log R, where R is the radix, N the range to be represented, and R - 1 the number of threshold levels per digit. In the classical equation without the R - 1 factor, the minimum sits near e = 2.718; with the threshold factor, the curve rises with R and the minimum is at R = 2. The circuit comparisons then use a second quantitative tool: the information ratio log(3)/log(2) = 1.58, the maximum factor by which a ternary circuit's transistor count may exceed a binary circuit's and still be competitive. Every ternary design is checked against that ratio, and the decoder/encoder structure needed to implement arbitrary ternary truth tables is what pushes arithmetic circuits far over it.","core_discovery":"The paper's central claim is that the traditional proof of radix-3 optimality is invalid because it assumes the hardware cost of a digit is independent of how many voltage levels the digit must distinguish. Replacing the digit capacity R by R(R - 1), where R - 1 counts threshold levels, turns the cost curve from one with a minimum near e into one that rises monotonically, making radix 2 optimal. On the circuit side, the paper counts transistors for ternary designs taken from the CNTFET literature and compares them with binary implementations in the same technology. For half adders the ternary version needs 66 transistors versus 9 to 18 for binary; for full adders 124 versus 8 to 36; for a 5x5 ternary multiplier 6190 versus 2382 for an 8x8 binary one. Since the information ratio is only 1.58, any ratio above that means the ternary circuit uses more wires, area, and power, and the paper judges such circuits not competitive. The single three-transistor ternary inverter has a ratio of 1.5, but it achieves that only with an additional power supply and an always-on transistor creating a dc path, so it does not rescue the general claim.","pith_inferences":["The same threshold-level argument would apply to radix 4 and higher, so the classical equality C(2) = C(4) should not be read as saying binary and quaternary circuits have equal hardware cost.","If a ternary arithmetic circuit style could be built with a transistor ratio below 1.58 without an extra power supply or dc path, the paper's 'always outperformed' conclusion would need qualification; the search for such a style is a natural test of how general the result is.","Because the overhead comes from decoder/encoder logic and threshold levels rather than from carbon nanotubes specifically, the same conclusion is likely to hold in any technology where binary and ternary gates are built from the same transistor primitives."],"forward_implications":["If the paper's cost model is right, there is no information-theoretic reason to prefer radix 3, and the classical e-radix argument should stop being cited as a motivation for ternary logic.","For arithmetic building blocks in a MOSFET-like CNTFET technology, ternary circuits cannot compensate their transistor overhead by carrying more information per wire.","The only ternary designs that meet the 1.58 bound are inverters, NAND gates, flip-flops, and SRAM cells built from the three-transistor inverter style, and those carry two serious drawbacks: an extra power supply and a static dc path.","Ternary remains useful for special functions with three natural states, such as content-addressable memory storing 0, 1, and don't-care, but not as a general-purpose replacement for binary computation."],"supporting_citations":[{"why":"Supplies the classical cost model C = k R log N / log R whose minimum at R = e is the target of the paper's refutation.","marker":"[1]"},{"why":"Provides one ternary inverter and NAND design with 8 transistors whose transistor count is compared against binary.","marker":"[5]"},{"why":"Provides the 6-transistor ternary inverter and NAND designs and the ternary adder building approach used in the comparison.","marker":"[6]"},{"why":"Provides the ternary decoder/encoder circuits and the full-adder equations whose transistor counts are the basis for the 124-transistor ternary full adder.","marker":"[7]"},{"why":"Provides the three-transistor ternary inverter and SRAM cell, the only designs with transistor ratio below the information ratio.","marker":"[8]"},{"why":"Gives the general decoder/encoder scheme for m-valued circuits that explains the overhead in ternary arithmetic.","marker":"[9]"},{"why":"Supplies the CNTFET three-transistor XOR and eight-transistor full adder used as low-count binary baselines.","marker":"[10]"}],"fun_headline_variants":["Ternary's transistor count busts the e-optimal radix myth","Radix 3 not optimal when you count the hardware","Why e=2.718 as best radix fails on real circuits","Counting transistors kills the radix-3 advantage","Ternary circuits lose to binary in hardware count"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The argument collapses if hardware cost per digit does not actually grow with the number of threshold levels; the R(R - 1) term is assumed, not derived.","fun_headline_variants_meta":{"raw":{"variants":["Ternary's transistor count busts the e-optimal radix myth","Radix 3 not optimal when you count the hardware","Why e=2.718 as best radix fails on real circuits","Counting transistors kills the radix-3 advantage","Ternary circuits lose to binary in hardware count"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000413,"raw_usage":{"total_tokens":2121,"prompt_tokens":913,"completion_tokens":1208,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":529,"completion_tokens_details":{"reasoning_tokens":1127}},"tokens_in":529,"tokens_out":1208,"duration_ms":9887,"temperature":1.0,"reasoning_tokens":1127,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T12:32:21.245581+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"A CNTFET ternary full adder with a transistor count at or below 1.58 times a binary full adder (roughly 28 transistors if the binary baseline is 18), built without an additional power supply and without a static dc path, would disprove the claim that ternary arithmetic circuits are always outperformed by binary ones.","supporting_citations":[{"cited_title":"Robust and energy-efficient carbon nanotube FET- based MVL gates: A novel design approach","cited_arxiv_id":null,"evidence_quote":"Provides one ternary inverter and NAND design with 8 transistors whose transistor count is compared against binary."},{"cited_title":"CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuit","cited_arxiv_id":null,"evidence_quote":"Provides the 6-transistor ternary inverter and NAND designs and the ternary adder building approach used in the comparison."},{"cited_title":"High Performance Ternary Adder using CNTFET","cited_arxiv_id":null,"evidence_quote":"Provides the ternary decoder/encoder circuits and the full-adder equations whose transistor counts are the basis for the 124-transistor ternary full adder."},{"cited_title":"Design of a ternary static memory cell using carbon nanotube based transistors","cited_arxiv_id":null,"evidence_quote":"Provides the three-transistor ternary inverter and SRAM cell, the only designs with transistor ratio below the information ratio."},{"cited_title":"Comparison of binary and multivalued inte- grated circuits according to VLSI criteria","cited_arxiv_id":null,"evidence_quote":"Gives the general decoder/encoder scheme for m-valued circuits that explains the overhead in ternary arithmetic."},{"cited_title":"Comparative Analysis of CNTFET and CMOS Logic Based Arithmetic Logic Unit","cited_arxiv_id":null,"evidence_quote":"Supplies the CNTFET three-transistor XOR and eight-transistor full adder used as low-count binary baselines."}],"review_version":1}