{"id":"ea9b187d-681b-4814-b410-73c3794ab407","arxiv_id":"1908.07299","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"Ternary adders and multipliers use fewer digits and wires, but their 1-trit cells are so much larger that binary designs remain more efficient.","lead":"This paper compares binary and ternary adder and multiplier circuits made in the same CNTFET technology by counting transistors in their basic building blocks. It concludes that ternary circuits need too many transistors per digit to beat binary circuits for the same computing capability.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The multiplier conclusion depends on a single 38T 1-trit multiplier cell; the paper itself cites a 27T ternary FA yet uses 124T in totals, so 'cannot compete' for multipliers is not robust to plausible better ternary cell counts.","rationale":"The paper's structural comparison (fewer 1-trit adders/multipliers and cells) is transparent and correct. The breakeven thresholds IR and IR^2 are the right framework. The weakness is in the complexity data: the 1-trit multiplier count of 38T is a single point, and the paper's own cited 27T ternary FA is not used in the multiplier totals. I checked whether the conclusion survives under the paper's own alternative data: with a 27T ternary FA and an 11T binary FA, the 16x16-vs-10x10 multiplier ratio is about 2.05 in ternary disfavor, so the negative conclusion still holds under a like-for-like threshold-logic comparison. However, the margin for the multiplier cell breakeven is small (roughly 32-36T versus the reported 38T), and no evidence rules out a lower-count cell. For adders, the conclusion is more robust because even the cited 27T ternary FA is 3.375x an 8T binary FA, well above IR = 1.585. Thus the central claim is conditionally supported but not robustly established for multipliers. The reader's verdict of CONDITIONAL with medium risk is appropriate; my concern is more specific than the reader's transistor-count-proxy point, so agreement is partial. No change to the verdict is needed.","tokens_in":8123,"tokens_out":11930,"duration_ms":122775,"concrete_test":"Search the CNTFET ternary arithmetic literature for the lowest reported transistor count of a 1-trit multiplier that produces one ternary product and one binary carry; if none exists, re-synthesize the Section VI.A design using the same capacitive-threshold technique as references [5] and [6]. Then recompute the 16x16-bit vs 10x10-trit multiplier totals using that cell count together with both the 124T and the 27T ternary FA counts and the corresponding binary FA counts (28T and 11T). If the 1-trit multiplier can be implemented in ≤32T and the 27T FA is used, the ternary multiplier becomes competitive or better, falsifying the abstract's blanket 'cannot compete' for multipliers; if only >38T designs are found, the concern fails.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that ternary multipliers cannot compete is load-bearing on the transistor counts of the ternary building blocks. The breakeven for the 1-trit multiplier cell is about 6T x IR^2 ≈ 15.1T, and with a 27T ternary FA the full-multiplier breakeven for the 16x16-vs-10x10 case is roughly 32-36T for the cell. Section VI.A reports a single 38T design (4 decoder + 12 Sum2 + 12 Sum1 + 6 product encoder + 4 cout encoder), with no survey or optimization argument showing this is near-minimal. The paper's own Section V.A cites a 27T threshold-logic ternary FA [6], yet the overall multiplier complexity in Section VI uses the 124T FA from [4] for the reduction tree. Substituting the cited 27T FA with a like-for-like 11T binary FA keeps the ternary multiplier worse (ratio ≈2.05 for 16x16 vs 10x10), but the margin shrinks dramatically, and the conclusion is not established if a 1-trit multiplier with ≤32T exists. The paper provides no evidence that 38T is close to optimal, so the strong negative claim for multipliers rests on an unverified representativeness assumption. The reader's transistor-count-proxy concern is related but secondary; even granting the proxy, the specific cell counts need to be representative.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This manuscript compares binary and ternary adders and multipliers at equal information throughput, using M = N/IR with IR = log(3)/log(2) ≈ 1.585. It first derives cell-count comparisons: a ternary ripple-carry, carry-lookahead, or carry-skip adder uses fewer 1-trit full adders than a binary adder uses 1-bit full adders, but the 1-trit adder must cost less than IR times the 1-bit adder to break even; for multipliers, the 1-trit multiplier must cost less than IR² times the 1-bit AND, and the carry generated by each 1-trit multiplier doubles the number of partial-product lines. The paper then uses published CNTFET designs to count transistors: a 124T ternary full adder versus 8–28T binary full adders, a 27T threshold-logic ternary FA versus an 11T binary FA, and a 38T 1-trit multiplier versus a 6T AND. From these counts it concludes that ternary adders and multipliers cannot compete with binary ones, since observed ratios are 4.4–15.5 for adders and about 6.3 for the multiplier cell, and the CLA and carry-skip carry circuitry is also more costly for ternary.","tokens_in":8398,"tokens_out":8744,"duration_ms":89067,"significance":"The paper provides a clean and useful quantitative framework: the breakeven ratios IR and IR² are correctly derived from the information ratio, and the adder comparison is robust because even the best cited ternary FA is more than IR times the best cited binary FA. If transistor count is accepted as a proxy for hardware complexity, the negative result for ternary adders is convincing. The multiplier comparison identifies the right structural issue (carry generation doubling the number of partial-product lines), and the overall conclusion is plausible, but it is less robust than the adder conclusion because it depends on a single 1-trit multiplier cell and because the full multiplier totals are never tabulated in transistor counts. The paper is useful as a reference-point comparison for the MVL/ternary logic community, provided the missing sensitivity analysis is supplied.","major_comments":[{"comment":"The 1-trit multiplier is represented by a single 38T design (Equations 1–3), and no evidence is given that this count is close to minimal. The breakeven value against a 6T binary AND is IR² × 6 ≈ 15T, so the 38T cell supports the qualitative conclusion, but the margin is not overwhelming; the adder section itself shows that a different design style (threshold logic, Section V.A) reduces a 124T ternary FA to 27T. A threshold-logic or otherwise optimized 1-trit multiplier in the 20–30T range would shrink the overall multiplier margin substantially. Please add a survey of existing 1-trit multiplier designs, a lower-bound argument, or a sensitivity analysis of the full multiplier ratio as a function of this cell count. Without this, the strong claim that ternary multipliers 'cannot compete' is not fully established.","section":"VI.A"},{"comment":"The paper never provides a complete transistor-count table for whole multipliers analogous to Table VI for adders. Section VI.B compares only the reduction trees in equivalent-FA terms and states that the difference 'is not able to compensate' the FA advantage, but it does not add the partial-product generator counts to the comparison. In addition, Table III gives 12 ternary HAs for the 5×5 case while Section VI.B says 14. Please give explicit total transistor counts for the N = 8, 12, and 16 comparisons, using consistent cell counts, and do so for both cited ternary FA designs (124T and 27T) to show the range of the final ratio. This is necessary to support the multiplier conclusion quantitatively.","section":"VI.B / Table III"},{"comment":"The abstract and Section VII make an unqualified claim that the ternary operators have more connections, more chip area, more propagation delays, and more power dissipation because they have more transistors. Section IV.B explicitly adopts transistor count as the only complexity criterion; the step from transistor count to delay and power is an assumption, not a demonstrated relation. For example, a logically shallower but transistor-heavier circuit can have a shorter critical path, and interconnect counts depend on cell placement and routing, not only on transistor count. Please either provide supporting data for the delay/power/area inference or restrict the conclusion to 'more transistors and, correspondingly, higher wiring and area under the same cell style.'","section":"IV.B / VII"}],"minor_comments":[{"comment":"The text 'M = N/1.858' should read 'M = N/1.585'; the value 1.858 is inconsistent with the information ratio defined in the paper.","section":"III.A.2"},{"comment":"The sentence 'For CPAs, CSAs and CSAs, the M-trit adders cannot compete' contains a repeated 'CSAs'; it should read 'For CPAs, CLAs and CSAs'.","section":"V.B.4"},{"comment":"In the sentence 'a M-trit multiplier will be more efficient than a N-bit multiplier', the word 'multiplier' should be 'adder', since the section is about ripple-carry adders.","section":"V.B.1"},{"comment":"The entries in Table VIII sum to 320, not 310 as listed; the 5-trit CLA carry-count row should be recomputed.","section":"Table VIII"},{"comment":"The number of ternary half adders in the reduction tree is given as 12 in Section III.A.2 and as 14 in Section VI.B; these counts should be reconciled.","section":"VI.B"}],"recommendation":"major_revision","confidential_remarks":"The manuscript is a straightforward comparison with a clear negative result. The adder half is solid and the breakeven analysis is well framed; the multiplier half needs a sensitivity analysis or a survey of 1-trit multiplier designs before the broad 'cannot compete' statement can be accepted. There are no concerns about originality or attribution beyond the author's prior work being appropriately cited."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: useful negative result for ternary arithmetic, but the multiplier leg is shakier than the adder leg, and the 'cannot compete' slogan is broader than the transistor-count evidence.\n\nThe paper's core move is to compare N-bit binary adders/multipliers with M-trit ternary ones, M=N/log2(3), and compute the breakeven complexity ratio: a 1-trit cell must cost no more than IR=1.585 times a 1-bit cell for the ternary version to win, and no more than IR^2 for multipliers. That framing is clear and correct. The application to CNTFET cells from the recent literature is new, and the arithmetic is transparent; I could reproduce the tables easily. Credit is due: this is an honest, readable reference point for a literature that usually ignores binary comparison.\n\nThe adder conclusion holds up well. The best cited ternary FA is the 27T threshold-logic one, vs an 11T binary FA; ratio 2.45 > 1.585. Even ignoring the 124T adder used as the main reference, ternary is worse. The carry-lookahead and carry-skip comparisons reinforce this. So the negative result for adders is solid.\n\nThe multiplier conclusion is softer. It rests almost entirely on a single 38T 1-trit multiplier cell from one design. The paper cites a 27T ternary FA elsewhere but uses the 124T FA in the multiplier reduction-tree totals; that inflates the ternary multiplier cost. If you substitute the 27T FA, the 16x16-bit vs 10x10-trit ratio drops to about 2.0—still above breakeven, but not by the comfortable margin the paper implies. More importantly, there is no survey or lower-bound argument showing 38T is near-minimal. If a 1-trit multiplier cell at or below IR^2 times a 6T AND gate (~15T) or even a 32T cell were published, the multiplier conclusion would fall apart. The paper needs a sensitivity analysis or a representative set of ternary multiplier cells before making a strong claim.\n\nThe transistor count proxy is a known simplification; the paper states it but then draws conclusions about area, interconnect, power, and delay. The inference is plausible but unproven, and 'cannot compete' is too global.\n\nWho should read it: ternary logic researchers and anyone deciding whether to invest in ternary arithmetic. It deserves a serious referee and likely publication after revision as a short note, provided the multiplier claims are scaled back and the sensitivity of the conclusion to the 38T cell is admitted. I'd cite it for the breakeven argument and the adder comparison.","headline":"Useful negative result for ternary arithmetic, but the multiplier conclusion rests on a single transistor count and the 'cannot compete' claim overshoots the evidence.","tokens_in":8924,"tokens_out":2843,"would_cite":true,"duration_ms":27052,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Ternary arithmetic loses to binary when basic cells are counted","keywords":["ternary adders","ternary multipliers","binary adders","binary multipliers","CNTFET","transistor count","information ratio","multivalued logic"],"falsifier":"Build or simulate a 5-trit and an 8-bit adder in the same CNTFET technology with equal supply voltage and design rules, and measure delay, power, and area; if the 5-trit adder wins on a combined metric, the claim fails. More directly, any design of a 1-trit full adder with 13 or fewer transistors for an 8-transistor binary full adder, or a 1-trit multiplier at 15 or fewer transistors against a 6-transistor binary gate, would cross the paper's own break-even thresholds and overturn the conclusion.","tokens_in":7913,"feed_emoji":"🔢","tokens_out":7004,"duration_ms":62887,"temperature":0.7,"pith_summary":"Ternary (three-valued) logic promises fewer wires and fewer arithmetic cells than binary, since one trit carries $\\log_2(3)\\approx 1.585$ bits. This paper tests that promise by comparing adders and multipliers of equal information capacity, implemented in the same carbon-nanotube field-effect transistor (CNTFET) technology and measured by transistor count. The author's central claim is that ternary loses: a 1-trit adder needs 4.4 to 15.5 times as many transistors as a 1-bit adder, while the break-even ratio is only $IR = \\log(3)/\\log(2)\\approx 1.585$, and a 1-trit multiplier is about 6.3 times heavier than a 1-bit multiplier against a break-even of $IR^2\\approx 2.51$. Because the count of basic cells is only slightly smaller in ternary (e.g., five 1-trit adders versus eight 1-bit adders), the inflated cell complexity dominates and the ternary operators cannot compete on area, interconnect, power, or delay. The paper matters because it provides a quantitative, technology-matched baseline for a literature full of isolated ternary circuit proposals.","feed_headline":"Ternary arithmetic loses to binary when basic cells are counted","feed_subtitle":"One-trit adders need 4.4 to 15.5 times the transistors of one-bit adders — far above the 1.585 break-even point.","key_machinery":"The load-bearing identity is the information ratio $IR = \\log(3)/\\log(2)\\approx 1.585$, which converts equal computing power between binary and ternary: $N$ bits correspond to $M = N/IR$ trits. This ratio turns the comparison into a single cost threshold: a ternary cell can win only if its transistor count is below $IR$ times the binary cell for adders, and below $IR^2$ for the elementary multiplier, because a ternary multiplier cell emits both a product and a carry and thereby doubles the number of partial-product rows. The paper applies the threshold to transistor counts of CNTFET cells — a 1-trit full adder at 124 transistors and a 1-trit multiplier at 38, against binary cells at 8–28 and 6 respectively — and to carry-lookahead and carry-skip overheads, showing the ternary cell costs exceed the thresholds.","core_discovery":"The central discovery is a pair of break-even thresholds, derived from the information ratio $IR = \\log(3)/\\log(2)\\approx 1.585$, that decide the contest before any layout is drawn. An $M$-trit adder needs only $M\\approx N/IR$ full-adder cells to do the work of an $N$-bit adder, so ternary is competitive only if one 1-trit full adder costs no more than $IR\\approx 1.585$ times one 1-bit full adder. Surveying CNTFET designs, the paper finds the 1-trit full adder at 124 transistors versus 8 to 28 for binary full adders, ratios of 4.4 to 15.5, so the threshold is missed by a wide margin. For multipliers, the 1-trit multiplier must stay below $IR^2\\approx 2.51$ times the 1-bit multiplier, but the counted 38-transistor 1-trit cell is 6.3 times a 6-transistor and gate, and the ternary reduction tree also spends more on full adders. The author concludes that despite fewer external wires and fewer elementary blocks, ternary adders and multipliers cannot compete with binary ones in the same technology.","pith_inferences":["The break-even ratios double as design targets: a ternary circuit with a 1-trit full adder at or below $1.585$ times a matched 1-bit full adder would reverse the adder conclusion, so the paper implicitly sets a falsifiable engineering goal (roughly 13 transistors if the binary cell is 8).","If a metric other than transistor count dominates — for example, off-chip pin count in interconnect-bound systems — the paper's negative conclusion does not automatically transfer, and ternary could still win in that narrower regime.","The same threshold logic suggests a scaling test for radix 4 or radix 5: as the radix grows, cell complexity typically rises quickly while $IR$ grows slowly, so the break-even condition becomes harder to satisfy, not easier.","A direct experimental check would be to fabricate an 8-bit binary and a 5-trit ternary adder in the same CNTFET process and compare measured delay-power-area products; the paper's transistor-count prediction implies ternary should be worse on all three."],"forward_implications":["For carry-propagate, carry-lookahead, and carry-skip adders alike, the verdict is the same: any 1-trit full adder costing more than $1.585$ times the 1-bit full adder makes the $M$-trit adder lose to the $N$-bit adder.","Ternary multipliers face a double penalty: the 1-trit multiplier must stay under $2.51$ times the 1-bit multiplier, and the 1-trit full adders used in the reduction tree must also stay near the adder threshold; the counted cells fail both.","The outward advantage of ternary — fewer input/output wires and fewer elementary blocks — is real but is outweighed by internal interconnect, area, power, and delay, all of which scale with transistor count.","The comparison method carries over to other multivalued radices: replace $IR$ by $\\log(r)/\\log(2)$ and test the same cell-count thresholds."],"supporting_citations":[{"why":"Supplies the earlier 1988 comparison that motivates redoing the binary-versus-multivalued comparison with modern technologies.","marker":"[1]"},{"why":"Provides the transistor counts for binary full adders, from 28T conventional CMOS down to 8T, that set the baseline the ternary adder must beat.","marker":"[3]"},{"why":"Supplies the CNTFET ternary half-adder design that the paper extends to a 124-transistor 1-trit full adder, the measured ternary cell complexity.","marker":"[4]"},{"why":"Supplies a binary CNTFET full-adder design with capacitive threshold logic, used for the 11-transistor binary reference in the secondary comparison.","marker":"[5]"},{"why":"Supplies the corresponding ternary CNTFET full-adder design with 27 transistors, giving the 2.45 ratio used to show ternary still misses the 1.585 threshold.","marker":"[6]"}],"fun_headline_variants":["Ternary logic fails break-even test vs binary","One-trit cell costs too much to beat binary","Ternary adders lose to binary on transistor cost","Break-even ratio proves ternary impractical","CNTFET ternary cells are 4.4x+ binary cost"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The whole comparison rests on the assumption that transistor count is a sufficient proxy for overall hardware cost — that more transistors always mean more area, power, delay, and interconnect, so the ternary circuits' larger counts decide the contest.","fun_headline_variants_meta":{"raw":{"variants":["Ternary logic fails break-even test vs binary","One-trit cell costs too much to beat binary","Ternary adders lose to binary on transistor cost","Break-even ratio proves ternary impractical","CNTFET ternary cells are 4.4x+ binary cost"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00029,"raw_usage":{"total_tokens":1708,"prompt_tokens":967,"completion_tokens":741,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":583,"completion_tokens_details":{"reasoning_tokens":668}},"tokens_in":583,"tokens_out":741,"duration_ms":7669,"temperature":1.0,"reasoning_tokens":668,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T12:20:22.558431+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Build or simulate a 5-trit and an 8-bit adder in the same CNTFET technology with equal supply voltage and design rules, and measure delay, power, and area; if the 5-trit adder wins on a combined metric, the claim fails. More directly, any design of a 1-trit full adder with 13 or fewer transistors for an 8-transistor binary full adder, or a 1-trit multiplier at 15 or fewer transistors against a 6-transistor binary gate, would cross the paper's own break-even thresholds and overturn the conclusion.","supporting_citations":[{"cited_title":"Etiemble, M","cited_arxiv_id":null,"evidence_quote":"Supplies the earlier 1988 comparison that motivates redoing the binary-versus-multivalued comparison with modern technologies."},{"cited_title":"Anitha, ``Comparative study on transistor based full adder designs``, World Scientific News, WSN 53(3) (2016) 404-416, EISSN 2392-2192","cited_arxiv_id":null,"evidence_quote":"Provides the transistor counts for binary full adders, from 28T conventional CMOS down to 8T, that set the baseline the ternary adder must beat."},{"cited_title":"Sahoo, G.Akhilesh, R","cited_arxiv_id":null,"evidence_quote":"Supplies the CNTFET ternary half-adder design that the paper extends to a 124-transistor 1-trit full adder, the measured ternary cell complexity."},{"cited_title":"Hurst, ``Multiple-Valued Logic - Its Status and Its Future``, IEEE Trans","cited_arxiv_id":null,"evidence_quote":"Supplies a binary CNTFET full-adder design with capacitive threshold logic, used for the 11-transistor binary reference in the secondary comparison."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the corresponding ternary CNTFET full-adder design with 27 transistors, giving the 2.45 ratio used to show ternary still misses the 1.585 threshold."}],"review_version":1}