{"id":"a2066110-6579-44a2-bd60-a8c8d37c7d80","arxiv_id":"1908.07412","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A 180nm CMOS homeostatic circuit achieves 25,000-second time constants and 1.2 attoampere leakage currents, enabling automatic gain control of synaptic inputs over biologically realistic time scales.","lead":"A tiny silicon circuit slowly adjusts the strength of all synapses feeding a neuron to keep its firing rate steady, using a leakage current of just over one attoampere. It brings hours-long homeostatic plasticity to standard CMOS neuromorphic chips without floating-gate or off-chip memory.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The headline 1.2 aA / 25k s claim rests on an unmeasured assumption that gate and other parasitic leakages stay below 0.1 aA; the published closed-loop data reach only ~9k s, and the 25k s value is reported from an undocumented 'further test'.","rationale":"The reader's weakest-assumption analysis identifies essentially the same load-bearing point I would raise: the 1.2 aA figure and the 25k s time constant depend on leakage parasitics being below about 0.1 aA, which is estimated rather than measured. The paper has genuine strengths: a fabricated chip, direct measurements, no fitted-parameter derivation, and a qualitatively convincing closed-loop response at shorter time scales (Fig. 4 and Fig. 5). Those results support the mechanism, but they do not yet secure the headline claim. The internal logic of the paper is consistent: if the LLC channel current really is 1.2 aA and all parallel leakages are negligible, the reported slope on a 1 pF capacitor does give 25k s, and the AGC loop should work at that scale. The weak point is external reliability, not internal consistency: the required leakage budget is asserted from a literature-based gate-oxide density, and the 25k s result is mentioned but not shown. A zero-drive drift measurement would settle whether the controlled current is the dominant contributor; without it, the strongest claim should remain conditional. No change to the reader's verdict is needed.","tokens_in":6300,"tokens_out":6019,"duration_ms":66290,"concrete_test":"One decisive check: on the same test chip, bias the LLC cell in a zero-drive configuration (VREF_L = VREF_M = VREF_H and the LLC p-FET gate set to cutoff so no intentional channel current flows), then record VTHR drift on CF for at least 25,000 s. If |dVTHR/dt| exceeds about 0.12 uV/s (i.e., more than 0.1 aA into 1 pF), parasitic leakage is already comparable to the claimed 1.2 aA controlled current, and the headline time constant is not reliably reproducible; repeating at two temperatures and on two chips would also bound variability.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section III estimates total gate leakage below 0.1 aA by combining device geometry with a leakage density taken from [14]; this is an assumption, not a measurement, and it does not account for other parallel leakage paths into CF, such as OTA2 input leakage, drain-body junction leakage if finite OTA2 gain leaves VDB slightly off zero, or capacitor and switch leakage. Section IV then infers the 1.2 aA controlled current from a single dV/dt = 1.2 uV/s slope on a 1 pF capacitor. If even a small fraction of that drift were parasitic leakage rather than the LLC p-FET channel current, the 'controllable leakage' claim and the derived 25k s time constant would degrade proportionally. The long-timescale claim is also not supported by waveform data: Fig. 5 shows restoration up to about 9k s, while the 25k s value is stated as 'verified with further tests' without showing the trace, trial count, or temperature conditions. For the central claim to hold, the measured CF drift must be dominated by the controlled LLC channel current, and the AGC loop must actually restore firing rate at the 25k s scale. Neither condition is presently demonstrated.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript proposes an automatic gain control (AGC) circuit for homeostatic synaptic scaling in neuromorphic systems. The circuit uses a Differential Pair Integrator (DPI) synapse whose gain Igain is controlled by a voltage VTHR. A feedback loop compares the synaptic current to a reference and, via a comparator, switches a low-leakage cell (LLC) that slowly charges or discharges a 1 pF capacitor to adjust VTHR. The LLC is based on a subthreshold p-FET with leakage reduction techniques. The circuit was fabricated in 180 nm CMOS and occupies 84 µm × 22 µm with 10.8 nW power consumption. Measurements show closed-loop restoration of firing rate after step changes in the DPI input current (Fig. 4) and tunable restoration time scales up to about 9k seconds (Fig. 5). The paper further claims time constants up to 25k seconds and a controllable leakage current of 1.2 aA (7.5 electrons/s), inferred from a 1.2 µV/s slope on the 1 pF capacitor.","tokens_in":6492,"tokens_out":5491,"duration_ms":46636,"significance":"The ability to implement homeostatic plasticity with extremely long time constants in standard CMOS, without floating gates or off-chip digital control, is a valuable result for neuromorphic engineering. The measured closed-loop homeostasis (Fig. 4) is a direct demonstration of the AGC concept, and the area and power numbers are attractive. The paper also benefits from using standard, well-characterized subthreshold circuits (DPI, OTA) and from providing a concrete measurement method for leakage current. However, the headline 25k s and 1.2 aA claims are not fully substantiated by the presented data, so the significance is conditional on the additional evidence requested below.","major_comments":[{"comment":"The paper states that 'the longest time scale we measured in this experiment is around 9k seconds' and that 'we verified, with further tests' a time scale of about 25k seconds, but no waveform, trial count, or temperature is shown for the 25k s case. Since the 25k s value is the headline claim of the abstract and Table I, the authors should show the closed-loop firing-rate restoration (or at least the VTHR/VSYN trace) at that timescale and report the number of repetitions and conditions. Without this, the 25k s value is anecdotal rather than a measured result.","section":"Section IV, after Fig. 5"},{"comment":"The estimate that total gate leakage is smaller than 0.1 aA is derived from a gate-oxide leakage density taken from [14] and the device geometries, but it is an assumption, not a measurement. It also does not account for other parallel leakage paths into the CF node, such as OTA2 input leakage, drain-bulk junction leakage if the finite OTA2 gain leaves VDB slightly off zero, or capacitor and switch leakage. The inference in Section IV that the measured 1.2 µV/s slope corresponds to a controlled LLC channel current of 1.2 aA is only valid if these parasitic leakages are negligible. I recommend an explicit control measurement, e.g., monitoring the CF drift with the LLC p-FET channel forced off, to bound the parasitic leakage.","section":"Section III, 'The ultra-low leakage cell'"},{"comment":"The measurements are reported without error bars, repeated trials, or temperature information; subthreshold leakage currents are exponentially sensitive to temperature and bias. To support the reproducibility of the reported time constants, the authors should specify the number of chips/devices measured, the ambient temperature, and the spread of the results.","section":"Section IV, Figs. 4 and 5"}],"minor_comments":[{"comment":"'refectory period' should be 'refractory period'.","section":"Section IV, first paragraph"},{"comment":"There are minor formatting issues ('with aW/L ratio', '10− 8A/m2') and the relationship between the 84 µm × 22 µm area, the DPI, and the LLC sizes should be clarified.","section":"Section III and Table I"},{"comment":"The term 'time constant' is used inconsistently: Fig. 4 reports ~60 s, Fig. 5 up to ~9k s, and Table I lists 25k s. Define how each time constant is extracted (e.g., exponential fit to the firing-rate envelope, or VTHR ramp duration) so that the values are comparable.","section":"Throughout"},{"comment":"The paper claims an improvement over the prior LLC in [8], but the discussion is brief; a short quantitative comparison (e.g., leakage current, time constant, area) would help the reader assess the novelty.","section":"Section I, discussion of prior work"},{"comment":"In the description of the AGC loop, the comparator output SW is described as digital, but no hysteresis or deadband is mentioned; given the bang-bang behavior visible in Fig. 4, a sentence on comparator hysteresis (or its absence) would be useful.","section":"Section II, AGC loop description"}],"recommendation":"major_revision","confidential_remarks":"The paper is a compact circuit demonstration with a strong concept, but the central quantitative claims (25k s, 1.2 aA) need direct experimental support. The issues are addressable with additional measurements, so I recommend major revision rather than rejection. I see no concern about circular reasoning or fitted parameters; the concerns are about missing evidence and unverified leakage assumptions. The paper is quite short for the claims made, and a revised version should include more experimental detail."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The thing to know: this is a hardware paper, not a simulation. The authors fabricated a 180 nm chip with an ultra-low leakage cell controlling DPI synapse gain, and they show closed-loop homeostatic restoration of firing rate after input steps at a ~60 s time constant. That part is convincing and is the real contribution.\n\nWhat is genuinely new is the leakage claim. They improve on their own prior ISCAS 2014 design and on O'Halloran and Sarpeshkar's 10 aA analog storage cell, reporting ~1.2 aA controllable leakage and 25k s time constants. If it holds, that is an order-of-magnitude step and useful for neuromorphic designers who want plasticity on behavioral timescales without floating gates or off-chip memory.\n\nThe paper does several things well. The circuit description is clear; the DPI transfer function is used as a design tool, not retrofitted to the data. The closed-loop restoration in Fig. 4 is a direct measurement with no fitted parameters. Area (84 µm × 22 µm) and power (10.8 nW) are reported. There is no circularity and no invented entities.\n\nWhere it gets soft: the headline 25k s value is not shown in any waveform. Fig. 5 shows restoration up to about 9k s, and the text says \"we verified, with further tests\" that 25k s is reachable, but gives no trace, no trial count, no temperature conditions. The 1.2 aA inference also depends on an assumption, not a measurement: the authors estimate total gate leakage into the storage node below 0.1 aA using a gate-oxide density from a 2000 paper, then subtract nothing for OTA2 input leakage, junction leakage, or switch/capacitor leakage. If even a fraction of the measured 1.2 µV/s drift on the 1 pF capacitor is parasitic rather than the intended LLC channel current, the controllable-leakage claim and the derived 25k s time constant degrade proportionally. There are also no error bars anywhere; the reported numbers look like single measurements.\n\nThese are not fatal objections to the architecture. The AGC topology is sound and the 60 s closed-loop result stands on its own. What is missing is evidence that the extreme long-time behavior is dominated by the intended current, and a proper closed-loop demonstration at the 25k s scale. A referee should ask for raw long-duration traces, multiple trials, temperature characterization, or at least an explicit uncertainty budget for the leakage estimate.\n\nThis paper is for neuromorphic circuit designers, and it deserves a serious referee. The engineering is credible and the claim is important if true. I would send it out, with the expectation of heavy revision requests on the leakage evidence. A desk reject would be wrong; accepting the headline numbers as-is would also be wrong.","headline":"A real CMOS homeostatic AGC circuit with an order-of-magnitude lower leakage claim, but the headline 25k-s / 1.2-aA numbers rest on an unmeasured parasitic-leakage assumption and a single unreported trace.","tokens_in":7081,"tokens_out":1901,"would_cite":true,"duration_ms":20356,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper presents a compact CMOS automatic-gain-control circuit that uses a 1.2-aA leakage current to achieve homeostatic synaptic scaling with time constants up to 25,000 seconds.","keywords":["homeostatic plasticity","synaptic scaling","automatic gain control","ultra-low leakage cell","DPI synapse","neuromorphic circuits","analog CMOS design","long time constants"],"falsifier":"Set the cell to its slowest configuration, the one giving roughly 1.2 uV/s on the 1 pF capacitor, and record $V_{\\mathrm{THR}}$ over an hour on multiple chips and at a range of temperatures; if the voltage ramp is not consistent with a 1.2-aA current, or if the firing-rate restoration time does not extend near 25,000 seconds, the central claim fails. Separately, measure $V_{DB}$ with the OTA2 feedback active to verify that it actually remains at zero.","tokens_in":1862,"feed_emoji":"🧠","tokens_out":1906,"duration_ms":87316,"temperature":0.7,"pith_summary":"The paper aims to show that homeostatic synaptic scaling can be built on-chip in ordinary 180 nm CMOS technology, without floating-gate devices or off-chip memory. It introduces an ultra-low-leakage cell whose controllable current can be as small as 1.2 atto-amperes, about 7.5 electrons per second, and an automatic gain control loop that gradually adjusts the gain of differential-pair integrator synapses. In measurements on a fabricated test chip, the loop restores a silicon neuron's firing rate to its reference value after a step change in input current, with time constants tunable from roughly 60 seconds up to about 25,000 seconds. If correct, this gives neuromorphic systems a compact, low-power way to compensate for chronic shifts in input statistics without interfering with faster synaptic learning.","feed_headline":"Tiny circuit restores neuron firing over 25,000 seconds","feed_subtitle":"A 180-nm CMOS gain-control loop scales synaptic strength with a 1.2-aA current, no floating gates.","key_machinery":"The argument is carried by two cooperating blocks. The first is the Differential-Pair Integrator (DPI) synapse, a log-domain integrator whose output current obeys $\\tau_s \\, dI_{\\mathrm{syn}}/dt + I_{\\mathrm{syn}} = I_w \\, I_{\\mathrm{gain}}/I_\\tau$; here $I_w$ is the summed synaptic weight current and $I_{\\mathrm{gain}}$ is an independent multiplicative scaling current set by a control voltage $V_{\\mathrm{THR}}$, so scaling $I_{\\mathrm{gain}}$ scales every afferent synapse together. The second is the ultra-low-leakage cell (LLC), a p-FET with $W/L = 0.5\\,\\mu\\mathrm{m}/1\\,\\mu\\mathrm{m}$ charging a 1 pF capacitor through a controllable current as small as 1.2 aA. Two subthreshold OTAs keep the drain-body voltage at zero and clamp the source voltage to one of two reference levels, while a comparator in the AGC loop chooses which reference is active; the result is a bang-bang loop that slowly raises or lowers $V_{\\mathrm{THR}}$ until the DPI output current matches the reference $I_{\\mathrm{REF}}$.","core_discovery":"The central claim is that a single well-biased p-FET, with its drain-body voltage forced to zero by an on-chip feedback amplifier and its gate leakage contained below about 0.1 aA through transistor sizing, can produce a controllable current of around 1.2 aA. Charging or discharging a 1 pF capacitor with this current yields voltage slopes around 1.2 uV/s, which through the DPI synapse's exponential gain control slowly moves the neuron's firing rate back toward its set point. The paper demonstrates the full loop: after the input current steps from 0.3 nA to 0.6 nA and back, the neuron's firing rate rises and then returns to the reference 100 Hz over a tunable time constant, and the same setup reaches time scales of about 25,000 seconds in further tests.","pith_inferences":["If the same leakage levels hold across process and temperature, the cell is a general-purpose analog integrator or memory: it could store a voltage for hours and drive other slow adaptive circuits, not just synaptic scaling.","The bang-bang controller could be replaced by a linear or delta-sigma analog loop to reduce ripple near steady state; the paper's measurements show an alternating locked region where the comparator keeps toggling near equilibrium.","A natural test is to combine this AGC with spike-timing-dependent plasticity in a small network: the multiplicative form of the scaling preserves weight ratios, so the two mechanisms should coexist; the paper motivates this but does not demonstrate it.","With a larger capacitor or further leakage reduction, time constants could extend beyond 25,000 seconds toward days, approaching the hours-to-days scales of biological homeostatic plasticity."],"forward_implications":["Neuromorphic arrays can implement homeostatic plasticity on-chip in standard CMOS, avoiding floating-gate transistors and external digital storage.","Because the loop scales all synapses afferent to a neuron through a shared $V_{\\mathrm{THR}}$, relative synaptic weights are preserved during homeostasis, so learning-induced weight ratios are not disrupted.","The time constant is tunable by setting $V_G$ and the $V_{\\mathrm{REF}}$ differences; the paper demonstrates restoration at roughly 60 seconds and verifies settings reaching about 25,000 seconds.","A full homeostatic loop occupies 84 um by 22 um and consumes about 10.8 nW at 1.8 V, making it practical to embed in large neural arrays.","The circuit restores the neuron's average firing rate to its reference value after bidirectional step changes in input drive, as shown by the 0.3 nA to 0.6 nA and back experiment."],"supporting_citations":[{"why":"Supplies the baseline previous ultra-low-leakage synaptic scaling circuit that this design improves on, establishing the need for a more controllable cell.","marker":"[8]"},{"why":"Provides the survey of CMOS leakage current mechanisms used to minimize off-state leakage in the low-leakage p-FET.","marker":"[9]"},{"why":"Contributes the earlier 10-aA-leakage analog storage cell whose leakage-minimization approach underlies the ultra-low-leakage estimates.","marker":"[10]"},{"why":"Defines the differential-pair integrator synapse transfer function that the automatic gain control loop scales via $I_{\\mathrm{gain}}$.","marker":"[11]"},{"why":"Provides the DPI circuit analysis in the neuromorphic VLSI context used to describe the synapse and its current scaling behavior.","marker":"[12]"},{"why":"Supplies the gate-oxide leakage current density used to estimate that gate leakage is below 0.1 aA for the 180 nm process.","marker":"[14]"},{"why":"Offers the subthreshold DC-gain enhancement technique used to build the high-gain, low-power OTAs that hold the leakage-cell voltages steady.","marker":"[15]"}],"fun_headline_variants":["Ultra-low leak circuit rebalances neuron firing for hours","1.2-aA leak powers 25,000-second synaptic homeostasis","Tiny CMOS gain control resets neurons over 7 hours","Attp-amp leak drives neuron firing-rate stability","Homeostatic loop scales synapse gain with 1.2-aA current"],"cache_read_input_tokens":9216,"weakest_assumption_plain":"The load-bearing premise is that every unintended leakage path in the low-leakage transistor is smaller than about 0.1 atto-ampere, so the intended 1.2-aA control current is not drowned out; if the feedback amplifier cannot hold the drain-body voltage at zero, or the gate leakage is larger than estimated, the 25,000-second time constants will not reproduce.","fun_headline_variants_meta":{"raw":{"variants":["Ultra-low leak circuit rebalances neuron firing for hours","1.2-aA leak powers 25,000-second synaptic homeostasis","Tiny CMOS gain control resets neurons over 7 hours","Attp-amp leak drives neuron firing-rate stability","Homeostatic loop scales synapse gain with 1.2-aA current"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000286,"raw_usage":{"total_tokens":1701,"prompt_tokens":982,"completion_tokens":719,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":598,"completion_tokens_details":{"reasoning_tokens":632}},"tokens_in":598,"tokens_out":719,"duration_ms":7857,"temperature":1.0,"reasoning_tokens":632,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T12:40:59.575902+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Set the cell to its slowest configuration, the one giving roughly 1.2 uV/s on the 1 pF capacitor, and record $V_{\\mathrm{THR}}$ over an hour on multiple chips and at a range of temperatures; if the voltage ramp is not consistent with a 1.2-aA current, or if the firing-rate restoration time does not extend near 25,000 seconds, the central claim fails. Separately, measure $V_{DB}$ with the OTA2 feedback active to verify that it actually remains at zero.","supporting_citations":[{"cited_title":"Ultra low leakage synaptic scaling circuits for implementing homeostatic plasticity in neuromorphic architectures,","cited_arxiv_id":null,"evidence_quote":"Supplies the baseline previous ultra-low-leakage synaptic scaling circuit that this design improves on, establishing the need for a more controllable cell."},{"cited_title":"Leak- age current mechanisms and leakage reduction techniques in deep- submicrometer CMOS circuits,","cited_arxiv_id":null,"evidence_quote":"Provides the survey of CMOS leakage current mechanisms used to minimize off-state leakage in the low-leakage p-FET."},{"cited_title":"A 10-nw 12-bit accurate analog storage cell with 10-aa leakage,","cited_arxiv_id":null,"evidence_quote":"Contributes the earlier 10-aA-leakage analog storage cell whose leakage-minimization approach underlies the ultra-low-leakage estimates."},{"cited_title":"Synaptic dynamics in analog VLSI,","cited_arxiv_id":null,"evidence_quote":"Defines the differential-pair integrator synapse transfer function that the automatic gain control loop scales via $I_{\\mathrm{gain}}$."},{"cited_title":"Neuromorphic electronic circuits for building autonomous cognitive systems,","cited_arxiv_id":null,"evidence_quote":"Provides the DPI circuit analysis in the neuromorphic VLSI context used to describe the synapse and its current scaling behavior."},{"cited_title":"Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime,","cited_arxiv_id":null,"evidence_quote":"Supplies the gate-oxide leakage current density used to estimate that gate leakage is below 0.1 aA for the 180 nm process."},{"cited_title":"Subthreshold DC-gain enhance- ment by exploiting small size effects of MOSFETs,","cited_arxiv_id":null,"evidence_quote":"Offers the subthreshold DC-gain enhancement technique used to build the high-gain, low-power OTAs that hold the leakage-cell voltages steady."}],"review_version":1}