{"id":"fa27e6ce-7869-4315-8907-f1c0ebd629b1","arxiv_id":"1908.07874","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"The authors present 28 nm FD-SOI analog synapse and neuron circuits with leakage cancellation that, in simulation, can operate at both slow biological timescales and fast ReLU-like rates.","lead":"This paper describes compact analog brain-like synapse and neuron circuits designed for a 28 nanometer chip manufacturing process, using tiny currents and leakage-cancellation tricks. It reports simulations suggesting these circuits could power low-energy spiking neural networks for real-time sensory processing and fast data tasks.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Leakage cancellation's reliability is unverified: the 4-to-1 static replica may not match 256 branches under mismatch or active-branch state changes, yet the pA-domain claim depends on it.","rationale":"The paper's central assertion is conditional on the leakage-canceling block making pA-scale currents usable in 28nm FD-SOI. The synapse and neuron topologies are largely extensions of designs previously validated in older processes (e.g., Ref. [7]), and the simulation curves in Figs. 4–6 are qualitatively plausible. The genuinely new, load-bearing element is the 4-to-1 replica leakage cancellation, and the paper provides no quantitative evidence that it works: no mismatch analysis, no corner analysis, no measured silicon, and no treatment of how individual branch activation affects the cancellation. I largely agree with the reader's weakest assumption about replica matching, which is the most direct threat to the central claim. In good faith, I do not recommend rejection because the design may still be salvageable: the leakage residual may be small at the 10 nA operating points shown, and a post-tapeout measurement or Monte Carlo study could validate it. But as written, the support for the central claim is incomplete, so the CONDITIONAL verdict should stand. I add the static-replica/active-branch over-subtraction point as a second, distinct failure mechanism that would remain even with perfect matching; it should be analyzed or explicitly disclosed as a limitation.","tokens_in":5491,"tokens_out":10747,"duration_ms":125765,"concrete_test":"Run a focused SPICE Monte Carlo and process-corner study of the Fig. 1 leakage-canceling block: program one synapse branch current to 1 pA, deliver a presynaptic pulse, and measure the compensated output Iwht with zero, one, and four branches active. If the residual offset—from replica mismatch or from static over-subtraction of active-branch dark current—exceeds 10% of the 1 pA signal, the pA-domain leakage-cancellation claim is unsupported. The same run will show whether the replica tracks branch activation or only the all-off leakage.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The load-bearing element is the leakage-canceling block in Fig. 1: a scaled 4-to-1 replica of 16 leak cells (4 branches each), biased with the same settings as the 64 synapse blocks, is used to estimate and subtract the total off-channel leakage of 256 branches. The central claim—sub-threshold computation with pA-nA currents and millisecond time constants—holds only if this replica current closely matches the real leakage. Three things are unstated or unverified. (1) No mismatch, temperature, or process-corner analysis is provided; in 28nm FD-SOI, subthreshold threshold-voltage mismatch causes exponential leakage variation, and the residual after subtracting a 64-branch replica from 256 branches could be comparable to the pA signals the paper targets. (2) The chip is said to be taped out, but all reported results (Figs. 4–6) are simulations only; no measured leakage or cancellation accuracy is given. (3) The replica appears static: it sums always-dark leak cells, so when a synapse branch is selected by a presynaptic spike it no longer contributes off-channel leakage, and the fixed subtraction over-cancels by one dark current per active branch, injecting an activity-dependent offset proportional to the number of active branches. Even if this offset is negligible at the 10 nA operating points shown, the paper neither quantifies it nor explains how the 'same leakage current' is maintained when branches are activated. These issues are not addressed in Section II or Section III, and they directly affect the strongest claim rather than secondary features.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents analog sub-threshold synapse and neuron circuits designed for a 28 nm FD-SOI process, intended for large-scale mixed-signal neuromorphic systems. The synapse circuit combines 64 programmable blocks (256 current branches) with a replica-based leakage-canceling block, a DPI low-pass filter for synaptic dynamics, an NMDA-like gating block, and a pA-nA current-mode integrator. The neuron circuit is a current-mode integrate-and-fire design with leak, AHP, Na+, and K+ compartments. The paper reports transistor-level simulation results for synaptic currents, membrane traces, and combined synapse-neuron transfer functions in both slow, biologically realistic regimes and fast ReLU-like regimes. The central claim is that leakage-canceling and mismatch-reducing techniques allow compact, energy-efficient pA-nA analog computation and millisecond-range time constants in an advanced scaled process.","tokens_in":5834,"tokens_out":3149,"duration_ms":34454,"significance":"If validated, this work would be a valuable demonstration that sub-threshold neuromorphic building blocks can be ported to 28 nm FD-SOI while retaining the long time constants and low currents needed for real-time sensory processing. The paper gives concrete area figures (3 µm^2 synapse block, 12.5 µm^2 DPI circuit, 20 µm^2 neuron), reports two clearly different operating regimes, and grounds the dynamics in the authors' prior DPI theory and measured 65 nm chip. The simulation traces are internally consistent with expected synaptic and neural dynamics. However, the load-bearing leakage-cancellation scheme rests on an unverified replica-matching assumption, and all reported results are simulations rather than measurements from the taped-out chip.","major_comments":[{"comment":"The leakage-cancellation scheme assumes that the summed dark current of a 4-to-1 replica of 16 leak cells (64 branches) matches the summed off-channel leakage of the 256 synapse branches. The paper provides no Monte Carlo, process-corner, or temperature analysis of this replica match. In 28 nm FD-SOI subthreshold operation, threshold-voltage mismatch causes exponential variation in leakage current, so the residual after subtraction may be comparable to the pA-scale signals the design targets. Please provide a mismatch/corner analysis of the replica relative to the synapse array and quantify the residual leakage after cancellation.","section":"Section II, Fig. 1"},{"comment":"The replica appears to be static: the leak cells are always dark, while a synapse branch that receives a presynaptic spike is active and no longer contributes its off-channel leakage. The fixed subtraction therefore over-cancels by approximately one dark-branch leakage current for each simultaneously active branch. The paper does not quantify this activity-dependent offset or explain how \"the same leakage current\" is maintained when branches are activated. This should be analyzed and, if necessary, corrected in the cancellation scheme.","section":"Section II, Fig. 1"},{"comment":"All quantitative results in Figs. 4-6 are transistor-level simulation traces. The abstract and introduction mention that a chip has been taped out, but no measured leakage-cancellation accuracy, no measured time constants, and no simulation-versus-silicon comparison are reported. Since the central claim concerns pA-nA operation and long time constants in this specific process, measured validation of the leakage cancellation and subthreshold dynamics is needed to fully support the claim as stated.","section":"Section III"},{"comment":"The text states that the Leakage Canceling block \"attempts to produce the same leakage current,\" which correctly flags that matching is not guaranteed by construction. The subsequent simulation results implicitly assume ideal matching. The paper should either derive the matching requirement from device statistics and bias tolerances, or explicitly state the conditions under which the cancellation remains valid.","section":"Section II, Fig. 1"}],"minor_comments":[{"comment":"Figure 3 is referenced in the text but never discussed; its caption \"Membrane current trace over time\" lacks context, axis units, and simulation conditions. Please add a proper description.","section":"Section III"},{"comment":"The notation \"dpi_tau!\" and \"dpi_thr!\" appears with inconsistent formatting in the text and figure captions; please make the \"!\" convention for programmable biases uniform throughout.","section":"Section II"},{"comment":"The DPI time-constant dependence is described only qualitatively as proportional to capacitance and inversely proportional to the bias current. An explicit equation, or a reference to the exact formula in [17], would make the design trade-off reproducible.","section":"Section II"},{"comment":"The phrase \"4-to-1 copy of 16 leak cells with 4 branches each\" is confusing; clarify that the replica contains 64 branches total, i.e., one quarter of the 256 synapse branches, and state how the 4-to-1 scaling is implemented in the current mirror.","section":"Section II, Fig. 1"}],"recommendation":"major_revision","confidential_remarks":"The main risk is that the leakage-cancellation scheme, which is the paper's key 28 nm-specific contribution, is validated only by ideal-matching simulations. If the authors add a proper mismatch/corner analysis and at least some measured leakage-cancellation or time-constant data from the taped-out chip, the paper could become acceptable. The novelty relative to the authors' earlier 65 nm work [7] is incremental but real, focusing on the leakage-canceling circuit and the FD-SOI design techniques."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The honest headline: this is a serious engineering paper that takes the DPI synapse and I&F neuron the authors have already validated in older nodes and adapts them to 28nm FD-SOI. The new content is the leakage-canceling block, the split-transistor biasing for pA currents, and the compact layout areas (3µm² per synapse, 12.5µm² for the DPI, 20µm² for the neuron). Transistor-level simulations show the expected dynamics, including the biological time constants and the ReLU-like high-frequency transfer function. As a circuit-design paper, it demonstrates that sub-threshold operation is conceivable in a modern scaled process, which is a legitimate and useful contribution for the neuromorphic community.\n\nThe soft spots are real but not disqualifying, especially for a conference-level venue. First, there are no measured silicon results. The chip is said to be taped out, but all figures are simulations. That is disclosed clearly, but it means the central claim—that the pA-nA computation actually works—is only plausible, not demonstrated. Second, the leakage-cancellation block, which is the load-bearing new element, gets no mismatch, temperature, or process-corner analysis. The stress-test point about activity dependence is worth taking seriously: the replica sums always-dark leak cells, so when a synapse branch is selected by a spike, the fixed subtraction over-cancels by the dark current of that branch. This injects an activity-dependent offset. At the 10nA operating points shown it may be negligible, but the paper neither quantifies it nor explains why it can be ignored. That is a gap, not a fatal flaw, and a careful referee could reasonably ask for the analysis or for measured data.\n\nThe citation pattern is fine. The paper leans on the authors' own prior fabricated work and the DPI theory paper, which is appropriate here because those results are the basis for the claim that the dynamics are 'expected from theory.' The plotting and schematic descriptions are clear enough to reproduce the design. The authors are not overclaiming—they call the results 'simulation results' and mention the tape-out, not measured validation.\n\nWho gets value: anyone designing mixed-signal neuromorphic systems in advanced nodes, and people interested in sub-threshold analog design under leakage. The paper deserves a serious referee; it should not be desk-rejected. For peer review, I would recommend conditional acceptance with a request for either measured leakage-cancellation data or a quantitative analysis of replica mismatch and activity-dependent offset. If neither is available, the authors should narrow the claims to simulated plausibility. As it stands, it is a competent, honest, and useful contribution that is one measurement away from being fully convincing.","headline":"Solid 28nm FD-SOI synapse/neuron design with real engineering, but the leakage-cancellation claim needs measured data or a tighter analysis.","tokens_in":6338,"tokens_out":2183,"would_cite":false,"duration_ms":26067,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Bio-physically realistic synapse and neuron dynamics can be implemented in 28 nm FD-SOI with ultra-low-power analog circuits that cancel channel leakage and operate on pico-ampere currents.","keywords":["subthreshold analog circuits","neuromorphic computing","28nm FD-SOI","leakage cancellation","spiking neural networks","mixed-signal VLSI","synapse circuits","integrate-and-fire neuron"],"falsifier":"On the taped-out chip, drive all 256 synapse branches with zero input spikes and measure the summed output current before and after leakage cancellation while sweeping temperature over the operating range; if the post-cancellation baseline drifts by more than the intended pA-nA signal, the replica-matching assumption fails. A second check is to compare the measured synapse-neuron transfer function for 100 Hz input pulses with the simulated response shown in the paper.","tokens_in":5296,"feed_emoji":"🧠","tokens_out":5271,"duration_ms":50992,"temperature":0.7,"pith_summary":"This paper argues that advanced scaled CMOS, specifically 28 nm FD-SOI, need not be abandoned for analog neuromorphic design. By adding a leakage-canceling block that mirrors the dark currents of 256 synapse branches and using split-transistor sub-threshold biasing, the authors show in simulation that pA-nA currents and time constants of tens to hundreds of milliseconds are achievable. This matters because it lets massively parallel spiking neural networks run at biologically realistic speeds for real-time sensory processing and at fast speeds for deep-network-style computation, without the von Neumann bottleneck. The circuits, including a 64-synapse block and a compact integrate-and-fire neuron, were designed for a chip that has been taped out.","feed_headline":"Chip circuit cancels leakage to run brain-like synapses at pA currents","feed_subtitle":"A leakage replica subtracts dark current from 256 synapse branches, keeping computation in the pico-ampere range.","key_machinery":"The load-bearing mechanism is a combination of leakage-canceling current subtraction and split-transistor sub-threshold biasing. The leakage-canceling block makes a scaled 4-to-1 copy of the 16 leak cells that mimic the 64 synapse blocks, sums their dark currents, and mirrors the result to subtract it from the total synapse current. The split-transistor pseudo-cascode technique, applied throughout the mirror transistors, keeps currents in the pico-ampere range with accurate mirroring despite advanced-node leakage and short-channel effects. Together these allow the Differential Pair Integrator and neuron compartments to realize long time constants with small MIMCAPs (1 pF and 1.5 pF) and compact active areas (3 $µm^{2}$ per synapse block, 20 $µm^{2}$ per neuron).","core_discovery":"The central discovery is that compact sub-threshold synapse and neuron circuits can be built in 28 nm FD-SOI by treating leakage not as an unavoidable obstacle but as a current that can be replicated and subtracted. A 4-to-1 replica of 16 leak cells, biased with the same settings as the 64 synapse blocks (256 branches), produces a copy of the total dark current; this copy is subtracted from the summed synaptic current, leaving only the weighted signal. Synaptic dynamics are implemented with a Differential Pair Integrator whose time constants are set by a 1 pF MIMCAP and pico-ampere bias currents generated with split-transistor pseudo-cascode mirrors. The neuron, built from leak, after-hyperpolarization, sodium, and potassium compartments with a current comparator, occupies 20 $µm^{2}$ and produces spiking behaviors tunable from biologically plausible firing to fast ReLU-like transfer functions.","pith_inferences":["If the leakage replica tracks mismatch and temperature the same way in silicon, the same cancellation scheme should port to other advanced nodes where off-state leakage is the bottleneck, not just 28 nm FD-SOI.","A natural next measurement is a chip-level comparison of the replica leak current against the 256-branch sum across temperature; that would quantify how much of the pA-nA operating range survives real silicon mismatch.","The ReLU-like fast configuration suggests the same analog front end could be used for high-throughput event-driven deep networks, where the limiting factor becomes the AER encoder bandwidth rather than the synapse time constant."],"forward_implications":["A 64-synapse block with leakage cancellation can sum currents from 256 branches while keeping the output proportional to the true weighted input.","The same circuits can be configured for slow, biologically realistic dynamics (tens to hundreds of milliseconds) for real-time sensory processing, and for fast ReLU-like transfer functions for spiking deep networks.","Because the neuron and synapse blocks are compact, multi-core architectures can avoid time-multiplexing and memory transfer, bypassing the von Neumann bottleneck.","The circuits are compatible with existing spike-based learning circuits and can be integrated into next-generation multi-neuron, multi-core neuromorphic processors."],"supporting_citations":[{"why":"Establishes the 28 nm FD-SOI process as the target and the prior scaling study this design extends.","marker":"[11]"},{"why":"Supplies the split-length-transistor technique used to create pico-ampere bias currents and accurate mirrors in the scaled process.","marker":"[18]"},{"why":"Supplies the 10-bit temperature-compensated bias generator that sets the programmable weights and dynamics.","marker":"[16]"},{"why":"Provides the Differential Pair Integrator circuit that implements the synaptic low-pass filtering and time-constant behavior.","marker":"[17]"},{"why":"Defines the spiking processor architecture and learning circuits whose building blocks are extended to the 28 nm process here.","marker":"[7]"},{"why":"Provides the sub-threshold analog VLSI design principles that the synapse and neuron circuits exploit.","marker":"[10]"},{"why":"Supplies the conceptual basis for using device physics to implement neural computation.","marker":"[1]"}],"fun_headline_variants":["Leakage-busting circuits keep neuromorphic chips at pA currents","28nm FD-SOI circuits cancel leakage for pA-scale spiking","Leakage replica subtraction keeps synapses at pA currents in 28nm","Canceling leakage enables dense sub-threshold neuromorphic circuits","28nm FD-SOI synapse and neuron circuits run at pA bias"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The whole pico-ampere operating range rests on the assumption that the leakage current of 16 leak cells is a faithful 4-to-1 miniature of the leakage from the 64 synapse blocks (256 branches), so that subtracting its copy removes the real dark current under actual bias, temperature, and mismatch conditions.","fun_headline_variants_meta":{"raw":{"variants":["Leakage-busting circuits keep neuromorphic chips at pA currents","28nm FD-SOI circuits cancel leakage for pA-scale spiking","Leakage replica subtraction keeps synapses at pA currents in 28nm","Canceling leakage enables dense sub-threshold neuromorphic circuits","28nm FD-SOI synapse and neuron circuits run at pA bias"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001156,"raw_usage":{"total_tokens":4752,"prompt_tokens":873,"completion_tokens":3879,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":489,"completion_tokens_details":{"reasoning_tokens":3784}},"tokens_in":489,"tokens_out":3879,"duration_ms":27510,"temperature":1.0,"reasoning_tokens":3784,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T12:41:15.390213+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"On the taped-out chip, drive all 256 synapse branches with zero input spikes and measure the summed output current before and after leakage cancellation while sweeping temperature over the operating range; if the post-cancellation baseline drifts by more than the intended pA-nA signal, the replica-matching assumption fails. A second check is to compare the measured synapse-neuron transfer function for 100 Hz input pulses with the simulated response shown in the paper.","supporting_citations":[{"cited_title":"Scaling mixed-signal neuromorphic processors to 28nm fd-soi technologies,","cited_arxiv_id":null,"evidence_quote":"Establishes the 28 nm FD-SOI process as the target and the prior scaling study this design extends."},{"cited_title":"Compensation of CMOS op-amps using split-length transistors,","cited_arxiv_id":null,"evidence_quote":"Supplies the split-length-transistor technique used to create pico-ampere bias currents and accurate mirrors in the scaled process."},{"cited_title":"Addressable current reference array with 170db dynamic range,","cited_arxiv_id":null,"evidence_quote":"Supplies the 10-bit temperature-compensated bias generator that sets the programmable weights and dynamics."},{"cited_title":"Synaptic dynamics in analog VLSI,","cited_arxiv_id":null,"evidence_quote":"Provides the Differential Pair Integrator circuit that implements the synaptic low-pass filtering and time-constant behavior."},{"cited_title":"A re-configurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses,","cited_arxiv_id":null,"evidence_quote":"Defines the spiking processor architecture and learning circuits whose building blocks are extended to the 28 nm process here."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the sub-threshold analog VLSI design principles that the synapse and neuron circuits exploit."},{"cited_title":"Neuromorphic electronic systems,","cited_arxiv_id":null,"evidence_quote":"Supplies the conceptual basis for using device physics to implement neural computation."}],"review_version":1}