{"id":"1e1023b2-6ddc-4cab-95cd-abb6d719b035","arxiv_id":"1908.09212","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"low","formal_verification":"none","parameter_count":1,"one_line_summary":"A low-cost digital FPGA servo locked the repetition rate and carrier-envelope offset of a commercial Er:fiber comb for 30 hours with phase noise comparable to manufacturer electronics.","lead":"Researchers used a low-cost FPGA board and open-source software to lock the two key frequencies of a commercial laser frequency comb. The digital system stayed locked for 30 hours with phase noise comparable to the manufacturer's own electronics, at a fraction of the cost.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 30-hour cycle-slip-free claim in Sec. 3.2 lacks a stated slip-detection criterion; the external counter data in Fig. 6 could miss brief 2π slips, so the headline lock duration is not independently established.","rationale":"The paper's core demonstration—a low-cost FPGA PLL performing comparably to manufacturer electronics—is supported by independent out-of-loop phase-noise measurements (Sec. 3.1, Fig. 5) and direct comparison to reported values. The only load-bearing weakness is the long-term 'no cycle slips' assertion. The reader identified this exact gap. Since the short-term performance is solid and the long-term claim can be repaired by documenting the slip criterion and raw counter analysis, the appropriate verdict remains CONDITIONAL rather than REJECT. The missing code URL/commit hash and error bars are secondary reproducibility issues that do not by themselves undermine the phase-noise result.","tokens_in":9906,"tokens_out":3993,"duration_ms":45619,"concrete_test":"Recover the raw 30 h counter logs and reanalyze them without any rejection: flag any 1 s (or stated gate-time) frequency reading that deviates from the local mean by more than 0.5/T_gate, and separately compare the integrated total cycle count over the full 30 h to the count expected from the setpoint frequency. If no flagged bins occur and the total count agrees to within one cycle, the slip-free claim is confirmed; if any flags appear or the count is off, the headline duration must be revised or re-qualified.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central long-term claim—'cycle-slip free locking ... over a 30 hour period' (Abstract and Sec. 3.2)—rests on Fig. 6, which plots frequency deviations of fceo, fbeat, and frep measured with Agilent 53132A counters. The paper does not state the counter gate time, dead time, or any threshold or rejection algorithm used to declare the data slip-free. A single cycle slip changes the counted beat-note frequency by 1/T_gate for the gate containing the slip; for a 1 s gate this is 1 Hz, far above the reported 0.1–0.2 mHz standard deviations. Such an event would be visible if every gate were recorded continuously. But if the counter has dead time, or if outlier points were removed before computing statistics, the displayed statistics cannot certify 'slip-free.' No raw time series, gate settings, or analysis script is supplied, so a reader cannot reproduce the slip determination. This is not a criticism of the phase-noise measurements, which are out-of-loop and reported consistently; the gap is specific to the 30-hour lock-duration headline.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports a digital servo system for stabilizing the repetition rate and carrier-envelope offset frequency of a commercial Er:fiber frequency comb. The system uses two low-cost Red Pitaya 125-14 FPGA boards running open-source digital phase-locked-loop software, with slow and fast actuators on the laser. The authors claim cycle-slip-free locking of optically derived beatnotes over a 30 hour period, integrated phase noise of 41 mrad and 114 mrad for f_beat and f_ceo over 100 Hz to 2 MHz, and a corresponding timing jitter of 70 attoseconds, which they argue is comparable to manufacturer-supplied lock electronics and sufficient for precision comb applications. The paper also demonstrates direct RF locking of the repetition rate by reconfiguring the same FPGA platform.","tokens_in":10065,"tokens_out":7412,"duration_ms":78874,"significance":"If the claims hold, this is a valuable demonstration: it shows that an inexpensive, commercially available FPGA board combined with open-source code can replace manufacturer-specific laser lock electronics without degrading short-term phase noise or long-term lock duration, lowering the cost and complexity barrier for frequency comb stabilization. The paper's strengths include out-of-loop phase-noise measurements made with a signal analyzer, long-term monitoring with external frequency counters, a benchmark against the laser manufacturer's specified phase noise, and a public code repository. The central short-term phase-noise result appears well supported. However, the headline long-term claim of 30-hour cycle-slip-free operation needs a more rigorous and clearly documented detection methodology, and there is an internal inconsistency in the assignment of the integrated phase-noise values that must be resolved before the comparison to manufacturer values can be assessed.","major_comments":[{"comment":"The 30-hour cycle-slip-free claim is not backed by a defined slip-detection procedure. The paper should state the Agilent 53132A counter's gate time, dead time, measurement mode, number of samples, and any outlier-rejection or threshold criteria used to declare the data slip-free. With a gated counter, a brief 2π phase excursion occurring during dead time, or a transient that is averaged over a long gate, could be hidden in the displayed statistics. The quoted standard deviations of 0.1-0.2 mHz are only meaningful if every gate was continuously recorded; a single cycle slip within a 1 s gate would shift the counted frequency by roughly 1 Hz and would be visible only if that gate were included in the analysis. Please provide the raw time series or the analysis script used to establish the slip-free determination.","section":"§3.2, Fig. 6"},{"comment":"The integrated phase-noise values are assigned inconsistently between the text and the figure caption. Section 3.1 states that the integrated phase noise is 114 mrad for f_ceo and 41 mrad for f_beat, and the conclusions repeat the 41 mrad / 114 mrad pairing, but the Fig. 5 caption assigns 114 mrad to f_beat and 40 mrad to f_ceo. This directly affects the central claim that the digital servo performs comparably to the manufacturer's values of 85 mrad and 43 mrad, because swapping the labels changes which lock is compared to which specification. The caption and text must be reconciled, and the corresponding value should be used consistently in the abstract and conclusions.","section":"§3.1, Fig. 5"},{"comment":"The manufacturer comparison is not fully specified. The statement that 'the laser's manufacturer reports values of 85 mrad and 43 mrad' is given without a citation or a statement of the bandwidth and measurement conditions for those values. If the manufacturer's numbers are integrated over a different band, or were obtained with different loop gain settings, the conclusion that the Red Pitaya is not a significant limitation is not established. Please provide the source of the manufacturer values and confirm that the comparison is over the same 100 Hz to 2 MHz integration range.","section":"§3.1"}],"minor_comments":[{"comment":"The abstract says 'residual phase noise at or below ~0.1 rad,' but the reported f_ceo value of 114 mrad exceeds 100 mrad; either relax the wording or state explicitly that 0.1 rad is an approximate bound.","section":"Abstract / §3.1"},{"comment":"The calculation of the 70 attosecond timing jitter is not shown. Please state the formula and the carrier frequency or optical frequency used, so that a reader can reproduce the conversion from integrated phase noise to timing jitter.","section":"§3.1"},{"comment":"Please clarify how the reported frequency deviations and standard deviations are computed, especially for f_rep, which is described as having a linear drift corrected before the 0.1 mHz standard deviation is calculated.","section":"§3.2, Fig. 6"},{"comment":"The phrase 'up to 222π radians' appears to be a typesetting artifact; it should read 'up to 2^22 π radians' if that is the intended claim.","section":"§1"},{"comment":"The text says that the optically derived f_ceo and f_beat are 'in-loop measurements' in the Allan deviation discussion, while earlier the paper states that the reported measurements were made with instruments 'out of loop to the phase locks'; please reconcile this terminology.","section":"§3.2"},{"comment":"In Table 1, the 'Modulation Control' row for the slow f_beat path lists '0 to 1 V' while the other paths list '-1 to 1 V'; please confirm this is intentional and clarify the voltage convention.","section":"Table 1"}],"recommendation":"major_revision","confidential_remarks":"The work is a solid experimental demonstration and appears well within the journal's scope. The main concern is that the 30-hour cycle-slip-free headline is not yet independently supported without explicit gate/dead-time and slip-detection criteria; this should be fixable by adding methodological detail or raw data. The phase-noise figure/caption inconsistency also needs correction before acceptance. The paper builds closely on the authors' prior DPLL work (Ref. [46]), but the application to a commercial comb and the long-term stability study provide sufficient incremental contribution if the documentation gaps are addressed."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is a useful engineering paper, not a conceptual breakthrough. It takes an existing open-source digital PLL (Tourigny-Plante et al. 2018), runs it on a Red Pitaya FPGA, and locks both f_ceo and f_beat of a commercial Menlo Er:fiber comb. The out-of-loop phase noise measurements are believable, and the comparison to the manufacturer's quoted numbers is a good benchmark. The 30-hour slip-free claim is plausible but under-documented.\n\nWhat's genuinely good: the authors are careful about in-loop versus out-of-loop diagnostics. They explicitly note that the FPGA's internal counter sees artificially low noise, and they report instead measurements from an external signal analyzer and frequency counters referenced to a shared maser. The measured integrated phase noise (41/114 mrad, modulo the caption mix-up) and the derived 70 as timing jitter are consistent with the manufacturer's specs. The RF-lock demonstration and the factor-of-400,000 sensitivity comparison are nice practical touches. The writing is clear, and the experimental section is reproducible in spirit, though not quite in letter.\n\nSoft spots, in increasing order of seriousness. First, Fig. 5's caption swaps the f_ceo and f_beat labels relative to the text; also the abstract's ~0.1 rad sits oddly with the f_ceo value of 114 mrad. Minor, but worth fixing. Second is the 30-hour cycle-slip claim. The paper states that the counters show no slips, but it never gives the gate time, the dead time, or the criterion used to decide that a point is a slip rather than a glitch or an outlier. A single cycle slip would appear as a large frequency excursion if the counters were continuous, so the claim is credible; but as written it is not independently checkable. That is a reporting gap, not a fatal flaw. Third, no code URL beyond \"a fork of the Github repository\" and no commit hash; for a paper whose message is that open-source digital locks are the way to go, this is a miss.\n\nOverall the central argument holds up: a low-cost board plus open firmware performs like manufacturer electronics. I would send this to a serious referee and expect it to come back with minor revisions. The right reader is someone building a comb system on a budget or a teaching lab; they will get a clear template. I'd cite it if I were writing an instrumentation paper on low-cost frequency control.","headline":"A solid, incremental demonstration that a low-cost FPGA digital PLL can match manufacturer electronics for comb stabilization; worth a referee, with a few reporting gaps to fix.","tokens_in":682,"tokens_out":1174,"would_cite":true,"duration_ms":34994,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A low-cost FPGA board phase-locks a commercial laser frequency comb for 30 hours without a single cycle slip.","keywords":["optical frequency comb","FPGA","digital phase-locked loop","carrier-envelope offset frequency","repetition rate stabilization","Er:fiber laser","phase noise","cycle-slip-free locking"],"falsifier":"Record the phase-error signal out of loop during a 30-hour lock and scan for any discrete $2\\pi$ jump in a phase record sampled faster than the counter gate time; if one appears, the claimed slip-free duration is not valid. A simpler version: inspect the counter time series for adjacent pairs whose difference exceeds the expected drift plus counter dead time — that pattern is the signature of a hidden cycle slip.","tokens_in":9645,"feed_emoji":"🔒","tokens_out":6869,"duration_ms":66129,"temperature":0.7,"pith_summary":"This paper establishes that the two radio-frequency handles of an optical frequency comb—its repetition rate and its carrier-envelope offset—can both be phase-locked by a single inexpensive FPGA board running open-source digital servo code, instead of the manufacturer's dedicated lock electronics. Using only the fast electro-optic and slow thermal/piezo actuators already inside a commercial erbium-fiber comb, the servos hold both optical beat notes without a single phase slip for 30 hours. Out-of-loop measurements show residual phase noise at or below about 0.1 rad from 100 Hz to 2 MHz, corresponding to roughly 70 attoseconds of timing jitter, comparable to the laser manufacturer's quoted performance. The significance is practical: phase-stabilized combs become cheaper, more modular, and programmable, which lowers the barrier for field use, dual-comb spectroscopy, optical ranging, and student-lab projects.","feed_headline":"Low-cost FPGA board locks a laser comb for 30 hours","feed_subtitle":"Open-source digital servos match manufacturer electronics with under 100 attoseconds of timing jitter.","key_machinery":"The work's load-bearing object is an FPGA-based digital phase-locked loop: the board digitizes the optical beat note, mixes it with digitally synthesized I/Q reference frequencies to extract a phase error, forms a frequency error from the one-clock-cycle difference of that phase, and passes it through a loop filter with proportional, integral, double-integral, and differential terms (PII2D). Two such loops run in parallel, one for $f_\\text{ceo}$ and one for $f_\\text{beat}$, and each is backed by a slow auxiliary servo (a 10 Hz current controller on the $f_\\text{ceo}$ modulator's thermoelectric cooler and a 1 Hz piezo driver in the laser cavity) that keeps the fast electro-optic actuators centered. This two-tier architecture is what lets the fast loop provide ~100 kHz bandwidth and sub-0.1 rad residual phase while the slow loops absorb long-term drift, sustaining a slip-free lock beyond a day. The same FPGA simultaneously records the error signals, which is how a single platform acts as its own phase-noise analyzer and frequency counter.","core_discovery":"The central claim is that a generic digital phase-locked loop implemented on a low-cost FPGA board—rather than in analog circuits or vendor-specific digital boxes—can simultaneously stabilize the carrier-envelope offset frequency $f_\\text{ceo}$ and the repetition rate $f_\\text{rep}$ of a commercial Er:fiber comb to a level comparable with the laser's own control electronics. The paper reports integrated phase noise of 41 mrad on the optical beat note $f_\\text{beat}$ and 114 mrad on $f_\\text{ceo}$ (100 Hz to 2 MHz), corresponding to 70 as timing jitter, and cycle-slip-free locking maintained over a continuous 30-hour run. It also shows the same hardware can lock the repetition rate directly in the radio-frequency domain simply by switching inputs and recalling saved PID settings, with the optical beat note roughly 400,000 times more sensitive to the repetition-rate actuator than the RF beat note, as the comb equation predicts.","pith_inferences":["An immediate testable extension is to add an out-of-loop cycle-slip detector to the same FPGA firmware; because the paper specifies no slip-detection threshold for the 30-hour claim, an independent counter of $2\\pi$ phase jumps would make the lock-duration number self-verifying.","The measured ~400,000-fold sensitivity difference between the RF and optical beat notes to the repetition-rate actuator could be used as a quick diagnostic: measuring that ratio on a new comb predicts how much leverage an optical lock will provide before building the full setup.","The software-defined nature of the loop filter suggests the same board could phase-lock noisier or broader-linewidth sources than the manufacturer laser used here, since capture range and filter shape can be retuned without hardware changes; the paper does not demonstrate this.","The paper's own in-loop bias caveat implies that anyone replicating the results should report out-of-loop phase noise, not the internal counter, when comparing lock quality; adopting that habit in future FPGA-based comb papers would make published stability numbers more directly comparable."],"forward_implications":["Phase noise of 41 mrad on $f_\\text{beat}$ and 114 mrad on $f_\\text{ceo}$ (100 Hz to 2 MHz) puts the lock within a factor of 1–2 of the manufacturer's quoted 43 and 85 mrad, so the low-cost board is not the limiting element.","The 70 attosecond integrated timing jitter satisfies the jitter budget of broadband dual-comb spectroscopy and is below current requirements for optical ranging and fiber-network timing transfer.","Because the same board can lock the repetition rate optically or in the RF domain by switching ADC input and recalling saved PID settings, one platform replaces two distinct control chains.","The slow servos keep the fast EOMs centered over long intervals, which is what allows continuous slip-free locking beyond 30 hours.","The board's built-in diagnostics mean that locking and characterization need no separate spectrum analyzer, phase-noise analyzer, or frequency counter."],"supporting_citations":[{"why":"Supplies the FPGA firmware architecture and Python control code, including I/Q phase detection, the PII2D loop filter, and the 565 ns latency figure used to estimate the ~100 kHz feedback bandwidth.","marker":"[46]"},{"why":"Describes the commercial all-polarization-maintaining Er:fiber laser whose repetition rate and carrier-envelope offset are locked in this work.","marker":"[48]"},{"why":"Provides the digital phase-locked-loop code base and the demonstration of unwrapping phase deviations beyond the $2\\pi$ ambiguity that the servo builds on.","marker":"[35]"},{"why":"Prior demonstration of slip-free digital clockwork operation that this work extends to an inexpensive, general-purpose FPGA platform.","marker":"[42]"},{"why":"Establishes the Er:fiber-based octave-spanning supercontinuum approach used here to generate the f-2f signal for $f_\\text{ceo}$.","marker":"[51]"},{"why":"Provides the PPLN ridge waveguide that frequency-doubles 2 µm comb light to generate the $f_\\text{ceo}$ beat note.","marker":"[52]"},{"why":"Describes the electro-optic modulator used as the fast actuator on $f_\\text{ceo}$ in the feedback chain.","marker":"[53]"},{"why":"Gives the comb equation linking tooth frequency to $f_\\text{rep}$ and $f_\\text{ceo}$, the relation the servo controls.","marker":"[29]"}],"fun_headline_variants":["Open-source FPGA locks comb for 30 hours","FPGA servo locks comb to 70 as jitter","30-hour comb lock with 70 as precision","Digital servo locks comb beats for 30h"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The 30-hour cycle-slip-free claim assumes the external frequency-counter records shown in Fig. 6 catch every skipped cycle, but the paper gives no threshold or algorithm for identifying slips, so a brief $2\\pi$ phase excursion between counter gates would go unnoticed.","fun_headline_variants_meta":{"raw":{"variants":["Open-source FPGA locks comb for 30 hours","FPGA servo locks comb to 70 as jitter","30-hour comb lock with 70 as precision","Digital servo locks comb beats for 30h"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00057,"raw_usage":{"total_tokens":2673,"prompt_tokens":901,"completion_tokens":1772,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":517,"completion_tokens_details":{"reasoning_tokens":1711}},"tokens_in":517,"tokens_out":1772,"duration_ms":13717,"temperature":1.0,"reasoning_tokens":1711,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T11:18:48.368635+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Record the phase-error signal out of loop during a 30-hour lock and scan for any discrete $2\\pi$ jump in a phase record sampled faster than the counter gate time; if one appears, the claimed slip-free duration is not valid. A simpler version: inspect the counter time series for adjacent pairs whose difference exceeds the expected drift plus counter dead time — that pattern is the signature of a hidden cycle slip.","supporting_citations":[{"cited_title":"An open and flexible digital phase-locked loop for optical metrology,","cited_arxiv_id":null,"evidence_quote":"Supplies the FPGA firmware architecture and Python control code, including I/Q phase detection, the PII2D loop filter, and the 565 ns latency figure used to estimate the ~100 kHz feedback bandwidth."},{"cited_title":"All polarization-maintaining fiber laser architecture for robust femtosecond pulse generation,","cited_arxiv_id":null,"evidence_quote":"Describes the commercial all-polarization-maintaining Er:fiber laser whose repetition rate and carrier-envelope offset are locked in this work."},{"cited_title":"Deschênes, Digital PLL code base, see https://github.com/jddes/Frequency-comb-DPLL","cited_arxiv_id":null,"evidence_quote":"Provides the digital phase-locked-loop code base and the demonstration of unwrapping phase deviations beyond the $2\\pi$ ambiguity that the servo builds on."},{"cited_title":"Femtosecondtimekeeping: Slip-freeclockworkforopticaltimescales,","cited_arxiv_id":null,"evidence_quote":"Prior demonstration of slip-free digital clockwork operation that this work extends to an inexpensive, general-purpose FPGA platform."},{"cited_title":"Phase-locked, erbium-fiber-laser-based frequency comb in the near infrared,","cited_arxiv_id":null,"evidence_quote":"Establishes the Er:fiber-based octave-spanning supercontinuum approach used here to generate the f-2f signal for $f_\\text{ceo}$."},{"cited_title":"Direct-bonded qpm-ln ridge waveguide with high damage resistance at room temperature,","cited_arxiv_id":null,"evidence_quote":"Provides the PPLN ridge waveguide that frequency-doubles 2 µm comb light to generate the $f_\\text{ceo}$ beat note."},{"cited_title":"Electro-optic modulator for rapid control of the carrier-envelope offset frequency,","cited_arxiv_id":null,"evidence_quote":"Describes the electro-optic modulator used as the fast actuator on $f_\\text{ceo}$ in the feedback chain."},{"cited_title":"Optical frequency metrology,","cited_arxiv_id":null,"evidence_quote":"Gives the comb equation linking tooth frequency to $f_\\text{rep}$ and $f_\\text{ceo}$, the relation the servo controls."}],"review_version":1}