{"id":"bbbc59a2-dde6-4030-b99c-8d25c63b75b5","arxiv_id":"1908.10674","paper_version":1,"verdict":"UNVERDICTED","confidence":"MODERATE","novelty_score":2.0,"correctness_risk":"unknown","formal_verification":"none","parameter_count":0,"one_line_summary":"A practical guide for analog VLSI designers to tape out integrated circuits using the SCL 180nm CMOS foundry.","lead":"This tutorial paper instructs analog VLSI designers on preparing chip layouts for fabrication at India's SCL 180nm CMOS foundry. It details the full flow from schematic simulation through layout, verification, and tape-out file submission.","discovery_kind":"review","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 'all requisite information' claim is not self-contained: §2.1 delegates PDK/tool setup to an external expert, so the tutorial cannot be reproduced or verified without proprietary SCL files and exact EDA versions.","rationale":"The reader's verdict of UNVERDICTED rests on the same load-bearing assumption I identified: the paper's instructions are only usable if the reader already has a correctly set-up SCL PDK, runset files, and licensed Cadence/Calibre tools. My reading of §2.1 and the appendix confirms that the paper explicitly excludes environment setup and provides no way to validate the steps against the proprietary components. This is not a reason to reject the tutorial; it is a reason to treat the abstract's 'all requisite information' phrasing as an overstatement relative to the body. The paper is transparent about its scope and should be useful to designers who already have the SCL environment, but its central claim cannot be independently verified without access to those external components. Since the reader already flagged this and assigned UNVERDICTED, I do not see a new concern that would move the verdict. The concrete test would settle whether the omission is merely a scoping choice or an actual gap that prevents a fresh designer from reaching tape-out; until such a test is run, UNVERDICTED remains the honest verdict.","tokens_in":11751,"tokens_out":5011,"duration_ms":50113,"concrete_test":"Obtain the SCL 180nm PDK (ts018_scl_prim, CIO150/CIO250, drc.rsf, lvs.rsf, pex.rsf, antenna.rsf, DUMMY.header), install the exact tool versions listed in the appendix (Cadence IC6.1.5.500.17, Calibre v2013.2_18.13, HSPICE J-2014.09-2), and have a fresh analog designer follow §3–§7 to tape out a minimal inverter with I/O ring. Record every point where the instructions require undocumented knowledge (e.g., DUMMY.header editing, CDF termOrder, manual CDL port reordering). If any step cannot be completed without additional SCL support or undocumented configuration, the 'all requisite information' claim is falsified.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The abstract's central claim is that the paper provides 'all the requisite information and guidance' needed to prepare chip designs for SCL submission. The body immediately narrows this: §2.1 states that environment and tool setup 'is required to be done by a person experienced in setting up of such tools' and is not covered, and every later step depends on proprietary runset files (drc.rsf, lvs.rsf, pex.rsf, antenna.rsf, DUMMY.header) and PDK libraries (ts018_scl_prim, CIO150, CIO250) that are referenced but neither supplied nor described at a level that lets an independent reader obtain or configure them correctly. The appendix lists EDA versions but provides no checksums, test cases, or validated output to confirm the flow. Consequently, the central claim is conditional on an external, unverifiable environment; if those components are unavailable or differ from the author's setup, the steps may silently fail. This is not an internal mathematical inconsistency, but it makes the completeness claim impossible to assess from the paper alone and means a reader cannot go from design to tape-out using only the paper.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper is a tutorial for academic analog VLSI designers who wish to submit chip layouts to the SCL 180 nm CMOS foundry in Chandigarh. It walks through the entire design-to-tape-out flow: setting up a working directory and model libraries, schematic simulation in Cadence Virtuoso ADE, physical design with SCL layers, Calibre DRC/antenna/LVS, parasitic extraction and post-layout simulation (including a CDF-based 'spectre' view and MTS co-simulation), Monte Carlo analysis, construction of an I/O pad ring from SCL's CIO150/CIO250 libraries, and final tape-out steps (seal ring, silicon number, dummy fill, full-chip DRC, GDS export, and MOSIS CRC checksum). The abstract and introduction claim the paper provides all requisite information and guidance for preparing designs for SCL submission.","tokens_in":11930,"tokens_out":7485,"duration_ms":72741,"significance":"If the described flow is accurate, the tutorial addresses a real information gap for Indian academic groups using SCL MPW runs, and several documented workarounds—particularly the CDF 'spectre' view for PEX netlists, the MTS-based co-simulation of extracted blocks with schematic blocks, and the I/O ring CDL port-order fixes—are non-obvious and likely to save significant time. The paper is honest about its dependence on a pre-installed SCL PDK and gives exact EDA versions in the appendix. Its main limitations are that the completeness claim exceeds what the body delivers and that the flow is not independently validated by a worked example with run logs and a tape-out outcome. If the authors revise the scope claim and add a validation case, the paper would be a useful service piece for the IETE Journal of Education.","major_comments":[{"comment":"The abstract and introduction claim that the paper provides 'all the requisite information and guidance' needed to prepare chip designs for SCL fabrication, but §2.1 explicitly defers environment and tool setup to an experienced lab administrator and states that such details are not provided. Moreover, the steps in §§3–7 all presume the reader already has the proprietary SCL PDK (ts018_scl_prim), the runset files (drc.rsf, lvs.rsf, pex.rsf, antenna.rsf), the I/O libraries (CIO150/CIO250), and GDS templates that are referenced but not supplied or specified to the level of file versions and checksums. A reader who does not already have these components cannot execute the flow, so the completeness claim is not supported. Please either narrow the claim to 'a guide for designers with an installed and qualified SCL PDK environment' or add an appendix that itemizes every external file with its source, version, and a minimal smoke test.","section":"Abstract, §2.1"},{"comment":"The paper gives no evidence that the flow was executed end-to-end on a concrete design. There is no example with DRC/LVS/PEX run reports, no post-layout simulation output, and no statement of which designs successfully reached tape-out using these instructions. Because the central value of the paper is the reliability of this sequence, I ask for a small worked case study (for example, an inverter or comparator with an I/O ring) that includes the final GDS checksum and the DRC/antenna results-summary files mentioned in §7.4. This would let readers verify tool-version-specific behavior and would substantiate the claim that the steps are sufficient.","section":"§3–§7 (overall validation)"},{"comment":"§7.4 instructs the reader to edit a DRC.header file by uncommenting '#define CHIP' and to submit the resulting results-summary file to SCL, but DRC.header is never introduced earlier: §3.2 describes running DRC only in terms of loading drc.rsf, and the origin of DRC.header and of the results-summary file is not explained. Likewise, §7.3 tells the reader to run 'calibre -drc ./DUMMY.header' without explaining how this header relates to the Calibre runset format or what inputs it expects beyond the paths shown in Fig. 9. These omissions make the final tape-out steps impossible to execute from the paper alone and should be addressed with explicit file-location and generation instructions.","section":"§7.4, §7.3"},{"comment":"The appendix lists exact EDA tool versions, but the text does not state which steps are sensitive to version changes. In particular, the CDF editing and MTS setup in §4.2–§4.3, the Calibre header edits in §6.4 and §7.4, and the runset file formats are likely to differ between tool releases. The authors should mark the tested versions on the relevant figures and commands and add a short 'version compatibility' note warning readers where newer releases may require different menu paths or runset syntax.","section":"Appendix, version sensitivity"}],"minor_comments":[{"comment":"The file name is given as tsl18cio150.cdl in the text but as ts018150.cdl in the figure caption; please make the names consistent and specify whether the file is part of the CIO150 distribution or the SCL PDK.","section":"§6.2.1, Fig. 6"},{"comment":"The grid snap instruction uses '0.005µm' and then says '0.005 (i.e., 5nm)'; please state the unit explicitly in the dialog entry (0.005 µm) to avoid ambiguity.","section":"§3.1"},{"comment":"The instruction to 'edit individual characters by changing their property' is vague; please provide the property name or a screenshot showing the edited silicon number block.","section":"§7.2"},{"comment":"The references to internal SCL and Tower documents lack version identifiers and accession dates; since these documents are not publicly available, the authors should provide document numbers or contact information for obtaining them.","section":"References [5], [6], [15], [16]"},{"comment":"The figures are screen captures that appear difficult to read at print resolution, especially the smaller panels in Figs. 4 and 7; enlarging or redrawing the key panels would improve usability.","section":"Figures 2–4, 7"}],"recommendation":"major_revision","confidential_remarks":"The paper is a tutorial rather than a research contribution, which is appropriate for IETE Journal of Education. The main risk is overclaiming completeness; the paper currently reads as an internal lab manual and would benefit from a clearer statement of scope and a validation case. I would not recommend rejection, but the authors should be required to address the completeness and validation issues. No concerns about citation patterns beyond the unavoidable reliance on proprietary vendor documentation."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"This is a tutorial, not a research result, and it is honest about being one. What it does well is concrete: it walks a designer through the SCL 180nm tape-out flow from schematic to GDS with specific runset names, CDF edits, the I/O ring LVS hack, dummy fill, and the CRC step. That information has been scattered across SCL manuals, tool docs, and lab folklore; pulling it together is genuinely useful. The author clearly knows the flow, and the appendix's list of tool versions plus the acknowledgments to SCL engineers give me confidence the steps came from real tape-outs, not from imagination.\n\nThe soft spots are real but not disqualifying. The abstract promises 'all the requisite information,' but §2.1 explicitly leaves environment and tool setup to an experienced lab admin, and the steps depend on proprietary PDK files (ts018_scl_prim, drc.rsf, lvs.rsf, pex.rsf, DUMMY.header, tsl18cio150.cdl) that are referenced but not supplied or described well enough to reproduce independently. No test case, no validated output, no die photo. So the completeness claim is overstated; a reader with a different tool version or an updated PDK will have to adapt. That said, the appendix's hedge is appropriate: the author acknowledges the best-effort nature and that there may be better methods.\n\nWhat the paper is not: it's not a scientific contribution, no new circuits, no measurements, no falsifiable predictions. The novelty score of 2 out of 10 is about right. But for a tutorial, novelty isn't the right yardstick. The value is in the details: the specific pad names in the I/O library, the LVS error workaround, the MTS co-simulation recipe, the dummy fill header editing. Those are the things that eat weeks of a student's time.\n\nThe citation pattern looks fine: it cites SCL and tool manuals, and the MOSIS checksum page. No self-citation issues.\n\nBottom line: if I were advising an Indian academic group about to submit to SCL, I'd hand them this paper and tell them to read it, then verify against their own lab setup. It deserves a serious referee — an experienced SCL tape-out engineer — to check for drift and version issues, but a desk reject would be wrong. I'd accept it for peer review as a tutorial contribution.","headline":"A genuinely useful tutorial for the SCL 180nm tape-out flow, with an overstated completeness claim; worthwhile for its niche and deserves refereeing.","tokens_in":12395,"tokens_out":1999,"would_cite":false,"duration_ms":21077,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"One tutorial maps the complete route from schematic to tape-out at SCL's 180nm CMOS foundry.","keywords":["SCL","180nm CMOS","tape-out","analog VLSI design","Cadence Virtuoso","Calibre layout verification","post-layout simulation","Multi Project Wafer"],"falsifier":"Run the paper's own demonstration project — an inverter core inside a CIO150 I/O ring — in the stated environment and follow every step. If the ring is not LVS clean, or the MTS co-simulation of the PEX netlist with a schematic block does not reproduce the all-schematic simulation results, the tutorial's claim of completeness fails; a sharper test is that reverting to the schematic view by unchecking MTS (as in Section 4.3) must exactly reproduce the schematic-only waveforms.","tokens_in":11546,"feed_emoji":"⚙️","tokens_out":8774,"duration_ms":80707,"temperature":0.7,"pith_summary":"This paper claims to assemble, in one place, all the information an analog VLSI designer needs to take a chip from a frozen schematic to a GDSII tape-out submission at the Semi-Conductor Laboratory's (SCL) 180nm CMOS foundry in Chandigarh, India. It documents the entire flow: schematic simulation in Cadence Virtuoso with the Spectre simulator, layout with design-rule, antenna, and layout-versus-schematic checks in Calibre, parasitic extraction and post-layout simulation, Monte Carlo analysis, assembly of the I/O ring from SCL's CIO150 pad library, and the closing tape-out steps of seal ring, silicon number, dummy metal fill, full-chip DRC, GDS generation, and CRC checksum. The practical point is that this workflow previously had to be reconstructed piecemeal, costing both academic designers and SCL liaison engineers considerable time, and the paper intends to close that gap so Indian academic and research groups can realistically use SCL's cost-effective Multi Project Wafer runs. If the guide works as written, a designer at any Indian institution with the right tool setup can produce a submission package SCL will accept.","feed_headline":"A complete design-to-tape-out route for SCL's 180nm CMOS line","feed_subtitle":"Step-by-step guidance for Indian academic designers submitting chips to SCL's cost-effective Multi Project Wafer runs","key_machinery":"The machine that carries the argument is the standard academic verification toolchain — Cadence Virtuoso with Spectre for simulation and a foundry-calibrated Calibre deck for physical verification — wired to SCL's 180nm process design kit (the ts018_scl_prim library and the ts18sl_scl.lib model file). The load-bearing mechanism inside that machine is scale handling: schematics carry dimensions in micrometres and run with scale = 1e-6 in the simulator, while Calibre's parasitic extraction emits a netlist in absolute metres that must run with scale = 1; the CDF 'model' parameter, the copied 'spectre' view, and ADE-XL's MTS mode are the workaround that lets an extracted sub-circuit be instantiated like a symbol and co-simulated with schematic blocks. Around that core sit the procedural fixtures: the runset files drc.rsf, lvs.rsf, pex.rsf and antenna.rsf, the tsl18cio150.cdl pad netlist, SCL-supplied seal-ring and silicon-number GDS blocks, the DUMMYFILL Calibre deck driven by DUMMY.header, and the mosiscrc.c checksum utility that closes the loop on GDS integrity.","core_discovery":"The central claim is that the procedures collected here form a complete and sufficient route to tape-out in SCL's 180nm CMOS process, provided the standard tool environment is already in place. The contribution is not a new circuit technique but a documented, debugged sequence of operations, including several non-obvious workarounds: setting the Component Description Format (CDF) 'model' parameter and creating a 'spectre' view (a copy of a cell's symbol that makes the simulator use the extracted netlist instead of the schematic); using ADE-XL's Multi-Technology Simulation (MTS) to co-simulate extracted netlists alongside schematic-level blocks despite their conflicting scale settings (1e-6 for schematics, 1 for extracted netlists); editing the exported CDL file so Calibre LVS can compare the I/O ring against the pad definitions in tsl18cio150.cdl; and commenting out the '#define ANALOG' line in the LVS header when pad resistors trigger 'property w not found' errors. Each step is presented as it was exercised in the author's own environment, with the explicit caveat that environment and tool setup are deliberately left to a qualified lab administrator.","pith_inferences":["A testable extension would be to run the identical flow with newer tool releases: the appendix pins the versions (Virtuoso IC6.1.5, Calibre v2013.2, HSPICE J-2014.09), and the tutorial's viability on current Cadence and Calibre releases is an open question the paper does not address.","The need to hand-edit exported CDL files and comment out runset defines suggests the SCL runsets retain Tower-Semiconductor options; designers should expect to maintain small local patches to the runset headers as their designs grow.","The tutorial implicitly maps SCL's tape-out interface for the first time in the open literature, and that alone may lower the perceived risk of using an Indian foundry, so the guide's existence may be as valuable as its content.","If SCL's Multi Project Wafer program expands, this workflow could become the seed of a standard Indian academic tape-out curriculum, since it names every file and form a student needs in advance."],"forward_implications":["Indian academic and R&D groups can target SCL Multi Project Wafer runs without reconstructing the workflow from scratch, removing the information gap the paper identifies as the main source of lost time.","A designer who follows the guide ends with the full submission package SCL requires: GDSII, DRC and antenna results summaries, stream-out logs and layer lists, device lists, and the CRC checksum from mosiscrc.c.","The documented co-simulation method — CDF model parameter, spectre view, and MTS — gives a reusable recipe for any design that mixes extracted netlists with schematic blocks, not just SCL designs.","Because block-level DRC checks 356 rules while full-chip DRC checks 421, the guide lets designers budget verification effort and plan for dummy fill and seal ring before the final run.","The steps for the 1.8V CIO150 pad library carry over to the 3.3V CIO250 library, and the same flow works for digital cores, so the paper's reach extends beyond analog designs, as the author states."],"supporting_citations":[{"why":"Website of Semi-Conductor Laboratory: establishes the 180nm process features and the foundry's role as the tape-out destination.","marker":"[5]"},{"why":"SPICE Models for TS18 Standard Logic Process (SCL): supplies the model library ts18sl_scl.lib and the device set used in every simulation step.","marker":"[6]"},{"why":"Calibre Interactive and Calibre RVE User's Manual: basis for the DRC, antenna, LVS, and PEX runset procedures that structure the physical verification flow.","marker":"[11]"},{"why":"Virtuoso ADE XL User Guide: underpins the Monte Carlo setup and the ADE-XL Multi-Technology Simulation used for co-simulation with PEX netlists.","marker":"[14]"},{"why":"TSL18CIO150 I/O pad library: source of the pad, filler, and corner cells, and of tsl18cio150.cdl, which defines the pad netlists the I/O ring LVS compares against.","marker":"[15]"},{"why":"Design Rules for TS18 Standard Logic Process for SCL: provides the DRC rules, seal ring rules, and LVS device names that the verification steps rely on.","marker":"[16]"},{"why":"MOSIS checksum utility (mosiscrc.c): supplies the CRC checksum pair that SCL uses to verify the submitted GDSII file's integrity.","marker":"[17]"}],"fun_headline_variants":["SCL 180nm tape-out: a practical step-by-step for chip designers","Submit your chip to SCL 180nm: a designer's tape-out guide","SCL 180nm tape-out explained: from design to fabrication","A practical route to SCL 180nm CMOS tape-out","Design-to-tape-out for SCL 180nm: an Indian academic guide"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The whole recipe presupposes that the designer already has a working SCL 180nm process design kit (ts018_scl_prim), the Calibre runset files, licensed Cadence and Calibre tools, and a lab administrator who has installed and configured them, because Section 2.1 explicitly leaves environment setup out.","fun_headline_variants_meta":{"raw":{"variants":["SCL 180nm tape-out: a practical step-by-step for chip designers","Submit your chip to SCL 180nm: a designer's tape-out guide","SCL 180nm tape-out explained: from design to fabrication","A practical route to SCL 180nm CMOS tape-out","Design-to-tape-out for SCL 180nm: an Indian academic guide"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000983,"raw_usage":{"total_tokens":4166,"prompt_tokens":937,"completion_tokens":3229,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":553,"completion_tokens_details":{"reasoning_tokens":3130}},"tokens_in":553,"tokens_out":3229,"duration_ms":25294,"temperature":1.0,"reasoning_tokens":3130,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T11:19:36.701199+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the paper's own demonstration project — an inverter core inside a CIO150 I/O ring — in the stated environment and follow every step. If the ring is not LVS clean, or the MTS co-simulation of the PEX netlist with a schematic block does not reproduce the all-schematic simulation results, the tutorial's claim of completeness fails; a sharper test is that reverting to the schematic view by unchecking MTS (as in Section 4.3) must exactly reproduce the schematic-only waveforms.","supporting_citations":[{"cited_title":"http://www.scl.gov.in/cmos_fab_facility.html","cited_arxiv_id":null,"evidence_quote":"Website of Semi-Conductor Laboratory: establishes the 180nm process features and the foundry's role as the tape-out destination."},{"cited_title":"Name: DRS2_0018SL_SCL, SCL, Chandigarh","cited_arxiv_id":null,"evidence_quote":"SPICE Models for TS18 Standard Logic Process (SCL): supplies the model library ts18sl_scl.lib and the device set used in every simulation step."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Calibre Interactive and Calibre RVE User's Manual: basis for the DRC, antenna, LVS, and PEX runset procedures that structure the physical verification flow."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Virtuoso ADE XL User Guide: underpins the Monte Carlo setup and the ADE-XL Multi-Technology Simulation used for co-simulation with PEX netlists."},{"cited_title":"1.0, 2003","cited_arxiv_id":null,"evidence_quote":"TSL18CIO150 I/O pad library: source of the pad, filler, and corner cells, and of tsl18cio150.cdl, which defines the pad netlists the I/O ring LVS compares against."},{"cited_title":"Name: DR2_0018_SL, SCL, Chandigarh","cited_arxiv_id":null,"evidence_quote":"Design Rules for TS18 Standard Logic Process for SCL: provides the DRC rules, seal ring rules, and LVS device names that the verification steps rely on."},{"cited_title":"https://www.mosis.com/pages/ support/submit/term_chksum","cited_arxiv_id":null,"evidence_quote":"MOSIS checksum utility (mosiscrc.c): supplies the CRC checksum pair that SCL uses to verify the submitted GDSII file's integrity."}],"review_version":1}