{"id":"96302991-4672-44ab-8e23-4ca741e0a696","arxiv_id":"1908.11242","paper_version":2,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A 12-channel, 24-bit ADC board with programmable anti-aliasing filters achieves 21.1 effective bits at 5 ksps for the CROSS bolometric experiment.","lead":"This paper describes a custom data acquisition board for the CROSS experiment, which searches for a rare nuclear decay. The board digitizes bolometer signals with 21-bit effective resolution at the needed speeds and uses a programmable filter and an FPGA for readout.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The quoted effective resolution is a single-board, direct-ADC-readout result; the full 96-channel FPGA/UDP path is acknowledged as untested in Sec. 4, so the system-level resolution claim rests on an unverified noise-transfer assumption.","rationale":"The single-board analog results are credible and self-consistent: the three RMS values correspond to the same full-scale range (approximately 20 V peak-to-peak), and the analog filter noise (5.7-7.1 uV) is comparable to but below the 5-ksps digitized noise, consistent with ADC/buffer dominance. The soft spot is not the arithmetic but the extrapolation to the deployed system. The paper's own Sec. 4 admits the full-rate multi-board readout is future work, and nothing in the characterization section quantifies simultaneous-channel or FPGA/UDP-induced noise. This is exactly the condition that must hold for the quoted 21.1 effective bits at 5 ksps to be the performance CROSS will actually use. The reader's conditional verdict is appropriate; I would not change it, though I would sharpen the condition by also requiring a simultaneous-all-channels test on a single board, not only a multi-board test.","tokens_in":3628,"tokens_out":5441,"duration_ms":52462,"concrete_test":"On a fully populated board, ground all 12 inputs, set the anti-aliasing filter to the same cutoff as in the characterization, and acquire all channels at 5 ksps and 25 ksps through the FPGA/UDP chain, using the provisional backpanel at minimum and an 8-board backplane if available. Compute per-channel RMS noise and effective bits. Accept the resolution claim if the values match 9.2 uV and 24 uV within measurement uncertainty; otherwise restate the claim as single-channel direct-readout performance.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central performance claim is the measured effective resolution: 22.0/21.1/19.7 bits at 1/5/25 ksps, corresponding to 4.7/9.2/24 uV RMS. The manuscript reports these values from first sample boards with direct ADC readout in a lab setup. For CROSS, the deployed configuration is 12 channels per board, 8 boards per FPGA, continuous acquisition through 20 MHz SPI and UDP Ethernet at up to 768 Mbps. Section 4 states explicitly that the full backpanel 'will be designed' and that only after a prototype detector test can the system be qualified at full output data rate with multiple boards. The paper therefore contains no measurement of crosstalk, simultaneous-channel noise, or digital-activity-induced noise in the final readout chain. If enabling all 12 ADCs simultaneously or operating the FPGA/UDP link adds noise, the quoted effective bits at 5 ksps will not transfer to the experiment. This is not a flaw in the analog design, but it makes the headline system-level resolution conditional on an unverified assumption.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper describes the design and characterization of a custom 12-channel DAQ board for the CROSS bolometric neutrinoless-double-beta-decay experiment. Each channel has a 6-pole Bessel-Thomson anti-aliasing filter with 10-bit digitally selectable cutoff from 24 Hz to 2.5 kHz, followed by a dual-channel 24-bit delta-sigma ADC. A commercial FPGA module collects data from 8 boards (96 channels) over 20 MHz SPI and sends it over UDP Ethernet. The measured performance includes the filter transfer function, DC CMRR of about -70 dB, analog noise of 5.7-7.1 uV RMS, effective resolution of 22.0/21.1/19.7 bits at 1/5/25 ksps (corresponding to 4.7/9.2/24 uV RMS), and temperature drifts of 10 uV/C and 10 ppm/C for offset and gain. The authors state that the full multi-board backpanel is still to be designed and that multi-board operation at full data rate has not yet been tested.","tokens_in":3853,"tokens_out":5374,"duration_ms":51871,"significance":"If the reported single-board performance transfers to the final system, the board meets CROSS's requirement for continuous, high-resolution digitization at 5 ksps with 12 channels per board, and it offers a useful design reference for other bolometric experiments. The strengths of the work are that the central figures come from direct measurements against external instruments (spectrum analyzer, climatic chamber) and involve no fitted parameters or circular self-calibration. The analog filter design and the temperature-stability measurements are concrete and reproducible. However, the headline effective-resolution numbers are presented without a stated full-scale range or measurement statistics, and the system-level claim in the title/abstract goes beyond what has actually been measured: only single-board operation with a provisional backpanel is characterized.","major_comments":[{"comment":"The central performance claim is the effective resolution (22.0/21.1/19.7 bits at 1/5/25 ksps, corresponding to 4.7/9.2/24 uV RMS), but the input full-scale range is never stated. Effective resolution in bits is a ratio of full-scale range to RMS noise, and the quoted numbers imply a full-scale range of roughly 20 V_pp (approximately +/-10 V). Please state explicitly the full-scale input range, the formula used for effective bits, and the bandwidth over which the RMS noise values are computed; without this, the headline numbers cannot be reproduced or compared with other systems.","section":"Section 3, 'Board performance'"},{"comment":"The title and abstract describe a digitization system spanning 8 boards per FPGA and UDP transfer at up to 768 Mbps, but all quantitative performance figures come from first sample boards read out through a provisional backpanel. Section 4 states that the full backpanel 'will be designed' and that multi-board operation at full data rate is future work. No crosstalk measurement, simultaneous-channel noise measurement, or end-to-end SPI/UDP data-rate test is reported. The abstract and conclusions should therefore be explicitly scoped as single-board characterization, with the multi-board data-rate path stated as an untested assumption; otherwise the system-level resolution claim rests on the unverified premise that the FPGA/UDP readout adds no additional noise or crosstalk.","section":"Section 4, 'Conclusions and future developments'"},{"comment":"No measurement statistics are provided for the central figures: the number of boards or channels characterized, the number of repeated acquisitions, or the channel-to-channel spread in effective resolution, CMRR, or temperature drift. The reported values are single numbers with no uncertainty or spread, which makes it difficult to judge whether the performance is representative. Please report at least the sample size and the observed spread across channels for the effective resolution at 5 ksps, the operating point most relevant to CROSS.","section":"Section 3, Table 1 and effective-resolution paragraph"}],"minor_comments":[{"comment":"The abstract says 'effective resolution of 21 bits at the typical sample rate' while Section 3 reports 21.1 bits; please align the rounding or state the values consistently.","section":"Abstract and Section 3"},{"comment":"There is a typographical double period in 'Fig.. 3 shows'; also, the caption of Figure 3 could state the cutoff-frequency range and the digital trimmer resolution so the reader does not have to search the text.","section":"Section 2, Figure 3"},{"comment":"The analog noise values in Figure 7 are quoted over a 0.1 Hz-100 kHz bandwidth, while digitized data at 5 ksps necessarily covers a narrower Nyquist band; please clarify the measurement bandwidth for each curve so that the comparison between analog and digitized noise is meaningful.","section":"Section 3, Figure 7"},{"comment":"The claim that the board improves on commercial solutions in 'noise, stability and power consumption' is not supported by any quantitative comparison or citation in the manuscript; either add the comparison or soften the claim.","section":"Section 4"},{"comment":"The description of the Ethernet link as 'optically decoupled' is unclear because a standard 1 Gbps Ethernet PHY is not normally optically decoupled; please clarify the actual galvanic-isolation scheme between the FPGA/backpanel and the storage system.","section":"Section 2, back-end description"}],"recommendation":"major_revision","confidential_remarks":"This is a credible instrumentation paper with an honest statement of remaining work, and the measured single-board performance is plausible. The main issue is that the paper must explicitly define the full-scale range and bit-counting convention, and it must scope the 'system' claim to the single-board measurements. These are fixable within the manuscript's scope, so I recommend major revision rather than rejection. I saw no circular reasoning or inflated calibration; the measurements are direct with external instruments."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"You should know this is a straightforward hardware paper, not a physics result. It describes a 12-channel DAQ board for the CROSS bolometric experiment, with 24-bit delta-sigma ADCs and a digitally programmable 6-pole Bessel-Thomson filter. The measurements are direct and credible: transfer functions from a spectrum analyzer, CMRR, analog noise spectra, and effective resolution from digitized data. The effective resolution numbers (22.0 bits at 1 ksps, 21.1 at 5 ksps, 19.7 at 25 ksps) line up with the reported RMS noise and the ADC's expected behavior. Temperature stability (10 uV/C offset, 10 ppm/C gain) is a nice extra.\n\nWhat is new is not any single component but the integration: 12 channels per board, 10-bit cutoff selection from 24 Hz to 2.5 kHz for fast scintillating bolometers, and an FPGA/UDP readout path designed for scalability. The paper is honest about what is tested and what is not. Section 4 explicitly says the full backpanel 'will be designed' and that qualification at full data rate with multiple boards is future work. So the stress-test concern about multi-board noise is real, but the paper does not overclaim it: the resolution values are presented as single-board results.\n\nSoft spots: no error bars on any measurement, which is typical for this kind of paper but still limits comparisons. The input full-scale range is unstated, so you can't easily convert microvolts RMS to ppm of full scale. The claim of 'many improvements over widely used commercial solutions' is asserted without a quantitative baseline, which is a minor sin. Also, the tests are on 'first samples,' so board-to-board variation is unknown. None of this undermines the central single-board result.\n\nWho it is for: people designing DAQ for low-temperature detectors, and CROSS collaborators. It is a competent contribution to a niche literature and deserves a serious referee; the measurements are reproducible and the design is clearly documented. I would accept it for peer review without hesitation. If the journal allows, I would ask the authors to add error bars, specify the input full-scale range, and soften the comparison to commercial systems until the side-by-side test they mention actually happens.","headline":"A credible, well-scoped characterization of a custom 12-channel DAQ board for bolometric experiments; the headline resolution numbers are real for single boards, but system-level claims are honestly deferred.","tokens_in":4282,"tokens_out":1661,"would_cite":false,"duration_ms":15544,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A custom 12-channel digitizer board for the CROSS bolometer experiment reaches an effective resolution of 22.0 bits at 1 ksps, 21.1 bits at 5 ksps, and 19.7 bits at 25 ksps, corresponding to 4.7 µV, 9.2 µV, and 24 µV RMS input noise.","keywords":["data acquisition system","high resolution digitization","bolometric experiment","neutrinoless double-beta decay","anti-aliasing filter","delta-sigma ADC","FPGA readout","UDP data transfer"],"falsifier":"Assemble the final backplane with eight DAQ boards and one FPGA, digitize all 96 channels at 5 ksps continuously while transferring the full UDP data stream to a storage server, and measure each channel's input-referred noise; if the effective resolution drops below roughly 20 bits or data packets are lost at the full rate, the scalability and performance claims for the complete system fail.","tokens_in":3493,"feed_emoji":"📡","tokens_out":10915,"duration_ms":85186,"temperature":0.7,"pith_summary":"This paper reports the design and measured performance of a custom 12-channel digitizer board for the CROSS bolometric experiment, which searches for neutrinoless double-beta decay. The central result is a measured effective resolution of 22.0 bits at 1 ksps, 21.1 bits at 5 ksps, and 19.7 bits at 25 ksps, corresponding to 4.7 µV, 9.2 µV, and 24 µV RMS noise respectively. At the experiment's typical 5 ksps rate this exceeds the ~20-bit target, and the board's anti-aliasing filter cutoff can be digitally set from 24 Hz to 2.5 kHz for each detector. With one FPGA collecting 96 channels from eight boards and sending data over Ethernet via UDP, the system scales to the full experiment. If the bench performance carries over, CROSS can run continuous high-resolution acquisition with the speed and pulse-shape discrimination its physics requires.","feed_headline":"Custom digitizer board hits 21.1-bit resolution at 5 ksps for CROSS","feed_subtitle":"Measured 9.2 µV RMS noise at the experiment's sample rate; 12 channels per board, 96 per FPGA.","key_machinery":"The load-bearing element is the per-channel signal chain on each 12-channel board: a buffered input that can be grounded for offset self-calibration, a 6-pole Bessel-Thomson anti-aliasing filter whose cutoff frequency is set by a 10-bit digital trimmer over 24 Hz to 2.5 kHz, a conversion to differential, and a dual-channel 24-bit delta-sigma ADC. The tunable filter is what allows one board design to serve both slow and fast bolometers, and the delta-sigma ADC is what provides the high effective resolution at the low sample rates used. The back end, a commercial FPGA module that reads six 20 MHz SPI lines and transmits via synthesized UDP over Ethernet, is the mechanism that scales the 12-channel board to 96 channels per FPGA.","core_discovery":"The central discovery is that a DAQ board combining a low-noise analog front end, a 6-pole Bessel-Thomson anti-aliasing filter with a 10-bit digitally selectable cutoff (24 Hz to 2.5 kHz), and 24-bit delta-sigma ADCs reaches an effective resolution of 22.0 bits at 1 ksps, 21.1 bits at 5 ksps, and 19.7 bits at 25 ksps, or 4.7 µV, 9.2 µV, and 24 µV RMS input noise. Above 5 ksps the resolution is dominated by the ADC and its buffer; the analog section alone contributes 5.7–7.1 µV RMS. The board reads out in both analog and digital modes, and in the digital mode an FPGA collects eight boards (96 channels) over 20 MHz SPI lines and forwards the data over 1 Gbps Ethernet using a hardware-synthesized UDP protocol. The measured offset drift is 10 µV/°C and gain drift 10 ppm/°C, meeting the stability needs of a long-running underground experiment.","pith_inferences":["Because the noise above 5 ksps is dominated by the ADC stage, a lower sampling rate than 1 ksps may push effective resolution beyond 22 bits, which could benefit other precision measurements with very slow signals.","The same board architecture, if ported or reproduced, would likely satisfy the DAQ needs of other bolometric double-beta experiments that require continuous acquisition and per-channel filter tuning.","The paper's single-board characterization leaves open whether the FPGA and UDP link add digital noise or packet loss at full load; a natural test extension is to compare the reconstructed noise spectrum with and without the Ethernet link active.","The offset self-calibration via grounded inputs suggests the board could self-correct long-term drifts in hardware, a feature that might remove the need for frequent baseline calibrations in a multi-year run."],"forward_implications":["CROSS can run continuous acquisition at 5 ksps per channel with effective resolution above 21 bits, meeting the noise and pile-up requirements for pulse-shape discrimination.","One FPGA handles eight boards (96 channels), so the full detector array can be read out with a small number of standard Ethernet links.","The digitally selectable filter cutoff lets the same board be tuned per detector, from 24 Hz for slow bolometers to 2.5 kHz for fast scintillating ones.","In 6-channel mode the same hardware digitizes at 250 ksps per channel, making the board usable for faster-signal applications without change."],"supporting_citations":[{"why":"Defines the CROSS experiment and its DAQ requirements (sampling rate, resolution, continuous acquisition) that the board is built to meet.","marker":"[1]"},{"why":"Provides the CUORE baseline bolometric DAQ approach that this system is designed to improve on in speed and resolution.","marker":"[2]"},{"why":"Documents CUPID-0, another 0νββ experiment whose DAQ requirements motivate the board's higher sample rate and pile-up capability.","marker":"[4]"}],"fun_headline_variants":["CROSS digitizer: 22-bit at 1 ksps, 21.1 at 5 ksps","CROSS DAQ board: 21.1 bits, 9.2 µV RMS noise at 5 ksps","CROSS readout: 12 channels, 24-bit ADCs, 19.7 bits at 25 ksps","CROSS custom digitizer: 4.7 µV noise at 1 ksps, 21.1 at 5 ksps","CROSS FPGA collects 96 channels, 21.1-bit resolution at 5 ksps"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The measured resolution was obtained on first sample boards in a lab test with direct FPGA readout, and the full multi-board system streaming 96 channels through the UDP Ethernet link has not yet been built, so the claimed performance must carry over from the single board to the complete configuration.","fun_headline_variants_meta":{"raw":{"variants":["CROSS digitizer: 22-bit at 1 ksps, 21.1 at 5 ksps","CROSS DAQ board: 21.1 bits, 9.2 µV RMS noise at 5 ksps","CROSS readout: 12 channels, 24-bit ADCs, 19.7 bits at 25 ksps","CROSS custom digitizer: 4.7 µV noise at 1 ksps, 21.1 at 5 ksps","CROSS FPGA collects 96 channels, 21.1-bit resolution at 5 ksps"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000376,"raw_usage":{"total_tokens":2024,"prompt_tokens":984,"completion_tokens":1040,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":600,"completion_tokens_details":{"reasoning_tokens":894}},"tokens_in":600,"tokens_out":1040,"duration_ms":7922,"temperature":1.0,"reasoning_tokens":894,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T10:20:02.708033+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Assemble the final backplane with eight DAQ boards and one FPGA, digitize all 96 channels at 5 ksps continuously while transferring the full UDP data stream to a storage server, and measure each channel's input-referred noise; if the effective resolution drops below roughly 20 bits or data packets are lost at the full rate, the scalability and performance claims for the complete system fail.","supporting_citations":[{"cited_title":"The $0\\nu2\\beta$-decay CROSS experiment: preliminary results and prospects","cited_arxiv_id":"1906.10233","evidence_quote":"Defines the CROSS experiment and its DAQ requirements (sampling rate, resolution, continuous acquisition) that the board is built to meet."},{"cited_title":"Alduino, First Results from CUORE: A Search for Lepton Number Violation via 0 Decay of ^ 130 Te , Phys","cited_arxiv_id":null,"evidence_quote":"Provides the CUORE baseline bolometric DAQ approach that this system is designed to improve on in speed and resolution."}],"review_version":1}