{"id":"a4ee53e2-9a53-4875-b49e-bb9be294d8c8","arxiv_id":"1909.13622","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"On-chip spiral inductors built by shunting CMOS metal layers in parallel measured above 250 nH and powered 30 MHz open-loop buck converters at 69.1% peak efficiency under light load.","lead":"This paper designs and fabricates large-value on-chip spiral inductors in a standard bulk CMOS process, reaching about 250 nanohenries, and uses them in two 30 MHz DC-DC buck converters. A generalist might read it because it tests whether fully integrated power conversion, without off-chip magnets or special post-processing, is practical for system-on-chip products.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Abstract and Table IV claim 69.1% converter efficiency was measured, but the body only reports post-layout simulation efficiency for the converters; no measured converter data appear in Section IV.","rationale":"The paper contains a genuine and well-documented inductor characterization: the 260 nH on-chip spiral measured from 5 MHz to 50 MHz, with Q around 4 at 30 MHz, is a useful applied data point. Credit is due for the shunted-metal-layer design and for feeding measured inductor parameters back into the converter simulation. The load-bearing problem is not the inductor work but the converter efficiency claim. The abstract says the 69.1% peak efficiency 'was measured,' yet the body's Section IV-C is explicitly titled 'Post layout simulation results of power stages' and Tables II and III are labeled POST-SIMULATION. No measured converter efficiency, output voltage, or load-current table appears anywhere in the provided text. This is an internal inconsistency between the abstract/conclusion and the body, and it directly affects the paper's central claim and its benchmark comparison in Table IV. The reader's stated weakest assumption was the same-rail LDR comparison, which is a valid secondary concern, but the more fundamental issue is that the headline efficiency number has not been shown to be measured at all. Because the reader's CONDITIONAL verdict already requires measured efficiency data, my analysis reinforces that condition rather than changing the verdict; if no such data are provided, the central claim should be treated as unverified.","tokens_in":5950,"tokens_out":3696,"duration_ms":39511,"concrete_test":"Inspect the full manuscript for any measured efficiency plot, oscilloscope capture, or measured Vout/Iout table for the two converters. The decisive check: locate the measured efficiency versus load-current data (or a measured waveform) for the converter with the active diode. If Tables II–III are the only efficiency data and are captioned 'POST-SIMULATION', then the abstract's 'peak efficiency was measured to be 69.1%' is unsupported; the claim would be restored only by a hardware measurement at Rload = 100 ohm agreeing with the simulated 69.06% within a few percentage points.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claim—69.1% peak efficiency at 12.9 mA and the Table IV comparison built on it—is presented in the abstract and conclusion as 'measured,' but the body reports no measured converter efficiency. Section IV is organized as IV-A setups, IV-B 'Characterization of on-chip inductors,' and IV-C 'Post layout simulation results of power stages'; Tables II and III are explicitly labeled POST-SIMULATION, and Fig. 11 is described as a comparison of simulated converters with an LDR. The only measured data reported are inductor L, R, Cs, Rs, fres, and Q from LCR/VNA. The sentence 'The converter with the off-chip passive diode was measured to deliver a larger output current...' appears under the 'Post layout simulation' heading and is contradicted by the table labels. Therefore the headline efficiency is a simulation result that was loaded with measured inductor parasitics, not a measured system efficiency. This is load-bearing because the abstract's first and last sentences, the conclusion, and Table IV's EEF comparison all depend on 69.1% being an experimental demonstration. If no measured converter data exist, the paper claims an experimental result it does not report.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper designs on-chip spiral inductors in a bulk 0.18 μm CMOS process by shunting metal layers in parallel, reports measured inductance above 250 nH over a wide frequency range with Q around 4 at 30 MHz, and employs these inductors in two open-loop 30 MHz buck converters, one with an off-chip passive diode and one with an on-chip active diode. The abstract and conclusion claim a measured peak efficiency of 69.1% at 12.9 mA load, and the paper compares the converters with an equivalent low-dropout regulator using an Efficiency Enhancement Factor figure of merit.","tokens_in":6128,"tokens_out":3096,"duration_ms":31594,"significance":"If the claimed measured system efficiency were fully supported, the work would be a useful data point for fully integrated DC-DC converters in a standard CMOS process, demonstrating that multi-nH on-chip inductors with Q around 4 can operate at 30 MHz and achieve competitive efficiency and EEF. The paper's strengths are the direct measurement of inductor L, R, Cs, Rs, resonant frequency, and Q from 1 kHz to 50 MHz, and the explicit reporting of simulation tables and layouts. However, the central efficiency claim is presented in the abstract as measured while the body only reports post-layout simulation efficiency, so the significance as an experimental demonstration is currently overstated.","major_comments":[{"comment":"The abstract states that the peak converter efficiency 'was measured to be 69.1%', and the conclusion repeats this as a measured result, but Section IV-C is explicitly titled 'Post layout simulation results of power stages' and Tables II and III are labeled 'POST-SIMULATION'. No measured converter efficiency, output voltage, or load current appears anywhere in Section IV; the only measured data are for the inductors. The sentence in Section IV-C claiming that the converter with the off-chip passive diode 'was measured to deliver a larger output current' appears under the post-layout simulation heading, which is internally contradictory. This is load-bearing because the abstract, the conclusion, and Table IV's efficiency and EEF comparison all depend on 69.1% being an experimentally observed value. Please either provide the measured converter efficiency data or explicitly and consistently recast the efficiency claim as a post-layout simulation result.","section":"Abstract and Section IV-C"},{"comment":"The efficiency comparison with the low-dropout regulator (LDR) in Fig. 11 and the EEF comparison in Table IV assume that the converters and the LDR deliver the same regulated output voltage. However, the converters are open-loop, and Tables II and III show Vout varying from 0.807 V to 1.295 V for the active-diode converter and from 1.091 V to 1.550 V for the discrete-diode converter across load resistances of 30 to 100 Ω. The peak efficiency of 69.1% occurs at Vout = 1.295 V, not at the nominal 1.2 V listed in Table IV. If the LDR comparison is not made at the same output voltage and conversion ratio, the claimed efficiency advantage and EEF are biased. Please specify the output voltage of the LDR and the conversion ratio used in each comparison, or restrict the comparison to operating points with equal output voltages.","section":"Section IV-C, Fig. 11, and Table IV"},{"comment":"Equation (4) states that the equivalent quality factor of two parallel coupled inductors can be approximated as Qeq ≈ Q1 + Q2. For two identical inductors with L1 = L2 = L and R1 = R2 = R, the exact parallel combination gives Qeq = ω(L+M)/R = Q(1+k), where k is the coupling coefficient, so Qeq ≈ Q1 + Q2 only when k is close to 1. The condition under which this approximation holds is not stated, and the later Q measurements do not isolate the benefit of shunting from other layout effects. Please state the assumed coupling coefficient or replace the approximation with the exact expression in Eq. (3).","section":"Section II.A, Eq. (4)"}],"minor_comments":[{"comment":"The abstract says the measured inductance is 'more than 250 nH', the conclusion says 'higher than 240 nH', and Section IV-B reports values 'around 260 nH' peaking at 269 nH. Please use one consistent number.","section":"Abstract and Section V"},{"comment":"The text says 'Fig. 8 shows the measured inductance' and then refers to measured Cs1, Cs2, Rs1, and Rs2, but Fig. 8 shows the measurement setup and Fig. 9 shows the measured parameter plots. The figure references appear to be off by one.","section":"Section IV.B"},{"comment":"The column 'Ig' is not defined in the text or table caption; please define it (presumably the input or supply current).","section":"Tables II and III"},{"comment":"The Efficiency Enhancement Factor (EEF) is used as a figure of merit but no formula or reference for it is given; please define EEF explicitly.","section":"Section V and Table IV"},{"comment":"The terms 'LDR' and 'low dropout regulator' are used; the standard acronym is LDO. Please clarify whether the comparison is with an ideal linear regulator or a specific implemented regulator.","section":"Section IV.C"}],"recommendation":"major_revision","confidential_remarks":"The main issue is that the abstract and conclusion overstate the experimental basis for the 69.1% efficiency claim; the body only presents post-layout simulation results for the converters. If the authors have measured converter data, they should add them; if they do not, the claims must be recast as simulation-based, which would substantially reduce the novelty of the efficiency comparison. The inductor measurements themselves appear solid and are the more defensible contribution."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Two things to know before you read it. The measured on-chip inductor result is real and useful: roughly 260 nH at 30 MHz, Q around 4, in a standard 0.18 um bulk CMOS process with no post-processing. The paper's second headline claim, however, does not hold up: the 69.1% peak converter efficiency is a post-layout simulation, not a measurement, despite the abstract and conclusion saying it was measured.\n\nThe inductor work gets credit. The design procedure, parallel shunting of metal layers, and the measured L, R, Cs, Rs, fres, and Q are internally consistent. The >250 nH claim is credible from the measured data, and this is a genuinely new data point for fully integrated DC-DC converters. The active diode is a known circuit properly cited from the authors' prior work, and there is no circularity.\n\nThe soft spots are concentrated in the converter section. Section IV-C is explicitly labeled 'Post layout simulation results of power stages,' and Tables II and III are marked POST-SIMULATION. The only sentence that says a converter 'was measured' appears under that same heading and conflicts with the table labels. So the abstract's first and last sentences, the conclusion, and Table IV's EEF comparison all rest on a simulation result presented as an experimental demonstration. That is load-bearing, and it needs to be fixed by either reporting measured converter results or revising the language. Also, the LDR comparison in Fig. 11 is not same-rail: the open-loop converters produce Vout from 0.81 V to 1.55 V, so the claimed efficiency advantage and EEF are biased. Minor: the reported inductance value varies between 240 nH (Table IV), 250 nH (abstract), and 260-269 nH (body). It should be one number.\n\nWho is this for? Practitioners designing on-chip power inductors in bulk CMOS. The measured inductor data are worth having. The converter efficiency demonstration is not, as reported, a measured result. I would send it to peer review, but with a clear request for measured converter data or a revision that correctly labels the efficiency as simulation-only.\n\nFor your own work: cite the inductor measurement, not the efficiency.","headline":"Useful measured 260 nH on-chip inductor data; the headline 69.1% converter efficiency is a post-layout simulation presented as measurement.","tokens_in":6671,"tokens_out":2992,"would_cite":true,"duration_ms":28710,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"On-chip shunted metal spirals exceed 250 nH and drive a buck converter to 69% efficiency.","keywords":["on-chip inductor","fully integrated DC-DC converter","active diode","shunt metal layers","spiral inductor","quality factor","buck converter","efficiency enhancement"],"falsifier":"Re-measure both open-loop converters and a linear regulator at identical output voltage and load current for every point of the efficiency comparison; if the buck converters no longer exceed the linear regulator's efficiency, the claimed enhancement factor comes from the unregulated output rather than from the inductor or active diode. As a second check, measure the inductor quality factor directly at 30 MHz on a fixture that excludes the power stage; if $Q$ is well below 4, the reported efficiency cannot be attributed to the modeled inductor.","tokens_in":5712,"feed_emoji":"⚡","tokens_out":13599,"duration_ms":119560,"temperature":0.7,"pith_summary":"This paper sets out to show that a useful power inductor, one with inductance above 250 nH and a quality factor near 4 at 30 MHz, can be built in bulk 0.18 µm CMOS using only the metal layers supplied by the process, without post-processing, bond wires, or packaging tricks. The route is to shunt several stacked metal layers in parallel as a spiral, which cuts series resistance and adds mutual inductance. The authors then place such an inductor in two open-loop 30 MHz buck converters, one with an off-chip passive diode and one with an on-chip active diode, and measure a peak efficiency of 69.1% at a light load of 12.9 mA. If the claims hold, the design chain from inductor model to layout to converter measurement is validated, moving fully integrated DC-DC conversion closer to cheap standard CMOS.","feed_headline":"Shunted on-chip spirals top 250 nH; buck hits 69%","feed_subtitle":"Parallel metal layers in ordinary CMOS can replace bulky discrete inductors in integrated power supplies.","key_machinery":"The load-bearing mechanism is the shunt connection of stacked metal layers in a spiral inductor, the top pair M6/M5 and lower pair M4/M3 in the 0.18 µm process, joined by vias so that series resistances appear in parallel while magnetic mutual inductance is retained. The paper's design formulas for two shunted branches are $R_\\mathrm{eq}=R_1\\|R_2$ and $L_\\mathrm{eq}=(L_1L_2-M^2)/(L_1+L_2-2M)$ with $M=k\\sqrt{L_1L_2}$, giving the approximation $Q_\\mathrm{eq}=\\omega L_\\mathrm{eq}/R_\\mathrm{eq}\\approx Q_1+Q_2$. This is what makes a large inductance with only moderate loss plausible in a 2 mm by 2 mm footprint. The second mechanism is the active diode: a comparator-controlled NMOS switch that conducts only when the anode is above the cathode, lowering the rectifier voltage drop and reverse-conduction loss compared with a passive diode.","core_discovery":"The central discovery claimed is that shunting metal layers in parallel in a bulk 0.18 µm CMOS process produces on-chip spiral inductors with measured inductance above 250 nH over a wide frequency range, peaking at 269 nH near 35 MHz, with self-resonant frequencies above 105 MHz and quality factor $Q$ around 4 at the 30 MHz switching frequency. The same die carries two open-loop buck converters designed for 2.4 V to 1.2 V conversion; the version with an on-chip active diode is reported to be about 6% more efficient than the version with an off-chip passive diode, reaching 69.1% peak efficiency at 12.9 mA load. The paper presents this as validating the simulation results and as an efficiency-enhancement factor of 27.6% relative to a linear regulator, using the highest on-chip inductance among the converters compared.","pith_inferences":["The shunting rule $Q_\\mathrm{eq}\\approx Q_1+Q_2$ implies that adding more parallel metal layers should keep improving the quality factor until substrate eddy-current loss and inter-layer capacitance take over, so the technique has a natural scaling limit worth testing in a process with more metal levels.","The open-loop outputs drift with load; a closed-loop version that keeps the output at a fixed 1.2 V would settle whether the efficiency advantage over linear regulation survives the regulation requirement.","With self-resonance only about three times the switching frequency, designs aiming at higher inductance or smaller area will push resonance down toward the switching frequency; a useful extension would map the efficiency-versus-$L/f_\\mathrm{res}$ trade-off explicitly.","A loss breakdown separating inductor copper loss, substrate eddy-current loss, switching loss, and active-diode loss would show where the remaining roughly 31% of input power goes and would identify which mechanism most limits further efficiency gains."],"forward_implications":["A usable power inductor above 250 nH can be made in plain bulk CMOS, allowing an inductive buck converter and its load to share a die without thick-metal post-processing, bond wires, or packaging inductors.","The measured self-resonant frequency above 105 MHz leaves enough margin for the 30 MHz switching frequency, so the inductor is not operating near its resonance.","Replacing the off-chip passive diode with the on-chip active diode is reported to raise efficiency by about 6%, supporting comparator-controlled rectification in integrated power stages.","At light loads the active-diode converter reaches 69.1% efficiency, corresponding to an efficiency-enhancement factor of 27.6% over a linear regulator under the comparison conditions used in the paper."],"supporting_citations":[{"why":"supplies the starting lumped two-port model of the planar spiral inductor that the paper extends with substrate loss terms.","marker":"[10]"},{"why":"identifies substrate and eddy-current losses in low-resistivity silicon that motivate the shunted-layer design and the added coupled-coil model.","marker":"[11]"},{"why":"provides the comparator-controlled active diode circuit adopted in the second buck converter.","marker":"[14]"},{"why":"serves as the prior fully on-chip inductor converter baseline in the efficiency and area comparison table.","marker":"[7]"},{"why":"serves as the high-efficiency bond-wire inductor baseline in the comparison table.","marker":"[9]"},{"why":"serves as the packaging-inductor baseline against which the efficiency-enhancement factor is compared.","marker":"[13]"}],"fun_headline_variants":["On-chip inductors in CMOS exceed 250 nH","Shunted metals give >250 nH inductors on chip","Active diode lifts buck efficiency to 69.1%","269 nH peak from shunted CMOS inductors","Bulk CMOS inductors enable 69% efficient buck"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The efficiency comparison against a linear regulator, including the 27.6% enhancement factor, assumes the open-loop buck converters deliver the same regulated output voltage as the linear regulator at each comparison point, but the measured outputs drift from 0.81 V to 1.55 V across load, so the comparison is fair only if the regulator is held to those varying outputs.","fun_headline_variants_meta":{"raw":{"variants":["On-chip inductors in CMOS exceed 250 nH","Shunted metals give >250 nH inductors on chip","Active diode lifts buck efficiency to 69.1%","269 nH peak from shunted CMOS inductors","Bulk CMOS inductors enable 69% efficient buck"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000564,"raw_usage":{"total_tokens":2643,"prompt_tokens":881,"completion_tokens":1762,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":497,"completion_tokens_details":{"reasoning_tokens":1681}},"tokens_in":497,"tokens_out":1762,"duration_ms":12516,"temperature":1.0,"reasoning_tokens":1681,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T12:19:40.285066+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-measure both open-loop converters and a linear regulator at identical output voltage and load current for every point of the efficiency comparison; if the buck converters no longer exceed the linear regulator's efficiency, the claimed enhancement factor comes from the unregulated output rather than from the inductor or active diode. As a second check, measure the inductor quality factor directly at 30 MHz on a fixture that excludes the power stage; if $Q$ is well below 4, the reported efficiency cannot be attributed to the modeled inductor.","supporting_citations":[{"cited_title":"A physical model for planar spiral inductors on silicon ,","cited_arxiv_id":null,"evidence_quote":"supplies the starting lumped two-port model of the planar spiral inductor that the paper extends with substrate loss terms."},{"cited_title":"Design considerations for extremely high-Q integrated inductors and their application in CMOS RF power amplifier,","cited_arxiv_id":null,"evidence_quote":"identifies substrate and eddy-current losses in low-resistivity silicon that motivate the shunted-layer design and the added coupled-coil model."},{"cited_title":"Integrated low-loss CMOS active rectifier for wirelessly powered devices,","cited_arxiv_id":null,"evidence_quote":"provides the comparator-controlled active diode circuit adopted in the second buck converter."},{"cited_title":"Improved on -chip components for integrated DC -DC converters in 0.13 µ m CMOS ,","cited_arxiv_id":null,"evidence_quote":"serves as the prior fully on-chip inductor converter baseline in the efficiency and area comparison table."},{"cited_title":"An 84.7% efficiency 100 -MHz package bondwire-based fully integrated buck converter with precise DCM operation and enhanced light -load efficiency","cited_arxiv_id":null,"evidence_quote":"serves as the high-efficiency bond-wire inductor baseline in the comparison table."},{"cited_title":"50 MHz dual-mode buck DC-DC converter,","cited_arxiv_id":null,"evidence_quote":"serves as the packaging-inductor baseline against which the efficiency-enhancement factor is compared."}],"review_version":1}