{"id":"481abcb2-5def-4b45-bc28-c17dddba6bf8","arxiv_id":"2411.10990","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"A double-chase grey wolf optimizer for approximate logic synthesis reduces critical path delay by an average of 27-38% on benchmark circuits under error constraints, beating prior ALS methods.","lead":"This paper proposes a timing-driven approximate logic synthesis framework that uses a double-chase grey wolf optimizer to select local logic substitutions reducing critical path delay and area under error constraints. The authors report average critical path delay reductions of 27.13% and 38.54% on benchmark circuits compared with prior methods, but the results come from hyperparameters tuned on the same benchmarks.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The optimizer selects circuits by pre-sizing depth/area fitness (Eq. 8), but the headline metric is post-sizing CPD; no evidence that the pre-sizing Pareto ordering is preserved after drive-strength enhancement, so the claimed maximum delay reduction is not established.","rationale":"The reader's weakest assumption identifies exactly the load-bearing gap: the pre-sizing fitness ranking in Eq. (8) must be preserved after Section III-C sizing for the optimizer's choice to be the best post-sizing circuit. My reading of the paper confirms this is the least secure link in the central claim, because the final reported metric is not the quantity being optimized and the paper supplies no evidence of monotonicity or correlation. The absence of multiple seeds and the in-sample tuning of wd are additional concerns, but they are secondary; the post-sizing mismatch directly attacks the meaning of 'maximum critical path delay reduction.' Since the reader already returned CONDITIONAL and this concern supports rather than overturns that verdict, no adjustment is needed.","tokens_in":11573,"tokens_out":9012,"duration_ms":112146,"concrete_test":"Rerun the DCGWO flow on the Table II and Table III benchmarks, but at the final iteration perform the Section III-C post-optimization on every non-dominated candidate (or at least the top-K candidates by Eq. (8)) instead of only the leader. Compare the post-sizing CPD of the leader with the minimum over all evaluated candidates. If a non-leader candidate yields a lower final CPD by more than a small tolerance (e.g., 1–2%), the surrogate fitness is misaligned with the claimed objective, and the headline reduction is not maximal. A complementary check is to replace the pre-sizing fitness with actual post-sizing CPD in the final selection step and observe whether the reported ratios improve.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claim—average 27.13% and 38.54% post-sizing critical path delay (CPD) reduction—is produced by a pipeline whose search objective is not the reported objective. Equation (8) ranks approximate circuits using only pre-sizing critical-path-depth ratio and pre-sizing area ratio (area of dangling gates removed), while the reported Ratiocpd values are measured after Section III-C gate resizing under an area constraint. The mapping from (Depthapp, Areaapp) to post-sizing CPD is not shown to be monotone: Design Compiler's drive-strength enhancement distributes area slack across remaining gates, and its effect on path delay depends on fanout, load, and which gates lie on the critical path—information that is largely discarded by the fan-in-only adjacency representation. A circuit with slightly worse Eq. (8) fitness but more area slack on critical-path gates can easily have a smaller final CPD after sizing. Thus the statements that the framework 'achieves maximum critical path delay reduction' (Abstract and Conclusion) are not consequences of the optimizer's selection rule; they are unverified assertions. No correlation or ablation between pre-sizing fitness and post-sizing CPD is reported, so the reader cannot tell whether the chosen approximate circuit is actually the best after post-optimization.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a timing-driven approximate logic synthesis (ALS) framework based on a double-chase grey wolf optimizer (DCGWO). Circuits are stored as fan-in adjacency lists, and LACs (wire-by-wire and wire-by-constant) are applied to reduce critical-path depth and area under ER or NMED error constraints. The optimizer ranks circuits with a weighted depth/area fitness function, and a final post-optimization step removes dangling gates and resizes remaining gates under an area constraint to convert area savings into further delay reduction. Experiments on ISCAS-85 and EPFL benchmarks with TSMC 28nm report average critical-path delay reductions of 27.13% under a 5% ER constraint and 38.54% under a 2.44% NMED constraint, claiming improvements over area-driven, depth-driven, and single-chase GWO baselines.","tokens_in":11844,"tokens_out":6739,"duration_ms":79950,"significance":"If the reported results survive re-evaluation, the work would be a practically useful contribution: the double-chase strategy is a plausible way to balance depth and area objectives in ALS, the adjacency-list representation is simple and efficient, and the post-sizing step is a sensible mechanism for converting area slack into timing. The paper also compares against several established baselines and reports runtime. However, the quantitative claims are not yet fully established because the depth weight is tuned on the evaluation benchmarks, the stochastic optimizer is reported without variance, and the optimizer's search objective is not the same as the headline post-sizing delay metric.","major_comments":[{"comment":"The depth weight wd is selected by running the framework on the benchmark circuits used for evaluation and choosing the wd that minimizes the average post-sizing Ratiocpd under the tightest and loosest ER/NMED constraints. This is parameter tuning on the test set, so the headline 27.13% and 38.54% average reductions reported in Tables II and III are not independent estimates. Please fix wd on a validation split or through leave-one-out selection, or report results across a range of wd to show that the main conclusions are robust to this choice.","section":"IV-A, Fig. 6"},{"comment":"DCGWO is stochastic: the initial population is random, target and switch gates are sampled, and the decision parameters D and W involve random values rc and r1. The tables report a single run per circuit with no variance or number of trials. The claimed margins over HEDALS and the other baselines are therefore not statistically grounded. Please report mean and standard deviation (or a box plot) over at least 10 independent seeds, and include a paired significance test against the main baselines.","section":"Tables II and III, Section III-B"},{"comment":"The fitness function in Eq. (8) ranks approximate circuits using pre-sizing depth and area ratios, but the reported metric Ratiocpd = CPDfac/CPDori is measured after Design Compiler drive-strength resizing in Section III-C. The paper gives no evidence that the pre-sizing Pareto ordering is preserved after resizing; post-sizing delay depends on fanout, load, and which gates lie on the critical path, information that is largely absent from the fan-in-only representation. Thus the abstract's claim that the framework achieves 'maximum critical path delay reduction' does not follow from the optimizer's selection rule. Please add an ablation that evaluates all Pareto-front candidates with the full post-sizing flow and reports the rank correlation between Eq. (8) fitness and final Ratiocpd, or modify the final selection to use post-sizing CPD directly.","section":"III-B Eq. (8), III-C"},{"comment":"The 'GWO (single-chase)' baseline is under-specified: the paper does not state which fitness function, which weights, which thresholds, and which stopping criterion this variant uses, nor whether its hyperparameters were tuned in the same way as those of DCGWO. Without this information the comparison is not reproducible and the claimed benefit of the double-chase mechanism cannot be separated from implementation details. Please describe the baseline configuration completely and, ideally, provide the artifact or code for all compared methods.","section":"IV-B, Tables II and III"}],"minor_comments":[{"comment":"The full text contains a leftover LaTeX comment in the abstract ('%based on double-chase grey wolf optimizer (DCGWO).'), which interrupts the sentence; please clean it up.","section":"Abstract"},{"comment":"The weights wt and we are given as numbers (0.9*CPDori, 0.1, 0.2) but the terms 1/Ta and 1/Error have different units and scales; please clarify how these weights are normalized or justified.","section":"Equation (3)"},{"comment":"The empirical parameter b in the asymptotic error constraint relaxation (Error_iter_cons = b*iter^2 + Error0_cons) is not reported; please give the values used for the ER and NMED experiments.","section":"IV-A"},{"comment":"Figure 7 compares only HEDALS and single-chase GWO, not VECBEE-SASIMI or VaACS; please state why those baselines are omitted from the constraint-sweep plots.","section":"Fig. 7"},{"comment":"Reference [14] contains a typo ('Eurpoe') and reference [18] contains a duplicated journal prefix in 'IEEE IEEE Trans. Evol. Comput.'; please correct these.","section":"References"},{"comment":"The term 'critical path depth' is used interchangeably with timing information from PrimeTime; please specify whether Depthapp is a logic level count or a static-timing delay value, since the difference matters for interpreting Eq. (8).","section":"III-B, Eq. (8)"}],"recommendation":"major_revision","confidential_remarks":"The header states that the paper was accepted at DATE 2025; if the submitted manuscript is an extended version of that conference paper, the authors should clarify the additional contribution in the revision. I also recommend asking the authors to provide code or detailed experimental configurations for the baselines, since the reported comparisons are otherwise difficult to verify independently."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThis is a solid but over-claimed ALS paper. The genuinely new thing is the double-chase grey wolf optimizer: the population is split into leader, elite, and omega groups, each with its own chase mechanism. That is a real algorithmic change, and the ablation against single-chase GWO suggests it helps. The adjacency-list representation for LACs is also a reasonable engineering choice, and the paper is commendably clear about the overall flow.\n\nWhat the paper does well: it compares against several strong baselines (VECBEE-SASIMI, VaACS, HEDALS, single-chase GWO) across multiple benchmarks and error/area constraint settings. The sensitivity plots (Fig. 7 and 8) give a consistent picture: the proposed method improves delay beyond the baselines under most constraints. That consistency is evidence that the method has real merit.\n\nThe soft spots are real, and the stress-test note lands. The optimizer ranks circuits by Eq. (8), which uses pre-sizing critical-path depth and area, but the headline Ratiocpd is measured after gate resizing in Section III-C. Nothing in the paper shows that the pre-sizing Pareto order survives resizing. A circuit with slightly worse depth/area could have more slack on critical-path gates and end up faster after drive-strength enhancement. I would not call this fatal—the paper does not claim the proxy is perfect—but the abstract's 'maximum critical path delay reduction' is an assertion, not an established result. A simple correlation plot between Eq. (8) fitness and final post-sizing delay would go a long way.\n\nSecond issue: wd is tuned on the same benchmarks that are later used to report improvement (Fig. 6). That is test-set tuning, even if it is just one parameter. It should be disclosed or justified with a train/test split.\n\nThird: the optimizer is stochastic, but all tables report single runs. No seeds, no variance. For an evolutionary method, that is a real weakness. It also makes the runtime comparisons less meaningful.\n\nNo code or data are released, so independent verification is limited. The benchmark circuits are public, so the results are at least repeatable in principle.\n\nBottom line: this is a worthwhile paper for people working on approximate logic synthesis and metaheuristics for VLSI optimization. It deserves a serious referee, but the central claim needs tightening. I would ask for a validation of the pre-sizing objective, multiple runs, and a clear statement about the tuning of wd before I would trust the headline numbers.\n\nRecommendation: send it to peer review, with expectation of major revision.","headline":"A genuine algorithmic variant with an honest experimental effort, but the core timing claim is weakened by an objective mismatch and in-sample tuning.","tokens_in":12388,"tokens_out":2984,"would_cite":false,"duration_ms":33502,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Approximate logic synthesis gains the most timing when critical-path depth and area are optimized together, and the proposed double-chase grey wolf optimizer with post-sizing reports average critical-path delay reductions of 27.13% at 5%…","keywords":["approximate logic synthesis","grey wolf optimizer","critical path delay","gate sizing","error rate","normalized mean error distance","local approximate changes","timing optimization"],"falsifier":"For any benchmark, enumerate all Pareto-front approximate circuits produced by the optimizer before post-optimization, apply the same dangling-gate deletion and gate-resizing step to each, and check whether the circuit selected by the pre-sizing fitness function has the smallest post-sizing critical path delay; a single counterexample where another Pareto candidate is faster after resizing would falsify the claim that the optimizer's choice yields the maximum delay reduction.","tokens_in":11370,"feed_emoji":"⚡","tokens_out":7803,"duration_ms":77648,"temperature":0.7,"pith_summary":"This paper argues that approximate logic synthesis should optimize critical path depth and area simultaneously, because depth-only methods leave area savings on the table and area-only methods rarely shorten the critical path. It introduces a double-chase grey wolf optimizer that explores local approximate changes (replacing wires or setting wires to constants) while tracking both depth and area, then converts the accumulated area reduction into stronger drive-strength gates, cutting delay further. On 28nm benchmarks, the framework claims average critical path delay reductions of 27.13% under a 5% error-rate constraint and 38.54% under a 2.44% normalized-mean-error-distance constraint, exceeding prior depth-driven, area-driven, and single-chase baselines with comparable runtime. If correct, the recipe makes approximation a timing tool rather than just an area or power tool.","feed_headline":"Approximate circuits get 27% faster with double-chase search","feed_subtitle":"Simultaneous depth and area search beats single-objective approximation; 28nm tests show 27–39% delay cuts.","key_machinery":"The central object is the double-chase grey wolf optimizer (DCGWO), an extension of the grey wolf optimizer in which the approximate-circuit population is split into a leader, three elite circuits, and an omega group. The leader guides the elites in Chase 1, and the elites guide the omegas in Chase 2; each chase alternates between circuit searching (applying wire-by-wire or wire-by-constant local changes on sampled critical-path gates, choosing replacement gates by output similarity) and circuit reproduction (recombining high-scoring primary-output transitive-fanin pairs from two parents). Fitness combines the critical-path-depth ratio and the area ratio, and a quadratic scheme gradually relaxes the error constraint across iterations. The companion mechanism is post-optimization: deletion of dangling gates followed by area-constrained gate resizing, which converts the accumulated area reduction into reduced critical path delay.","core_discovery":"Existing timing-driven approximate logic synthesis methods pick approximate changes by either critical-path depth or area alone, so they miss the best final timing. The paper's central claim is that the right objective is a weighted combination of critical-path-depth ratio and area ratio during search, and that a hierarchical 'double-chase' grey wolf optimizer can explore this two-objective space more effectively than greedy, genetic, or single-chase methods. The chosen approximate circuit is then passed through post-optimization that deletes dangling gates and resizes remaining gates under an area constraint, turning area saved by approximation into drive-strength enhancement on critical paths. The reported outcome is a maximum average critical path delay reduction (27.13% under an error-rate constraint of 5%, and 38.54% under a normalized-mean-error-distance constraint of 2.44%) at the same error and area constraints as the compared methods.","pith_inferences":["A testable extension is to make the error-constraint relaxation schedule circuit-adaptive; the fixed quadratic scheme may leave unexplored depth-area pairs on circuits with very different error tolerances.","Because final delay comes from drive-strength resizing, the depth/area weight (wd=0.8) should be recalibrated per cell library; on libraries with a different area-to-delay mapping, the same fitness ranking may not maximize post-sizing delay.","The fan-in adjacency representation discards wire and parasitic information, so the reported gains are likely best on gate-delay-dominated designs; adding wire-aware delay estimates would test how far the result carries to interconnect-dominated circuits."],"forward_implications":["Depth and area should be treated as simultaneous objectives during approximate search, since depth-only approximation leaves area savings that could be spent on drive strength, and area-only approximation rarely shortens the critical path.","Area reduction created by approximation is a timing resource: after dangling-gate deletion, the saved area can be invested in resizing critical-path gates for lower delay.","The hierarchical double-chase population produces smaller final delay ratios than single-chase grey wolf optimization within the same iteration budget.","The reported benefit persists across error budgets and area constraints, ranging from 1% to 5% error rate, 0.48% to 2.44% normalized mean error distance, and 0.8x to 1.2x area settings.","Runtime stays competitive because the fan-in adjacency representation makes local approximate changes cheap to apply and the population-based search parallelizes."],"supporting_citations":[{"why":"Depth-driven baseline whose critical-error-graph selection is the central timing competitor.","marker":"[6]"},{"why":"Area-driven baseline and fast Monte-Carlo error and similarity estimator used in evaluation.","marker":"[9]"},{"why":"Genetic ALS baseline that reports timing under variability and is compared on final delay.","marker":"[5]"},{"why":"Multi-objective grey wolf optimizer whose single-chase strategy the double-chase scheme extends and outperforms.","marker":"[11]"},{"why":"Genetic crossover idea that the circuit reproduction operator adapts.","marker":"[17]"},{"why":"Non-dominated sorting algorithm used to rank approximate circuits into Pareto fronts.","marker":"[18]"},{"why":"Defines the wire-by-wire local approximate change used for critical-path shortening.","marker":"[14]"},{"why":"Defines the wire-by-constant local approximate change used for critical-path shortening.","marker":"[15]"}],"fun_headline_variants":["Double-chase wolf optimizer cuts circuit delay by 27%","Approximate logic gets 38% faster with dual-objective search","New optimizer beats single-objective ALS in timing gains","Hierarchical wolf search trims critical path delay by 27%","DCGWO: 27% delay cut with area and depth co-optimization"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The circuit that scores best on the pre-sizing depth-and-area fitness function is assumed to remain the best after post-optimization resizing, so the reported final delay actually follows from the optimizer's choice.","fun_headline_variants_meta":{"raw":{"variants":["Double-chase wolf optimizer cuts circuit delay by 27%","Approximate logic gets 38% faster with dual-objective search","New optimizer beats single-objective ALS in timing gains","Hierarchical wolf search trims critical path delay by 27%","DCGWO: 27% delay cut with area and depth co-optimization"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000159,"raw_usage":{"total_tokens":1186,"prompt_tokens":863,"completion_tokens":323,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":479,"completion_tokens_details":{"reasoning_tokens":232}},"tokens_in":479,"tokens_out":323,"duration_ms":3805,"temperature":1.0,"reasoning_tokens":232,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T19:04:17.778525+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"For any benchmark, enumerate all Pareto-front approximate circuits produced by the optimizer before post-optimization, apply the same dangling-gate deletion and gate-resizing step to each, and check whether the circuit selected by the pre-sizing fitness function has the smallest post-sizing critical path delay; a single counterexample where another Pareto candidate is faster after resizing would falsify the claim that the optimizer's choice yields the maximum delay reduction.","supporting_citations":[{"cited_title":"Hedals: Highly efficient delay-driven approximate logic synthesis,","cited_arxiv_id":null,"evidence_quote":"Depth-driven baseline whose critical-error-graph selection is the central timing competitor."},{"cited_title":"VECBEE: A versatile efficiency–accuracy configurable batch error estimation method for greedy approximate logic synthesis,","cited_arxiv_id":null,"evidence_quote":"Area-driven baseline and fast Monte-Carlo error and similarity estimator used in evaluation."},{"cited_title":"Variability-aware approximate circuit synthesis via genetic optimization,","cited_arxiv_id":null,"evidence_quote":"Genetic ALS baseline that reports timing under variability and is compared on final delay."},{"cited_title":"Multi- objective grey wolf optimizer: a novel algorithm for multi-criterion optimization,","cited_arxiv_id":null,"evidence_quote":"Multi-objective grey wolf optimizer whose single-chase strategy the double-chase scheme extends and outperforms."},{"cited_title":"A fast and elitist multiobjective genetic algorithm: Nsga-ii,","cited_arxiv_id":null,"evidence_quote":"Genetic crossover idea that the circuit reproduction operator adapts."},{"cited_title":"An efficient approach to nondominated sorting for evolutionary multiobjective optimization,","cited_arxiv_id":null,"evidence_quote":"Non-dominated sorting algorithm used to rank approximate circuits into Pareto fronts."},{"cited_title":"Substitute-and- simplify: A unified design paradigm for approximate and quality con- figurable circuits,","cited_arxiv_id":null,"evidence_quote":"Defines the wire-by-wire local approximate change used for critical-path shortening."},{"cited_title":"Design and applica- tions of approximate circuits by gate-level pruning,","cited_arxiv_id":null,"evidence_quote":"Defines the wire-by-constant local approximate change used for critical-path shortening."}],"review_version":1}