{"id":"f71fecdb-ba5c-4519-9f10-88cbe76602fb","arxiv_id":"2411.13890","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":6,"one_line_summary":"GraCo uses reinforcement learning and graph consistency checks to jointly synthesize circuit topologies and transistor sizes, finding an inverter with about 5x fewer samples than random search and a faster NAND2 gate.","lead":"GraCo is a reinforcement learning system that builds integrated circuit diagrams step by step and checks each partial circuit for validity before running SPICE simulations. It aims to make automated chip design more sample-efficient, showing gains over random search on an inverter and a NAND gate.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Headline '2.5× faster NAND2' appears cherry-picked from best-of-15 runs across different consistency-check settings; no delay values or error bars are reported.","rationale":"The paper's central contribution is the claim that GraCo beats a random baseline by 5x (inverter) and 2.5x (NAND2). The inverter claim has 30 runs and is more credible. The NAND2 claim is the more striking and less supported: Table II's 'optimality gap' is an indirect reward-derived score, and the 2.5x figure is consistent with comparing the single best ES run (gap 6.66e-5) to the single best random run (gap 4.08e-4) across all 15 consistency-check configurations. That is a maximum-of-15 versus maximum-of-15 comparison, which inflates apparent superiority even when underlying distributions are identical. The paper also does not report actual delays, so the reader cannot check whether 'faster' is meaningful in absolute terms. The reader's weakest_assumption about design-space size is a valid concern but less directly tied to the headline number; the 2.5x claim is more falsifiable and more important. My proposed check would settle it by comparing delays under a fixed configuration with proper replication. Note: the inconsistency-check benefit claim (0.90 vs 0.88) is also marginal with n=3, but the 2.5x claim is the primary reason for the abstract's prominence.","tokens_in":13343,"tokens_out":6485,"duration_ms":60525,"concrete_test":"Reproduce the NAND2 comparison under one pre-registered consistency-check setting (e.g., 'None' or 'All during generation') for both GraCo ES and the random baseline, with at least 10 independent runs each. Report the measured propagation delays (the metric m in Eq. 4) for every run and compute the mean and 95% CI of the best-delay ratio ES/random. Also report the same ratio averaged over the 15 settings rather than using the best-of-15. If the ratio's CI does not exclude 1.0, or the best-of-15 ratio differs from the per-setting average by a large margin, the 2.5x claim should be revised or removed.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central NAND2 speedup claim is not supported by the paper's own table. In Sec. V-B, Table II reports only 'Optimality gap = 1 − Best reward' for three runs per consistency-check configuration. The smallest random gap is 4.08e-4 (Random, 'Connected in/out nets (during generation)', Run 1) and the smallest ES gap is 6.66e-5 (ES, 'No floating nets (GraCo input)', Run 1). Under the reward in Eq. 4, delay is proportional to sqrt(gap), so the ratio sqrt(4.08e-4/6.66e-5) ≈ 2.48 matches the claimed 2.5x. This selects the single fastest circuit from 15 random and 15 ES runs post hoc, across different consistency-check settings, and ignores the other runs. The paper's separate consistency-check result ('all checks during/after generation yields 0.90 vs 0.88') uses yet another subset of configurations, so the speedup claim is never compared under a fixed configuration. With n=3 per setting and no reported delay values or confidence intervals, the '2.5x faster' headline is an overstatement relative to the evidence.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes GraCo, an autoregressive graph-generation framework for integrated-circuit synthesis in which a graph neural network (DeeperGCN) sequentially adds nets and components, converts the assembled graph to a SPICE netlist, and scores it with a reward derived from transient simulation. Two optimization strategies are considered, REINFORCE with a leave-one-out baseline (RLOO) and evolution strategies (ES), and the framework allows the injection of design knowledge through explicit wiring rules, reward shaping, component limits, and graph consistency checks. Experiments are reported for two standard-cell tasks: an inverter and a two-input NAND gate. The headline claims are that ES finds the inverter with approximately 5× fewer sampling steps than a random baseline and that ES synthesizes a NAND2 gate that is 2.5× faster than the random baseline's best result, with consistency checks improving sampling efficiency. The manuscript describes the task setup, the graph representation, the consistency-check taxonomy, and an ablation table over consistency-check variants.","tokens_in":13565,"tokens_out":9066,"duration_ms":85944,"significance":"If the empirical claims were supported, GraCo would be a genuinely useful contribution to ML-based circuit synthesis: it jointly searches topology and sizing, is not tied to a fixed cell library, and formalizes several ways to inject expert knowledge (wiring rules, consistency checks, subcircuits). The paper is also honest about negative results, such as RLOO's premature convergence, and it reports multi-run data (30 runs for the inverter, 3 runs per NAND2 configuration). The stress-test worry that the design space is too constrained to make learning matter is not supported by the paper's own Table I: even after the mandatory wiring rules, the NAND2 topology space is on the order of 1e8–1e10 configurations. The weakness lies not in the task difficulty but in the reported comparisons: the NAND2 speedup claim is obtained by selecting the best run from different consistency-check settings, which is not a controlled comparison. The framework itself is plausible and the consistency-check ablation is informative, but the headline quantitative claims need to be re-established with paired, statistically grounded comparisons.","major_comments":[{"comment":"The headline '2.5× faster NAND2' is not supported by the table as reported. The value 2.48 arises from sqrt(4.08e-4 / 6.66e-5), which compares the single best random run under 'Connected in/out nets (during generation)' with the single best ES run under 'No floating nets (GraCo input)'. These are different consistency-check configurations, and the ES run uses a GraCo-input mechanism that the random baseline cannot use. Under the pure 'None' row, the ratio is only sqrt(1.33e-1 / 8.13e-2) ≈ 1.28. Moreover, for the 'All (during generation)' configuration highlighted in the consistency-check discussion, the best random gap (6.77e-2) and best ES gap (6.79e-2) imply essentially no speedup. A fair comparison must be made per configuration, with paired runs and with explicitly reported delay values or confidence intervals, not by post-hoc selection of the best run from 15 different settings.","section":"Sec. V-B, Table II, Eq. (4)"},{"comment":"The companion claim that ES is 'on average 30% faster than RLOO' is also a best-of-runs comparison, not an average: sqrt(1.34e-4 / 6.66e-5) ≈ 1.42 gives the 30% figure by comparing the single best RLOO gap (Paths after generation, Run 1) with the single best ES gap (No floating nets GraCo input, Run 1). With only three runs per configuration and no per-run delay values, no error bars, and no paired comparison under a fixed configuration, the word 'on average' is misleading. The authors should either report mean/median delays with variability across a fixed setting or soften the claim accordingly.","section":"Sec. V-B, Table II"},{"comment":"The inverter claim of '5× fewer sampling steps' is reported as a median ratio over 30 runs, but the figure does not show confidence intervals, and the text does not state whether the median is computed over successful runs only or over all runs (with failures counted at the 1024-step limit). Because the ratio of medians is a nonlinear statistic, a bootstrap confidence interval or at least explicit median and interquartile ranges should be reported. The current presentation leaves the magnitude of the improvement and its uncertainty unclear, which matters because the 5× figure is one of the two headline contributions.","section":"Sec. V-A, Fig. 5"}],"minor_comments":[{"comment":"The phrase 'random baseline' is used inconsistently: the 2.5× claim compares ES with a random run that uses a consistency check, whereas the pure random baseline without any consistency check is much slower. Please specify which configuration of the random baseline is being compared in each claim.","section":"Abstract and Sec. V-B"},{"comment":"The table reports only 'Optimality gap = 1 − Best reward' without giving the normalization factor m_norm from Eq. (4). Since delay is proportional to sqrt(gap) under the squared error reward, the reader should be told the m_norm used and, ideally, the absolute delay values for the best circuits, to make the speedup interpretation transparent.","section":"Table II"},{"comment":"The description of the 'No floating nets' check says 'all internal or output nodes are either unconnected or connected to at least two terminal nodes'; the phrase 'unconnected or' appears contradictory to the intent of preventing floating nodes and should be clarified.","section":"Sec. III-A"},{"comment":"The entropy regularization term is written as λH(πθ(·|st)) inside the sum over t; it should be made explicit whether H is a per-step entropy and whether the sum runs over all time steps, to avoid ambiguity in the loss definition.","section":"Sec. II-C, Eq. (2)"},{"comment":"The label 'until standard gate' in Table I is not defined in the text; please clarify whether it means the number of topologies that produce the standard-cell topology at exactly the minimal number of steps.","section":"Fig. 3 and Table I"}],"recommendation":"major_revision","confidential_remarks":"The paper fits the scope of an ML-for-EDA venue and the proposed framework is interesting, but the quantitative claims need to be substantially reworked. The NAND2 speedup is cherry-picked across different consistency-check settings and should be presented as a controlled per-configuration comparison with confidence intervals. The inverter claim also needs more statistical detail. I would be willing to look at a revised version that re-analyzes the existing data and clearly separates the pure random baseline from random-with-consistency-checks. No code or data release is mentioned, which makes the 3-run NAND2 results difficult to assess; adding a reproducibility note would help."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: the paper describes a real, working system, an autoregressive graph composer trained with RL (RLOO or evolution strategies) that builds circuit graphs step by step, converts them to netlists, and verifies them in SPICE. That part holds up. The headline NAND2 speedup does not, as stated.\n\nWhat is genuinely useful here: the consistency checks (connected I/O nets, path between input and output, no floating nets, no isolated subgraphs) are a simple, general way to prune invalid circuits before spending SPICE cycles, and the explicit wiring rules (bulk to supply/gnd, no supply to gate) reflect real manufacturing constraints rather than toy restrictions. Joint topology and sizing search in one autoregressive policy is a legitimate increment over AutoCkt, TOTAL, and CktGNN. The paper is clearly written and honest about RLOO's collapse problems.\n\nSoft spots, in order. First and largest: the \"2.5x faster NAND2\" claim. In Table II, the best random gap is 4.08e-4 (run 1 under \"Connected in/out nets (during generation)\") and the best ES gap is 6.66e-5 (run 1 under \"No floating nets (GraCo input)\"). Since delay scales as the square root of the gap under Eq. 4, that ratio is about 2.5, but it is the single best of 15 runs per method, under different consistency-check configurations, with n=3 per setting and no delay values or confidence intervals anywhere. The abstract presents this as the expected outcome; the paper's own table does not support that reading. The \"30% faster than RLOO\" claim has the same evidentiary problem. Second, the consistency-check benefit counts (\"12 of 15\", \"10 of 15\") rest on three runs per configuration, which is too thin to distinguish signal from noise. Third, the only baseline is random sampling; there is no comparison with published RL or evolutionary synthesizers, even though those are cited in the paper itself. The inverter result (30 runs, ES reliably finds reward 1, median 5x fewer steps) is the most solid piece of evidence, but even it lacks error bars on the ratio.\n\nOne place the skeptic goes too far: the worry that the wiring rules shrink the space so much that random search is near-optimal. The data argue otherwise, random fails to reach the correct voltage in 14 of the 15 NAND2 runs. So the space is not trivially searchable; the open question is whether the learned search, rather than the hand-set constraints, deserves the credit. These experiments do not settle that.\n\nBottom line: the framework deserves serious referee time, but the headline claims need correcting, and the experiments need more runs, code release, and at least one strong baseline. Send it to review.","headline":"A working RL graph-composer for circuit synthesis with a useful consistency-check idea, but the 2.5x NAND2 speedup is a best-of-run artifact and the claims need more runs and stronger baselines.","tokens_in":14161,"tokens_out":5458,"would_cite":true,"duration_ms":48374,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper claims that a reinforcement-learning agent which assembles circuits graph by graph and receives SPICE simulation rewards can beat random search, finding a verified inverter in about five times fewer sampling steps and a…","keywords":["circuit synthesis","reinforcement learning","graph neural networks","SPICE simulation","standard cells","consistency checks","evolution strategies","autoregressive graph generation"],"falsifier":"Run the same GraCo ES configuration on a larger standard cell, such as a 3-input NAND or full adder, with identical wiring rules and step limits scaled to the task; if the sampling-step advantage over random search disappears or becomes negative as the space grows, then the 5x and 2.5x results are artifacts of the small constrained inverter and NAND2 spaces rather than of the learned composer.","tokens_in":13102,"feed_emoji":"⚡","tokens_out":9030,"duration_ms":73824,"temperature":0.7,"pith_summary":"The paper introduces GraCo, a reinforcement-learning method that builds circuit schematics as graphs, one node and edge at a time, then converts the finished graph into a netlist and scores it with a SPICE simulation. The central claim is that learning to assemble the graph, guided by reward from simulation, is more sample-efficient than random search for small standard-cell design tasks. On an inverter, GraCo with evolution strategies finds a verified cell with roughly five times fewer sampling steps than the random baseline; on a two-input NAND gate, it finds a circuit that is on average 2.5 times faster than the random baseline's best. The paper also shows that graph consistency checks, applied during or after generation, improve the average best reward from 0.88 to 0.90 for the evolution-strategy variant. The framework is deliberately configurable, letting design knowledge enter through reward shaping, step limits, subcircuits, consistency checks, and explicit wiring rules.","feed_headline":"GraCo cuts inverter search 5x and builds a 2.5x faster NAND2","feed_subtitle":"Reinforcement learning that assembles circuit graphs step by step beats random search using far fewer SPICE simulations.","key_machinery":"The load-bearing object is the graph itself, with nets and component terminals as nodes and with each component's terminals forming a complete subgraph, so terminal identity needs no edge features. GraCo assembles this graph with a DeeperGCN, a graph convolutional network with skip connections, that reads the partially built graph and outputs logits for the next action, logits for choosing a component, means and log-variances for sizing parameters, and logits connecting each new terminal to an existing net. Two learning algorithms drive the search: RLOO, a REINFORCE variant with a leave-one-out baseline, and evolution strategies with mirrored sampling. The second key mechanism is a set of four graph consistency checks: connected input/output nets, a path from every input to every output, no floating nets, and no isolated subgraphs. These checks can be used to block premature stopping, to resample invalid graphs, or to augment the GCN input features, and they reduce the number of SPICE simulations spent on circuits that would fail anyway.","core_discovery":"GraCo's central claim is that circuit synthesis reduces to an autoregressive graph-generation problem that a reinforcement-learning agent can solve with fewer SPICE simulations than a random sampler. At each step the agent chooses one of three actions: add an internal net, add a component with continuously sampled sizing parameters, or stop generation and send the graph to SPICE. The paper reports that training this policy with evolution strategies rather than with RLOO, a leave-one-out-baseline REINFORCE variant, is the key to reliable search: ES finds a verified inverter in about five times fewer steps than random, and for NAND2 it discovers a circuit whose best reward corresponds to a gate that is on average 2.5 times faster than the random baseline's best. Consistency checks that reject invalid graphs before or after simulation make the search more efficient; on the NAND2 task, using all checks together raises the average best reward for the ES variant from 0.88 to 0.90. These results are presented as evidence that topology search and sizing can be learned jointly rather than assumed from a fixed circuit library.","pith_inferences":["A testable extension the paper leaves implicit: on larger design spaces where invalid graphs are more common, pruning with consistency checks should yield a larger speedup than the 5x observed on an inverter.","The comparison against random sampling leaves open how GraCo would fare against other learned topology or sizing tools on the same cells; a direct benchmark would clarify where the bounds lie.","The paper's single-best-instance goal suggests that an explicit replay buffer of successful circuits, which the authors list as future work, could turn GraCo into a reusable prior for new cells rather than a per-task search.","The consistency-check idea is purely graph-theoretic, so it might also apply to other autoregressive graph generators such as molecule synthesis or analog layout exploration."],"forward_implications":["If the results hold, topology search and transistor sizing can be optimized in one reinforcement-learning loop rather than in separate fixed-topology sizing steps.","The consistency-check mechanism is not tied to a particular component library, so the same four checks should transfer to other graph-based synthesis tasks.","Because ES outperformed RLOO on both tasks, exploration-oriented search is a better fit than exploitation-heavy policy gradients when the goal is a single best circuit rather than a reusable policy.","Adding subcircuits to the inventory lets designers inject existing IP blocks into the search without changing the underlying graph procedure.","Using all consistency checks during or after generation yielded the best average reward for the ES variant, while feeding the checks as extra GCN inputs did not help (0.86)."],"supporting_citations":[{"why":"Characterizes Bell numbers, used to argue the wiring-configuration space grows exponentially with circuit size.","marker":"[17]"},{"why":"Introduces DeepGCNs, the graph-convolutional backbone GraCo uses to read the partially assembled graph.","marker":"[24]"},{"why":"Extends DeepGCN to deeper architectures, supporting the eight-layer network GraCo employs.","marker":"[25]"},{"why":"Provides the REINFORCE gradient rule that underlies the RLOO baseline in GraCo.","marker":"[27]"},{"why":"Supplies the leave-one-out baseline technique that turns REINFORCE into RLOO.","marker":"[28]"},{"why":"Is the evolution-strategies method GraCo uses for weight-perturbation search, the algorithm that produced the best results.","marker":"[29]"},{"why":"Supplies mirrored sampling, which GraCo uses to reduce variance in the ES gradient.","marker":"[30]"},{"why":"Provides the 130 nm PDK transistor models and sizing bounds used in all experiments.","marker":"[31]"}],"fun_headline_variants":["GraCo RL synthesis beats random by 5x on inverter, 2.5x on NAND2","GraCo RL: 5x fewer SPICE runs for inverter, 2.5x faster NAND2","GraCo RL designs circuits: inverter found in 5x fewer steps, NAND2 2.5x faster","GraCo: RL graph composer finds inverter in 5x fewer SPICE calls, NAND2 2.5x faster","RL circuit composer GraCo: random beaten 5x on inverter, NAND2 2.5x faster"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The results assume that with the hand-set step limits (6 for inverter, 10 for NAND2) and mandatory wiring rules (bulk to supply/ground, no supply to gate), the remaining design space is large enough that the learned policy, and not the constraints, produces the reported gain over random search.","fun_headline_variants_meta":{"raw":{"variants":["GraCo RL synthesis beats random by 5x on inverter, 2.5x on NAND2","GraCo RL: 5x fewer SPICE runs for inverter, 2.5x faster NAND2","GraCo RL designs circuits: inverter found in 5x fewer steps, NAND2 2.5x faster","GraCo: RL graph composer finds inverter in 5x fewer SPICE calls, NAND2 2.5x faster","RL circuit composer GraCo: random beaten 5x on inverter, NAND2 2.5x faster"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000946,"raw_usage":{"total_tokens":4058,"prompt_tokens":984,"completion_tokens":3074,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":600,"completion_tokens_details":{"reasoning_tokens":2930}},"tokens_in":600,"tokens_out":3074,"duration_ms":18042,"temperature":1.0,"reasoning_tokens":2930,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T15:46:42.000776+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same GraCo ES configuration on a larger standard cell, such as a 3-input NAND or full adder, with identical wiring rules and step limits scaled to the task; if the sampling-step advantage over random search disappears or becomes negative as the space grows, then the 5x and 2.5x results are artifacts of the small constrained inverter and NAND2 spaces rather than of the learned composer.","supporting_citations":[{"cited_title":"A characterization of the bell numbers,","cited_arxiv_id":null,"evidence_quote":"Characterizes Bell numbers, used to argue the wiring-configuration space grows exponentially with circuit size."},{"cited_title":"Buy 4 reinforce samples, get a baseline for free!","cited_arxiv_id":null,"evidence_quote":"Supplies the leave-one-out baseline technique that turns REINFORCE into RLOO."},{"cited_title":"Antithetic acceleration of monte carlo integration in bayesian inference,","cited_arxiv_id":null,"evidence_quote":"Supplies mirrored sampling, which GraCo uses to reduce variance in the ES gradient."},{"cited_title":"Skywater 130nm PDK,","cited_arxiv_id":null,"evidence_quote":"Provides the 130 nm PDK transistor models and sizing bounds used in all experiments."}],"review_version":1}