{"id":"4bee29f5-3ad4-4be7-a6ab-057761ac9dbc","arxiv_id":"2411.13900","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":7.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"First known recovery of Apple Firestorm and Qualcomm Oryon conditional branch predictor internals, with identification of two new misprediction-inducing effects and a software mitigation.","lead":"Researchers reverse-engineered the internal conditional branch predictors of Apple's Firestorm and Qualcomm's Oryon CPUs using custom microbenchmarks and hidden performance counters. They then used the resulting models to find two previously undocumented behavior quirks that raise branch misprediction rates, and showed that a well-placed NOP instruction can cut mispredictions by up to 14% and speed up one workload by 7%.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Oryon recovery and low-confidence PHTs are not fully documented, making the central claim of recovering both CBPs partially unsubstantiated.","rationale":"The reader's weakest assumption targets the hidden PMC contamination. I find that concern partially mitigated: in the PHR-length experiment (Section 3.4.1, Figure 4), the misprediction rate is 0% for 100 dummy branches despite a randomized indirect branch in each iteration; if the conditional counter also counted indirect mispredictions, this baseline would be about 50%. Thus the counter is unlikely to be a fatal flaw. The more pressing issue is verifiability: the paper explicitly defers Oryon details to an unspecified online location, and Table 3 marks low-confidence entries. These are the soft spots of the central claim because the claim asserts exact recovery of both CBPs. My proposed check directly tests whether the promised supplement and the low-confidence entries hold. Since the reader's verdict CONDITIONAL already captures these addressable concerns, no verdict change is needed.","tokens_in":16411,"tokens_out":14382,"duration_ms":140070,"concrete_test":"Check whether the online supplement promised in Section 3.5 exists and contains the full Oryon PHT index/tag functions. If it does not, run the same differential microbenchmarks (Section 3.5.3/3.5.4) on a Qualcomm X1E-80-100 to see whether Table 3's Oryon entries reproduce; additionally, re-probe the Firestorm sixth PHT using an alternative correlation bit to test the 'low confidence' index bits. If the supplement is missing or the low-confidence entries are not reproducible, the central claim is only partially supported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim is that it recovers the CBPs of Apple Firestorm and Qualcomm Oryon. However, Section 3.5 states: 'we primarily present Firestorm results in the following paragraphs and we will publish the full results online.' No URL or artifact is given. The concrete Oryon PHT index/tag functions are therefore absent from the manuscript, so the Oryon half of the claim cannot be checked. Table 3 further marks several PHT rows with an asterisk ('low confidence'), including Firestorm's sixth PHT (index bits 11*) and Oryon's fifth and sixth PHTs. If the online supplement is unavailable or those low-confidence entries are wrong, the exact index/tag functions asserted in the central claim are not established. This is a missing-support concern, not a demonstrated error, but it is load-bearing because the claim is the recovery of exact structures.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a revised reverse-engineering pipeline for conditional branch predictors and applies it to Apple Firestorm and Qualcomm Oryon. It claims to recover a 100-bit PHRT, a 28-bit (Firestorm) or 32-bit (Oryon) PHRB, and six TAGE-like PHTs with the history lengths, associativities, and index/tag functions summarized in Table 3. The authors also report previously undisclosed PMCs (0xc5 on Firestorm and 0x400 on Oryon) that isolate conditional-branch mispredictions, identify two effects ('Scatter' and 'Annihilation') that degrade prediction accuracy, propose a NOP-insertion optimization that yields up to 14% MPKI reduction and 7% speedup on Oryon, and compare the recovered CBPs with Intel Skylake and Alder Lake in a common simulator.","tokens_in":16567,"tokens_out":5824,"duration_ms":60934,"significance":"If the recovered structures are correct, this is the first detailed disclosure of the conditional branch predictors in two major recent microarchitectures, and it would be of real value to compiler writers, performance engineers, and security researchers. The paper has several genuine strengths: the differential microbenchmarks avoid the strong PHR-clearing assumption of prior work, the hidden-PMC discovery is an independent contribution, and the measured NOP-optimization effect is a concrete, falsifiable result that does not depend on the correctness of the model. The unified simulator comparison, while preliminary, is a useful step toward cross-vendor CBP analysis. However, the paper is not fully self-contained: the Oryon index/tag functions are deferred to an unspecified online resource, and several PHT rows are explicitly marked low confidence. These gaps are load-bearing because the central claim is the recovery of exact structures.","major_comments":[{"comment":"The manuscript states that 'we primarily present Firestorm results in the following paragraphs and we will publish the full results online,' but no URL, repository, or artifact identifier is given anywhere. As a result, the Oryon PHT index and tag functions appear only as the column totals in Table 3, and even those are marked low confidence for Oryon PHTs 5 and 6. Because the first contribution claims recovery of the Oryon CBP, the Oryon half of the central claim is not checkable from the submitted manuscript. Please include the full Oryon recovery results (index/tag functions for all six PHTs) or explicitly reduce the claim to Firestorm only.","section":"Section 3.5, Contributions"},{"comment":"The identification of 0xc5 on Firestorm and 0x400 on Oryon as conditional-branch misprediction counters rests on only three microbenchmarks with expected values n/2, 0, and n/2. The paper does not report run-to-run variance, boundary behavior, or checks for contamination from indirect-branch mispredictions, return mispredictions, or other front-end events. Since every downstream measurement (PHR length, footprint bits, PHT index/tag functions) is filtered through this counter, an undetected contamination source would systematically bias the recovered parameters. Please add validation experiments with mixed branch types, varied branch frequencies, and repeated runs with reported confidence intervals.","section":"Section 3.3, Tables 1 and 2"},{"comment":"The recovery of PHTs 2–6 is described only briefly, and the history lengths in Table 3 (e.g., 57, 32, 18, 11, 6 for Firestorm) are asserted without the supporting microbenchmark evidence. In particular, the statement that 'to recover the 2nd PHT of Firestorm, which uses 57 bits of PHRT' appears to presuppose the quantity that the procedure is supposed to determine. Please explain how each history-length boundary was identified without prior knowledge of it, and provide the recovered index/tag equations for all six PHTs, or clearly mark which values remain provisional. The asterisked rows are not sufficient support for the exact-structure claim.","section":"Section 3.6 and Table 3"},{"comment":"The Scatter explanation is not quantitatively established. The text asserts that inserting a NOP between .L2 and .L3 makes the two critical branches' PHT tag contributions differ by only one bit, but it does not actually compute the tag/index values for the configurations in Table 4 using the recovered Oryon model, nor does it show that the model predicts the measured direction and magnitude of the MPKI change. Since the optimization itself is measured separately, this is not a circularity issue, but the 'root cause' claim needs a direct model-level demonstration, such as a simulated MPKI comparison with and without the NOP under the recovered Oryon CBP.","section":"Section 4.1.2"}],"minor_comments":[{"comment":"The comment 'how many taken branches an be tracked' contains a typo; it should read 'can be tracked'.","section":"Listing 1"},{"comment":"The figures appear to show single measurement runs without error bars or confidence intervals. Given the differential nature of the microbenchmarks, a small number of repeated runs would make the reported thresholds and bit positions considerably more convincing.","section":"Figures 4–8"},{"comment":"The header labels 'PHRT' and 'PHRB' do not indicate that the numeric values are history lengths in bits; please clarify, and also state whether the '# Index bits' column includes the associativity bits.","section":"Table 3"},{"comment":"The axis label 'Log2 branch base address' in Figure 7 is ambiguous; clarify whether the base address is the start address of a block of conditional branches and how the cases 2^3 through 2^19 were generated.","section":"Section 3.5.2"},{"comment":"The text states that the simulator 'aligns with a commercial processor' but gives no validation of modeled MPKI against hardware-measured MPKI for the same workloads. A brief validation table would substantially strengthen the comparison in Figure 9.","section":"Section 5.1.1"}],"recommendation":"major_revision","confidential_remarks":"To the editor: the main obstacle is verifiability rather than correctness of the measurements. The Oryon index/tag functions are promised in an online supplement that is not present, and several PHT rows are explicitly low confidence. If the authors can provide the missing artifact, the supporting microbenchmarks for PHTs 2–6, and error bars or repeated-run data, the paper could be considered for acceptance. If not, the central claim should be narrowed to Firestorm only. I also want to note that the measured NOP-insertion optimization is a useful empirical contribution independent of the model."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Here's the take: this is the first credible public reverse engineering of Apple Firestorm's conditional branch predictor, and the methodology is a real step beyond Half&Half. The Oryon half of the claim is real but not fully supported in the manuscript—the detailed results are deferred to an unspecified online location, and several PHT entries in Table 3 are marked low confidence. So treat the paper as a strong Firestorm study with an Oryon promise.\n\nWhat's new: the pipeline uses indirect branches to inject PHR values without contaminating the conditional misprediction counter, uses a differential approach to avoid needing to clear the PHR, and recovers tag before index. That's a legit generalization. The hidden PMC discovery on Oryon (0x400) is useful. The Scatter and Annihilation effects are documented with microbenchmarks; the NOP insertion giving 7% speedup on Oryon and 2% on Firestorm is a concrete, falsifiable result. The Firestorm model itself—100-bit PHRT, 28-bit PHRB, six PHTs with specific index/tag functions—is detailed and internally consistent. The comparison across Intel/Apple/Qualcomm under the ChampSim-like simulator is a nice touch, even if capacity dominates.\n\nSoft spots: First, the Oryon results. Section 3.5 says 'we primarily present Firestorm results... and we will publish the full results online.' No URL, no artifact. That means the central claim 'recover the CBPs of Apple Firestorm and Qualcomm Oryon' is only half-checkable. Table 3 marks several Oryon rows low confidence, and the Oryon index/tag functions are absent. This is a missing-support problem, not a demonstrated error, but it is load-bearing. Second, no error bars or run-to-run variance anywhere; the cliff in Figure 4 (0% to 50% at 100 vs 101 branches) is suspiciously clean. Third, the Scatter and Annihilation explanations are post hoc. They are consistent with the model, but the model is also used to explain them, so there's a mild self-reference. The NOP optimization is empirical and separate, so I don't see equation-level circularity, but the paper could be more careful about presenting the effects as hypotheses rather than confirmed mechanisms.\n\nWho benefits: compiler engineers, security researchers, and anyone doing microarchitectural side-channel analysis. The Firestorm model alone is worth the read. A serious referee should engage, but should request the Oryon supplement or a revision that includes at least the Oryon PHT functions in the paper.\n\nRecommendation: accept for peer review. The Firestorm contribution is substantial and the methodology is sound enough to warrant referee time. The Oryon gaps are addressable.","headline":"Firestorm CBP reverse engineering is strong and novel; Oryon details are deferred, making the dual-claim paper conditional.","tokens_in":17071,"tokens_out":3561,"would_cite":true,"duration_ms":29484,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper recovers the conditional branch predictor internals of Apple Firestorm and Qualcomm Oryon, revealing a TAGE-style design with split history registers and six pattern history tables.","keywords":["branch predictor reverse engineering","TAGE","Apple Firestorm","Qualcomm Oryon","path history register","performance monitoring counter","branch misprediction","MPKI"],"falsifier":"Run an indirect-branch-only workload on a Qualcomm X1E-80-100 and read counter 0x400; if it increments, the counter is not conditional-only and the inference chain collapses. Similarly, on Apple M1, if counter 0xc5 increments during an indirect-branch-only loop, the conditional-only assumption fails and the PHR-length measurement breaks.","tokens_in":16222,"feed_emoji":"🔍","tokens_out":4560,"duration_ms":45415,"temperature":0.7,"pith_summary":"The paper claims to recover, for the first time, the conditional branch predictor (CBP) internals of Apple Firestorm and Qualcomm Oryon, the microarchitectures behind the Apple M1 and Qualcomm X Elite. It identifies a TAGE-style predictor with a 100-bit target-address history register (PHRT), a second branch-address history register (PHRB) that is 28 bits on Firestorm and 32 bits on Oryon, and six pattern history tables with specified history lengths, associativities, index functions, and tag functions. It also discovers previously unpublished performance counters that count only conditional-branch mispredictions, which make the measurements possible. If these results hold, compilers and simulators can model these branch predictors instead of treating them as black boxes, and the paper reports up to 14% MPKI reduction and 7% speedup from two newly described misprediction effects, named Scatter and Annihilation.","feed_headline":"Apple and Qualcomm branch predictors cracked open","feed_subtitle":"Reverse-engineered TAGE tables and hidden counters yield up to 14% fewer mispredictions","key_machinery":"The central object is the split path history register pair (PHRT and PHRB) together with the six pattern history tables of a TAGE-style conditional branch predictor. TAGE is a predictor in which several pattern tables indexed by different history lengths vote, with the longest matching table overriding shorter ones. The paper's key mechanism is differential bit injection: instead of clearing the PHR to zero, it injects a single known bit difference into the history through indirect branches and observes conditional-branch mispredictions through newly discovered conditional-only performance counters. This allows each PHR bit, PC input bit, index bit, and tag bit to be located one XOR relationship at a time, without assuming a simple index organization or a clearable history register.","core_discovery":"The paper's central discovery is that the Firestorm and Oryon CBPs are TAGE-like predictors that keep branch history in two separate shift registers rather than one combined path history register. The first register, PHRT, is 100 bits wide and updates as PHRT_new = (PHRT_old << 1) XOR T[31:2]; the second, PHRB, is 28 bits on Firestorm and 32 bits on Oryon and updates as PHRB_new = (PHRB_old << 1) XOR B[5:2]. Each taken branch shifts both registers by one bit and XORs in the footprint, and only bits B[5:2] of the branch address and T[31:2] of the target address enter the footprint. The paper lists six pattern history tables for each core, with their history lengths, associativities, and capacities, and shows that Oryon's total inferred CBP size matches Qualcomm's announced 80 KB figure. It also recovers the index and tag functions of each table, which combine selected PHRT, PHRB, and PC bits through XOR operations, and uses these models to explain the Scatter and Annihilation effects that increase misprediction rates.","pith_inferences":["The differential-injection pipeline, including hidden-counter discovery, likely transfers to other undocumented out-of-order ARM cores, as long as any conditional-branch-only counter can be found or inferred.","The recovered index and tag formulas could enable more precise side-channel or branch-target-injection studies on these cores, a direction the paper does not explore.","The Scatter result suggests an automated compiler pass could simulate CBP tag behavior and choose NOP placements or branch reorderings to minimize PHT conflicts, rather than relying on manual inspection.","The split PHR design raises a question about speculative update and recovery cost that the paper leaves open; a quantitative study of that cost on real hardware would be a natural extension."],"forward_implications":["Software can now simulate the Firestorm and Oryon CBPs exactly enough to attribute mispredictions to specific branches and PHT entries, enabling root-cause optimization instead of heuristic tuning.","The Scatter effect implies that inserting a single NOP at a tag-sensitive location can cut mispredictions materially, as demonstrated by a 7% speedup on Oryon and 6% on Intel Cascade Lake.","The Annihilation effect implies that CBP designers should include lower bits of both branch and target addresses in the PHR footprint to reduce history collisions.","The cross-vendor comparison indicates that CBP capacity, not the fine details of hash functions, dominates MPKI, so future designs may trade hash complexity for larger tables.","Partitioning a PHT by one PC bit allows two adjacent conditional branches to be predicted per cycle from a single SRAM access, matching the observed Intel, Apple, and Qualcomm designs."],"supporting_citations":[{"why":"Supplies the original PHR-length and PHT reverse-engineering microbenchmarks that this paper generalizes and improves.","marker":"[26]"},{"why":"Demonstrates the prior CBP reverse-engineering approach on an ARM core, establishing the baseline this pipeline must surpass.","marker":"[25]"},{"why":"Provides the first branch-predictor reverse engineering through branch target injection, which motivates the counter-discovery and injection techniques.","marker":"[28]"},{"why":"Qualcomm's official description of the Oryon CBP size is used to validate the total inferred pattern-table capacity.","marker":"[24]"},{"why":"Defines the TAGE predictor structure, the tagged geometric history length scheme that the recovered CBPs implement.","marker":"[21]"},{"why":"Lists the standard ARMv8 performance counters, against which the paper identifies the previously undocumented Oryon counters.","marker":"[8]"}],"fun_headline_variants":["Apple and Qualcomm branch predictors cracked","Dual-history TAGE predictors in Apple and Qualcomm CPUs","14% fewer mispredictions via reverse-engineered branch models","Reverse-engineering Apple Firestorm and Qualcomm Oryon branch predictors"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The recovered structures are measured through performance counters that the paper assumes count only conditional-branch mispredictions; if those counters also count indirect-branch or other front-end mispredictions during the injection microbenchmarks, every inferred history length and index/tag bit could be wrong.","fun_headline_variants_meta":{"raw":{"variants":["Apple and Qualcomm branch predictors cracked","Dual-history TAGE predictors in Apple and Qualcomm CPUs","14% fewer mispredictions via reverse-engineered branch models","Reverse-engineering Apple Firestorm and Qualcomm Oryon branch predictors"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000257,"raw_usage":{"total_tokens":1615,"prompt_tokens":1019,"completion_tokens":596,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":635,"completion_tokens_details":{"reasoning_tokens":528}},"tokens_in":635,"tokens_out":596,"duration_ms":5654,"temperature":1.0,"reasoning_tokens":528,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T15:45:04.903196+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run an indirect-branch-only workload on a Qualcomm X1E-80-100 and read counter 0x400; if it increments, the counter is not conditional-only and the inference chain collapses. Similarly, on Apple M1, if counter 0xc5 increments during an indirect-branch-only loop, the conditional-only assumption fails and the PHR-length measurement breaks.","supporting_citations":[{"cited_title":"Half&half: Demystifying intel’s directional branch predictors for fast, secure partitioned execution","cited_arxiv_id":null,"evidence_quote":"Supplies the original PHR-length and PHT reverse-engineering microbenchmarks that this paper generalizes and improves."},{"cited_title":"Trustzonetunnel: A cross-world pattern history table-based microarchitectural side- channel attack","cited_arxiv_id":null,"evidence_quote":"Demonstrates the prior CBP reverse-engineering approach on an ARM core, establishing the baseline this pipeline must surpass."},{"cited_title":"Reading privileged memory with a side-channel,","cited_arxiv_id":null,"evidence_quote":"Provides the first branch-predictor reverse engineering through branch target injection, which motivates the counter-discovery and injection techniques."},{"cited_title":"The o-gehl branch predictor.The 1st JILP Championship Branch Prediction Competition (CBP-1) , 2004","cited_arxiv_id":null,"evidence_quote":"Qualcomm's official description of the Oryon CBP size is used to validate the total inferred pattern-table capacity."},{"cited_title":"A case for (partially) tagged geomet- ric history length branch prediction","cited_arxiv_id":null,"evidence_quote":"Defines the TAGE predictor structure, the tagged geometric history length scheme that the recovered CBPs implement."},{"cited_title":"Arm architecture reference manual armv8 for armv8-a archi- tecture profile, 2024","cited_arxiv_id":null,"evidence_quote":"Lists the standard ARMv8 performance counters, against which the paper identifies the previously undocumented Oryon counters."}],"review_version":1}