{"id":"76f3df59-fbae-4a86-acaf-a8bff4db59b5","arxiv_id":"2411.15521","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"A word-line voltage margin measured with a modified row decoder can characterize SRAM write stability without touching the memory core, and it correlates with existing writability metrics in simulation.","lead":"This paper introduces a new way to measure how easily a static RAM memory cell can be written, by finding the largest acceptable drop in the word-line voltage during a write. The method needs only a small change to the row decoder, so it can be applied to working memory chips to identify weak cells in advanced CMOS technologies.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Untested monotonicity of write success versus VDD_WL in the Section IV-B search is load-bearing: one non-monotonic cell near the failure boundary would misorder wlvm values and distort Section V distributions. Verify monotonicity and repeatability before accepting WLVM as a write-stability metric.","rationale":"The reader's weakest assumption is exactly the most load-bearing premise. The whole experimental pipeline reduces to pass/fail readouts at successively lower word-line voltages; if a cell can fail at j*Delta and succeed at (j+1)*Delta, then wlvm_i no longer equals 'the maximum reduction of the word-line voltage that still allows cell writing' as defined in Section IV. The simulated trajectories in Fig. 2 illustrate representative behavior but do not scan the VWL axis over a population, and the correlation coefficients in Fig. 6 do not test the internal consistency of the search algorithm. The concern is concrete and testable because the necessary control (VDD_WL) and readback path already exist on the test chip. I see no internal inconsistency in the row-decoder modification or in the basic idea, and the experimental PR dependence in Table III/Fig. 14 is a useful sanity check. The right disposition is the reader's CONDITIONAL verdict: the technique is plausible and the results are encouraging, but monotonicity and repeatability should be experimentally verified before WLVM is used to rank individual bit cells. Since the reader already identified this condition, no verdict change is needed.","tokens_in":8538,"tokens_out":8274,"duration_ms":83780,"concrete_test":"On the same 65 nm prototype, select about 50 cells per PR array and measure write success at each VDD_WL from nominal down to VDD-600 mV in steps of Delta (reporting Delta), performing M=100 write attempts at each level with a readout after every attempt. For each cell, plot success probability versus VDD_WL; monotonicity holds only if success probability is non-increasing as VDD_WL decreases for every tested cell. In addition, repeat the full Fig. 8 procedure twice per cell and report the fraction of cells whose wlvm changes by more than one Delta; a large fraction would show that the one-shot search is noise-limited rather than margin-limited.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section IV-B (Fig. 8) estimates wlvm_i with a one-shot decrement search: a cell that fails at VDD_WL = VDD - j*Delta is assigned wlvm_i = j*Delta, and because wlvm_i is updated as a running minimum, a later success at a lower VDD_WL cannot repair the assignment. The paper never establishes that write success is monotone non-decreasing in word-line voltage. In a 6T cell, word-line fall coupling, bit-line settling, and readback disturbance can each shift the pass/fail boundary, so a marginal write at one voltage could fail while a later attempt at a lower VDD_WL succeeds, especially since the write outcome may be probabilistic and only one attempt is made per cell per voltage. If this happens for even a small fraction of cells, the ranked wlvm distribution (Fig. 11), the byte-level aggregation (Fig. 13), and the PR trends in Table III would be distorted. This is an addressable concern, not a fatal one: the test chip already provides VDD_WL control and readback, so the assumption can be checked directly. The measured PR ordering in Fig. 14 is an encouraging independent check, but it does not validate the per-cell ordering produced by the search.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes Word-Line Voltage Margin (WLVM), defined as the maximum reduction of the word-line voltage that still allows an SRAM cell to be written, as an experimental writability metric. The measurement requires only a row-decoder modification providing a dedicated VDD_WL supply to the last decoder stage; the cell is written at progressively lower VDD_WL values and read back under nominal conditions. The authors validate the metric in Monte Carlo simulation against BWTV and WWTV, showing a linear correlation around 0.93, and then report measurements on a 65 nm CMOS prototype with five cell designs differing in pull-up ratio, demonstrating that the measured WLVM distributions exhibit the expected PR dependence and a spread attributable to process variability.","tokens_in":8754,"tokens_out":9066,"duration_ms":83325,"significance":"If the proposed technique is sound, it offers a practical, low-overhead way to obtain bit-level write-stability information from functional SRAM arrays without internal-node access, which would be valuable for weak-cell identification, yield analysis, and post-process characterization. The paper's main strength is the direct experimental demonstration: Table III and Fig. 14 show measured WLVM means within a few millivolts of simulation across five cell designs, and the monotonic dependence on pull-up ratio is consistent with device physics. The correlation with established writability metrics, however, is demonstrated only in simulation, not on the same test chip, and the search algorithm relies on an untested monotonicity assumption. The experimental data and the simple instrumentation are useful contributions, but the central measurement logic needs additional validation before the metric can be accepted as a reliable per-cell ranking tool.","major_comments":[{"comment":"The search algorithm assumes that write success is monotonically non-decreasing with word-line voltage, but this is never established. The procedure records the first voltage step j at which a cell fails and then never revisits that cell; if a later attempt at a lower VDD_WL succeeds, due to probabilistic write behavior, bit-line coupling effects, or word-line pulse-shape changes, the stored wlvm value would be wrong and the ranked distributions in Figs. 11-14 would be distorted. Since the test chip already provides VDD_WL control and readback, this assumption should be checked directly by repeating the measurement on the same cells and by sweeping VDD_WL both downward and upward to test for hysteresis.","section":"Section V-A, Table II"},{"comment":"The textual description of the algorithm is internally inconsistent with the definition of WLVM. The paper defines WLVM as the maximum voltage reduction that still allows writing, but the algorithm updates wlvm_i to the first failing step (the minimum failing drop), not the last successful drop, and the sentence 'This procedure finishes when any cell can be written to the their complementary value' would terminate the loop at the first iteration if taken literally. The authors should rewrite the procedure to state clearly whether wlvm records the last success or the first failure, give the correct termination condition, and reconcile the notation 'min(jΔ)' with the physical quantity being reported.","section":"Section V-A, Table II"},{"comment":"The measurement step Δ is never specified for the experimental results, despite the fact that quantization effects are acknowledged for the simulations (Section IV, Fig. 6). Without knowing Δ, the reported means and standard deviations in Table II and Table III cannot be interpreted, and the resolution of the per-cell ranking is unknown. Please state the step size used in the prototype measurements and, if the step is not negligible relative to the observed standard deviations, discuss the resulting quantization error.","section":"Section V-A, Table II"},{"comment":"The claim of 'good correlation with existing writability metrics' is supported only by Monte Carlo simulation, not by experimental cross-measurement on the prototype. The abstract and introduction state this property without qualification, which overstates the evidence. Please qualify the claim in the abstract and conclusions, or provide experimental measurements of BWTV/WWTV on the same test chip for at least one cell type.","section":"Section IV, Fig. 6"}],"minor_comments":[{"comment":"The text in Section V-A says the technique was applied at byte level, and Fig. 13 is described as byte-level results, but Table II labels the same level as 'Word level'. Please make the terminology consistent.","section":"Section V-A, Table II"},{"comment":"There are minor language issues, including 'Their experimental measurement can be attained' in the abstract and the keyword 'SRAM estability' (should be 'stability'). A copyedit pass would be beneficial.","section":"Abstract"},{"comment":"The overline notation for the complementary state XS is not typeset clearly in the provided text; please use a distinct symbol (e.g., XS_bar or a different variable name) to avoid confusion between the two states.","section":"Section IV-B"},{"comment":"The text states that WLVM was compared to WNM, BWTV, and WWTV in Fig. 5, but the correlation analysis in Fig. 6 only covers BWTV and WWTV. Please either add the WNM comparison to Fig. 6 or state explicitly that the WNM comparison is limited to the PR-trend plot.","section":"Section IV, Fig. 5"}],"recommendation":"major_revision","confidential_remarks":"The manuscript appears to build on the authors' workshop papers [7] and [9]. The editor may wish to confirm that the journal version adds sufficient new experimental content beyond those prior publications, particularly the measured PR dependence and the bit-level distributions. In addition, the abstract's correlation claim should be aligned with the fact that the BWTV/WWTV correlation is simulation-only. The monotonicity concern raised in Major Comment 1 is the most important technical issue and should be addressed with additional measurements before acceptance."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"This paper describes a measurement technique for SRAM write margin: WLVM, the maximum tolerable word-line voltage drop during a write. The genuinely new part is the measurement method—running normal write/read pass-fail sequences at decreasing VDD_WL, with the last row-decoder stage given its own supply. That is a small, clean modification, and they validate it on a 65 nm test chip with five cell sizes. The agreement between measured and simulated mean WLVM (Table III) is within a few percent, and the PR dependence is monotonic and in the right direction. That is real experimental evidence, not just simulation.\n\nThe correlation claim with BWTV and WWTV is more qualified. It is shown only in simulation (Fig. 6), with a linear correlation near 0.93. The abstract says \"good correlation\" without saying it is simulated; that overstates the evidence. On the same silicon they measured no reference metric, so the claim that WLVM tracks existing writability metrics is plausible but not demonstrated.\n\nThe bigger soft spot is the one the stress-test note lands on. The search in Fig. 8 assumes write success is monotone non-decreasing in word-line voltage. They never test that. If any cell is non-monotonic near the boundary—due to coupling or readback disturbance—the running-minimum update misorders wlvm values, and the distributions in Fig. 11 and the PR trends in Table III could be distorted. The measured PR ordering is encouraging but does not validate per-cell ordering. This is fixable: they have VDD_WL control and readback, so a simple repeatability/monotonicity check is within reach. Also, the step size Δ is never reported, which makes the quantized distributions hard to interpret. Minor but should be stated.\n\nThe paper reads as honest and careful; the citation pattern is appropriate, and the authors acknowledge Guo's analogous WWTV. It is a practical contribution for people who need bit-level write-stability screening on functional arrays.\n\nFor peer review: send it. The technique is useful, the silicon data is real, and the two concerns—monotonicity and the simulated-only correlation—are addressable in revision. I would not desk-reject.","headline":"A practical WL-voltage sweep method for SRAM write margin that mostly delivers, but needs a direct check of the monotonicity assumption and a reported step size before I'd trust the per-cell ordering.","tokens_in":9353,"tokens_out":1932,"would_cite":true,"duration_ms":17533,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A word-line voltage margin can expose every weak SRAM write cell","keywords":["SRAM","write margin","word-line voltage margin","process variability","writability","65 nm CMOS","weak cell identification","write trip voltage"],"falsifier":"Repeat the WLVM search on the same array but stepping the word-line voltage upward from below the expected threshold instead of downward; if per-cell thresholds differ systematically, or if any cell fails at a low voltage and later succeeds at an even lower voltage, monotonicity fails and the WLVM ranking is not trustworthy. A second check is to repeat the downward search with a finer voltage step and require per-cell values to shift by no more than one step.","tokens_in":8312,"feed_emoji":"⚡","tokens_out":9628,"duration_ms":83891,"temperature":0.7,"pith_summary":"SRAM cells in a modern CMOS memory are not all equally easy to write: process variability makes some cells marginal, and those weak cells are the ones most likely to fail later. This paper proposes the Word-line Voltage Margin (WLVM), defined as the largest reduction of the word-line voltage below its nominal value that still allows a successful write operation, as an experimentally measurable writability metric. The key claim is that WLVM can be obtained from a working memory array with only a small row-decoder modification, a dedicated supply node for the decoder's last stage, followed by a simple sequence of write attempts at decreasing word-line voltages and read-backs at nominal conditions. Results from a 65 nm CMOS prototype with five transistor-sizing variants show that WLVM distributions shift with pull-up ratio, that they expose per-cell weak spots, and that simulated WLVM values track the established BWTV and WWTV metrics with a linear correlation near 0.93. If correct, this gives designers a low-cost, non-intrusive way to map write stability cell by cell in a functional SRAM, something current test-structure-based parameters cannot provide.","feed_headline":"A word-line voltage margin can expose every weak SRAM write cell","feed_subtitle":"No internal nodes or current probes: the decoder supply alone yields a write margin for every cell in a 65 nm array.","key_machinery":"The load-bearing object is the Word-line Voltage Margin (WLVM), defined as the maximum reduction of the word-line voltage that still allows a cell write. Its experimental implementation rests on a row decoder whose final inverting stage is powered by a dedicated supply node, VDD_WL, so the word-line high level can be set independently of the memory core; the cell array layout itself is unchanged. The measurement procedure is an iterative search: start with VDD_WL at the nominal supply, write the complementary state, read back under nominal conditions, and repeat with VDD_WL reduced by Δ for every cell that wrote successfully, recording the largest tolerated drop and assigning a failed cell a zero margin. This mechanism turns an internal dynamic property, the transient state-space crossing that determines whether a write succeeds, into a pass/fail decision visible from the memory's normal interface, which is what makes bit-level write-margin mapping possible without current probes or internal node access.","core_discovery":"The central claim is that the write stability of a six-transistor SRAM bit cell can be quantified by a single externally observable number: the maximum word-line voltage drop that still lets the cell be overwritten. The paper shows that this number, WLVM, can be measured without touching the bit cell or the bit lines. The procedure writes the complementary state into a cell while the word-line voltage is stepped down by increments Δ, reads the cell back at nominal conditions after each attempt, and records the largest decrement for which the write still succeeds; the final WLVM for a cell is the minimum of the values obtained for the 0-to-1 and 1-to-0 write directions. In the minimum-sized 65 nm array these two directions differ, with a correlation of only r=0.2826, so both must be measured to identify weak cells. Across a 2048-cell array, WLVM spans roughly 160 mV between the strongest and weakest cell, and the mean value drops from 405 mV to 262 mV as the pull-up ratio rises from 1 to 2, rising to 482 mV for a pull-up ratio of 0.5, in agreement with simulation trends. The paper also reports that WLVM has a simulated linear correlation near 0.93 with both the bit-line write trip voltage and the word-line write trip voltage, while requiring none of the analogue switch arrays those metrics need.","pith_inferences":["An extension the paper leaves implicit is using the same VDD_WL knob to probe read stability, since read-disturb margin also varies with word-line voltage; the identical read-back search could find the maximum word-line voltage that does not disturb stored data.","The 0.93 correlation with BWTV and WWTV comes from simulation, not from simultaneous hardware measurement; putting all three metrics on the same die would test whether the ranking survives real process noise and measurement error.","Because the procedure needs no special test mode beyond ordinary write and read operations, it could be embedded as a production or in-field self-test with an on-chip adjustable word-line supply, turning WLVM into a drift and variability sensor."],"forward_implications":["Every cell in a functional SRAM array can be assigned a per-cell WLVM, so cells that are hard to overwrite can be located by address instead of inferred from separate test structures.","Because the measurement is only a write-and-read-back sequence with an adjustable word-line supply, it can be applied at bit, word, block, or full-memory level, trading resolution for test time.","The simulated correlation near 0.93 with BWTV and WWTV indicates that WLVM ranks cells nearly the same way as established metrics while eliminating bit-line current monitoring and the associated switch arrays.","WLVM distributions respond to pull-up ratio and transistor width in the expected direction, giving a quantitative, experimentally observable handle on how variability and sizing affect write-failure probability.","The row-decoder modification is compatible with write-assist techniques, so the margin measurement can coexist with other word-line voltage adjustments already present in low-power memories."],"supporting_citations":[{"why":"Defines the word-line write trip voltage (WWTV) measured through bit-line current monitoring, the baseline technique WLVM is designed to replace.","marker":"[8]"},{"why":"Introduce the Bit-line Write Trip Voltage (BWTV) metric that WLVM is compared against in the correlation analysis.","marker":"[16-18]"},{"why":"Demonstrates word-line pulse timing as an alternate writability monitor; WLVM avoids its clock-routing burden by modulating voltage instead.","marker":"[14]"},{"why":"First proposes the word-line voltage modulation approach to write margin that this paper turns into the WLVM metric.","marker":"[7]"},{"why":"Supplies the row-decoder word-line power-supply selector that gives experimental control of VDD_WL with minimal core modifications.","marker":"[9]"},{"why":"Shows the negligible area and timing impact of the decoder supply and its compatibility with write-assist, supporting the claim that WLVM is affordable.","marker":"[10]"}],"fun_headline_variants":["Word-line drop reveals every weak SRAM write cell","SRAM write stability from a single word-line measurement","No bit-line probes: word-line margin catches SRAM write fails","WLVM: one external voltage step maps SRAM write fragility","Affordable SRAM write test: step the word line, find the weak cells"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The search assumes that write success is monotone in word-line voltage: if a cell fails to write at one reduced voltage, it will also fail at every lower voltage, so stepping downward finds a clean single threshold without missing a narrow band of successful writes at lower voltages.","fun_headline_variants_meta":{"raw":{"variants":["Word-line drop reveals every weak SRAM write cell","SRAM write stability from a single word-line measurement","No bit-line probes: word-line margin catches SRAM write fails","WLVM: one external voltage step maps SRAM write fragility","Affordable SRAM write test: step the word line, find the weak cells"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000853,"raw_usage":{"total_tokens":3724,"prompt_tokens":982,"completion_tokens":2742,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":598,"completion_tokens_details":{"reasoning_tokens":2655}},"tokens_in":598,"tokens_out":2742,"duration_ms":19904,"temperature":1.0,"reasoning_tokens":2655,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T14:12:03.799020+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Repeat the WLVM search on the same array but stepping the word-line voltage upward from below the expected threshold instead of downward; if per-cell thresholds differ systematically, or if any cell fails at a low voltage and later succeeds at an even lower voltage, monotonicity fails and the WLVM ranking is not trustworthy. A second check is to repeat the downward search with a finer voltage step and require per-cell values to shift by no more than one step.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines the word-line write trip voltage (WWTV) measured through bit-line current monitoring, the baseline technique WLVM is designed to replace."},{"cited_title":"Design and Implementation of Dynamic Word - Line Pulse Write Margin Monitor for SRAM","cited_arxiv_id":null,"evidence_quote":"Demonstrates word-line pulse timing as an alternate writability monitor; WLVM avoids its clock-routing burden by modulating voltage instead."},{"cited_title":"Carmona, G","cited_arxiv_id":null,"evidence_quote":"First proposes the word-line voltage modulation approach to write margin that this paper turns into the WLVM metric."},{"cited_title":"Word-line power supply selector for stability improvement of embedded SRAMs in High Realiability Applications","cited_arxiv_id":null,"evidence_quote":"Supplies the row-decoder word-line power-supply selector that gives experimental control of VDD_WL with minimal core modifications."},{"cited_title":"Alorda, G","cited_arxiv_id":null,"evidence_quote":"Shows the negligible area and timing impact of the decoder supply and its compatibility with write-assist, supporting the claim that WLVM is affordable."}],"review_version":1}