{"id":"a6816d96-c202-419d-a0f2-1e291e548833","arxiv_id":"2411.16299","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"Back-gated IGZO nFETs fabricated in a 300mm fab show threshold voltage variability as low as 20mV sigma, with a newly reported spinel IGZO phase.","lead":"This paper reports IGZO transistors made on 300mm wafers that keep their turn-on voltage variation below 40mV across more than 100 devices. The work also reports a new crystalline phase of IGZO that may improve performance.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The sigma(VTH_ON) claim is computed \"across LCH and WCH,\" pooling different geometries; without per-dimension standard deviations, sub-40mV cannot be verified as a process-variability metric.","rationale":"The reader's weakest assumption was that the >100 devices are a representative, unfiltered sample of the 300mm wafer. That is related but not identical to my concern: even if the devices are unfiltered, the reported sigma is computed across a heterogeneous set of channel lengths and widths. A standard deviation across different geometries is not a standard process-variability metric; it conflates systematic design-dependent shifts with random variation. The paper does not provide per-cell sigma values, confidence intervals, or wafer-location information, so the sub-40mV claim cannot be independently checked. However, the paper does state explicitly that no filtering process was applied, which is positive evidence for representativeness, and the underlying device data likely exist. The appropriate response is therefore to keep the reader's CONDITIONAL verdict, with the condition sharpened to require per-geometry, per-location variability statistics. I do not see a reason to reject or accept outright based on the available text alone; the concern is about missing statistical detail in the central claim, not about an internal contradiction or an obviously false result. Other possible concerns, such as the identification of the 's-IGZO' phase, are less load-bearing because they do not directly support the headline variability claim. My recommendation is UNCHANGED relative to the reader's CONDITIONAL verdict, while emphasizing that the condition should be precisely about the definition and reporting of sigma(VTH_ON).","tokens_in":6654,"tokens_out":2883,"duration_ms":29729,"concrete_test":"Request the raw VTH_ON data for the >100 devices, including (LCH, WCH, and wafer x-y coordinates). Compute sigma(VTH_ON) separately for each geometry cell that contains at least 10 devices, and also compute within-cell spatial sigma from the wafer map. If the maximum within-cell sigma exceeds 40mV, or if the pooled sub-40mV value arises only from averaging across geometries, the central claim should be revised to specify per-condition variability. A simpler version: split the reported population along the LCH and WCH medians and compare the subgroup standard deviations; a large difference would indicate that the pooled statistic hides geometry-dependent variation.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is that \"The standard variation of the VTH-ON across LCH and WCH is often less than 40mV with a minimum of 20mV (Fig. 20).\" This statistic pools devices of different channel lengths and widths. In variability characterization, sigma(VTH) is conventionally reported for a fixed geometry and fixed operating condition; pooling across dimensions mixes systematic geometry-dependent shifts with random device-to-device variation. The text reports \">100 Back Gated IGZO-nFETs with no failed devices detected\" but gives no per-cell device count, no wafer map, and no confidence intervals. If VTH_ON has a systematic dependence on LCH or WCH, a pooled sigma can be either larger or smaller than the true within-cell sigma; the reported 20mV minimum is not tied to any specific geometry. The \"No filtering process applied\" statement addresses device selection but not the grouping of the statistic. Thus, the sub-40mV claim as stated is not yet established as a property of the process over a well-defined population; it is a property of an aggregate sample of varied devices. The NBTI and s-IGZO results do not substitute for a per-condition variability analysis.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports process-development results for back-gated and double-gated IGZO nFETs fabricated in a 300 mm fab, with channel lengths down to 120 nm and 70 nm, respectively. The central claim is that the standard deviation of the turn-on voltage VTH_ON is below 40 mV, with a minimum of 20 mV, measured across more than 100 back-gated devices of varying channel length and width. The paper also introduces a previously unreported IGZO phase called s-IGZO (spinel), supported by XRD and ab initio effective-mass calculations, and proposes an empirical model of n-type dopant location to explain variability, width-dependent electrostatic control, and the effect of hydrogen and oxygen annealing on different IGZO phases.","tokens_in":12,"tokens_out":2477,"duration_ms":65170,"significance":"If the variability claim holds with proper statistical backing, this is a meaningful empirical result for 300 mm-fab-compatible oxide semiconductor transistors, since threshold-voltage control is a known obstacle for IGZO nFETs. The paper reports a large device sample with no failed devices and explicitly states that no filtering was applied, which is a useful transparency measure. The ab initio effective-mass comparison for the claimed s-IGZO phase is a concrete, non-fitted theoretical cross-check. The process-learning results, such as the oxygen-anneal behavior under different capping oxides and the Ti contact scavenging studies, are potentially valuable for the IGZO community. However, the significance of the headline variability claim is currently limited by the absence of per-geometry statistics, confidence intervals, and wafer-map information.","major_comments":[{"comment":"The central claim, stated as 'The standard variation of the VTH-ON across LCH and WCH is often less than 40mV with a minimum of 20mV (Fig. 20)', pools devices of different channel lengths and widths into a single sigma. In variability characterization, sigma(VTH) is conventionally reported for a fixed geometry and operating condition; a pooled statistic mixes systematic geometry-dependent shifts with random device-to-device variation. Without per-dimension sigma values, per-cell device counts, and confidence intervals, the sub-40 mV result cannot be verified as a process-variability metric over a well-defined population. The statement 'No filtering process applied' addresses device selection but not the grouping of the statistic, so the headline claim needs additional statistical reporting to be established.","section":"Demonstration Of σ(VTH-ON) Down To 20mV"},{"comment":"The identification of a new 's-IGZO (spinel phase)' rests on a single XRD figure (Fig. 9) with peak assignments and the sentence 'we verified that the transition between the different phases is not due to any compositional changes within the IGZO material.' No supporting composition data, structural refinement, HRTEM/SAED, or detailed XRD analysis is shown. Since the claimed new phase is used to explain the improved ION-VTH_ON trade-off (Fig. 13) and is central to the paper's scientific novelty, the phase identification needs stronger structural and compositional evidence than a single unindexed XRD spectrum.","section":"Amorphous IGZO, C-Axis Aligned IGZO and new s-IGZO"},{"comment":"The paper does not report how the '>100 Back Gated IGZO-nFETs' were distributed across the wafer or across the LCH/WCH matrix, nor does it provide any measure of statistical uncertainty (e.g., confidence intervals for the standard deviation) or a wafer map. The conclusion that sub-40 mV variability is a property of the 300 mm process assumes that the measured devices are representative of the wafer. Without this contextual information, the claim remains an aggregate sample property rather than a validated process metric, even if the pooled sigma is accepted as a descriptive statistic.","section":"Demonstration Of σ(VTH-ON) Down To 20mV"}],"minor_comments":[{"comment":"Figure 10 and the related text state that amorphous IGZO has 'much reduced spread in VTH-ON and higher ID,LIN' than CAAC-IGZO, but no quantitative spread values are given; adding the standard deviation or range for each phase would strengthen the comparison.","section":"Discussion About Variability In IGZO NFET"},{"comment":"The caption of Fig. 17 is identical to that of Fig. 15 ('Dual IGZO deposition CAAC on top of a-IGZO...'), but Fig. 17 appears to display SSRM and the empirical dopant model; this caption mismatch should be corrected.","section":"Amorphous IGZO, C-Axis Aligned IGZO and new s-IGZO"},{"comment":"Figures 19 and 20 have essentially the same caption ('More than 100 back-gated IGZO nFETs functional across WCH dimensions. No filtering process applied') even though Fig. 20 is the sigma plot; the caption for Fig. 20 should describe the standard-deviation statistic and the axes.","section":"Demonstration Of σ(VTH-ON) Down To 20mV"},{"comment":"The abstract contains a typo, 's ub-40mV', which should read 'sub-40mV'.","section":"Abstract"},{"comment":"The author affiliation contains 'Jose Ignacio del Agua Borniquel2a' while the footnote indicates '2a also imec resident'; the superscript formatting is inconsistent and should be cleaned up.","section":"Fabrication Of Scaled 300mm-IGZO NFET"}],"recommendation":"major_revision","confidential_remarks":"The paper is a process-development report with a strong empirical core, but the headline variability claim is not yet presented in a form that a device-physics journal can fully evaluate. The authors should be asked to provide per-geometry sigma values, sample sizes, and confidence intervals, and to strengthen the structural evidence for the s-IGZO phase. If these are available from additional analysis of the existing data, a revision can address both concerns without new device fabrication."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThe imec paper is a solid engineering report: scaled IGZO nFETs on 300mm wafers with a reported sigma VTH_ON under 40mV, often down to 20mV, across more than 100 back-gated devices. That is a useful data point for anyone working on oxide channel transistors. The new claimed phase, s-IGZO (spinel), is the more ambitious claim, and it is supported by a single XRD figure plus some DFT effective-mass calculations. The empirical part—phase-dependent response to hydrogen anneals, PBTI/NBTI behavior, contact resistance engineering—is generally coherent and gives the paper value even if the phase identification turns out to need refinement.\n\nThe soft spots are real but not disqualifying. First, the sigma(VTH_ON) statistic pools across LCH and WCH. The text says ‘across LCH and WCH’, and Figure 20 plots a single standard deviation for more than 100 devices of mixed geometries. That makes it hard to tell whether this is a property of the process or an artifact of pooling systematic dimension-dependent shifts with random device variation. A per-cell breakdown, wafer map, or confidence intervals would settle it. The authors do say no filtering was applied, which is good, but it does not replace per-condition statistics. Second, the s-IGZO identification needs more than one XRD trace—no HRTEM, no selected-area diffraction, no Rietveld or PDF analysis. The ‘previously unreported’ claim deserves caution until that is provided. Third, a few figure captions are mismatched (Figure 17’s caption repeats Figure 15’s description), which is sloppy and makes the reader work harder to verify the claims.\n\nNone of this sinks the engineering message. The paper is honest, the data are extensive, and the ab initio results are not fitted to the device data. I would accept it for peer review with a request for additional statistical detail and structural evidence on s-IGZO.\n\nFor a reading group: maybe, if you care about IGZO or BEOL transistors. I would cite it if I worked on oxide channel variability. It deserves a serious referee.","headline":"A credible 300mm IGZO variability demonstration with an interesting but under-supported new phase claim.","tokens_in":7526,"tokens_out":2121,"would_cite":true,"duration_ms":20445,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Back- and double-gate IGZO nFETs fabricated in a 300mm fab achieve threshold-voltage standard deviations below 40mV, down to 20mV, across more than 100 unfiltered devices at channel lengths down to 120nm.","keywords":["IGZO thin-film transistors","threshold voltage variability","sub-40mV sigma(VTH_ON)","back-gate nFET","300mm wafer processing","s-IGZO spinel phase","oxygen vacancy doping","hydrogen doping"],"falsifier":"Run the same 300mm process flow on a second wafer without changing the recipe, and extract $\\sigma(V_{\\mathrm{TH,ON}})$ from every functional device across the full wafer, including edge and corner dies; if the all-site $\\sigma$ exceeds 40mV, or if a reproducible edge-of-wafer tail appears above the 40mV threshold, the wafer-level sub-40mV claim would be falsified.","tokens_in":6475,"feed_emoji":"🔬","tokens_out":12271,"duration_ms":102016,"temperature":0.7,"pith_summary":"This paper aims to show that IGZO thin-film transistors made in a 300mm production-line fab can hold threshold-voltage variability to a standard deviation of 20–40mV, a level of control normally associated with silicon rather than with oxide semiconductors. The authors establish this with back-gated nFETs scaled to 120nm gate length, and with double-gated devices to 70nm, by measuring more than 100 unfiltered devices across channel lengths and widths. The practical stakes are that IGZO could serve as the channel for dense 3D-stacked memory and logic, where tight and predictable threshold voltages are essential for low-power operation. To explain the result, the paper ties the low variability to a model of where n-type dopants (oxygen vacancies and hydrogen) sit in the channel, and reports a new spinel phase of IGZO, called s-IGZO, whose lower effective mass gives higher mobility.","feed_headline":"IGZO transistors hit sub-40mV threshold spread in 300mm fab","feed_subtitle":"Back-gated nFETs hold threshold variation under 40mV across 100+ devices, tightening oxide-semiconductor variability.","key_machinery":"The key machinery is the dopant-location model for n-type doping in IGZO. It treats oxygen vacancies and incorporated hydrogen as the two shallow donors that set $V_{\\mathrm{TH,ON}}$, and it specifies where those dopants end up after a 300mm process flow: vertically (the bottom half of the channel carries transport, the top half sets electrostatic control), longitudinally (titanium at the source/drain contacts scavenges oxygen to create local doping), and laterally (patterning leaves extra dopants at the channel edges, so widths below 200nm improve electrostatic control). This model turns variability from an uncontrolled material property into a process-controlled quantity, which is what lets the authors push $\\sigma(V_{\\mathrm{TH,ON}})$ below 40mV. A second piece of machinery is the newly reported s-IGZO phase, a spinel-structured IGZO whose band structure gives a lower electron effective mass and therefore higher mobility than CAAC-IGZO.","core_discovery":"The central discovery is that scaled IGZO nFETs processed in a 300mm fab can be made with sub-40mV $\\sigma(V_{\\mathrm{TH,ON}})$, with a minimum of 20mV, across more than 100 functional back-gated devices with no filtering. The paper attributes this control to a three-dimensional map of n-type dopants in the IGZO channel: oxygen vacancies and hydrogen act as shallow donors; oxygen anneals passivate vacancies poorly when a top gate blocks the anneal but work from the back side; a thin Ti contact layer scavenges oxygen locally to dope the source/drain regions; and patterned IGZO edges carry extra dopants, which is why shrinking the channel width below 200nm improves $V_{\\mathrm{TH,ON}}$ control. The paper also identifies a previously unreported spinel phase, s-IGZO, which has a lower conduction-band effective mass than the c-axis-aligned crystal phase (CAAC-IGZO) and gives a better ION-versus-$V_{\\mathrm{TH,ON}}$ trade-off at short channel lengths, along with a dopant-location model that reconciles the phase-dependent doping trends seen in earlier work.","pith_inferences":["If the unfiltered 100-device sample is representative, most observed $V_{\\mathrm{TH}}$ spread in IGZO FETs comes from process-induced dopant gradients (hydrogen loading, edge effects, contact scavenging) rather than from intrinsic channel disorder, which would mean variability is a layout and process parameter rather than a material ceiling.","The width-scaling result suggests a concrete design rule: using channels narrower than about 200nm can intentionally tighten $V_{\\mathrm{TH}}$ distribution, and the paper's own data indicate this can be done without sacrificing drive current at a fixed offset voltage.","The s-IGZO benefit was shown in thick back-gated films; a natural next test is whether the phase and its hydrogen tolerance survive a top-gate-first integration and ultra-thin channel scaling.","The contact data imply that source/drain doping and channel doping can be engineered independently, so one could combine a lightly doped channel with Ti-based contacts to push $\\sigma(V_{\\mathrm{TH,ON}})$ even lower than 20mV, a combination the paper does not explicitly optimize."],"forward_implications":["Back-gated IGZO nFETs with sub-40mV threshold control can be produced on 300mm wafers at channel lengths down to ~120nm and widths down to 200nm, making IGZO a realistic candidate for dense 3D-stacked memory and logic.","The s-IGZO spinel phase gives a better short-channel trade-off between drive current and $V_{\\mathrm{TH,ON}}$ than both amorphous and CAAC-IGZO, so it is a promising channel phase for scaled oxide transistors.","Because edge doping and hydrogen loading, not just the gate dielectric, dominate $V_{\\mathrm{TH}}$ spread, layout choices such as narrow channel widths become part of the variability-control toolkit.","The back-gated, oxygen-vacancy-controlled devices show limited NBTI degradation up to 1000s at oxide fields up to 5MV/cm, supporting the reliability of this integration scheme.","A Ti contact layer thinner than 5nm gives specific contact resistivity near $10^{-7}\\,\\Omega\\,\\mathrm{cm^2}$, decoupling low-resistance contacts from the channel doping used for $V_{\\mathrm{TH}}$ control."],"supporting_citations":[{"why":"Establishes that oxygen vacancies act as n-type dopants in IGZO and that post-processing oxygen anneals can passivate them, the mechanism the paper tunes to control $V_{\\mathrm{TH,ON}}$.","marker":"[7]"},{"why":"Provides the finding that the weakest-bonded oxygen atoms in IGZO are released under hydrogen anneal to form OH, the basis for the hydrogen-doping and phase-dependent response in Fig. 3.","marker":"[5]"},{"why":"Supplies TCAD modeling of hydrogen diffusion and bias temperature instability in a-IGZO, which the paper uses to interpret hydrogen-related doping and $V_{\\mathrm{TH}}$ behavior.","marker":"[6]"},{"why":"Defines the IGZO integration scheme with Ti/W metallization that the present 300mm flow builds on.","marker":"[4]"},{"why":"Provides the amorphous-IGZO effective mass value from literature that the paper compares against its ab-initio values for the s-IGZO and CAAC phases.","marker":"[8]"},{"why":"Documents the zepto-ampere off-state leakage premise that motivates IGZO as a candidate channel for low-power 3D integration.","marker":"[2]"}],"fun_headline_variants":["300mm-fab IGZO nFETs hit sub-40mV threshold spread","Back-gated IGZO: sub-40mV threshold variation in 300mm fab","New IGZO phase enables sub-40mV Vth in scaled nFETs","IGZO nFETs: sub-40mV Vth scatter, new spinel phase","Sub-40mV Vth spread in 300mm-fab IGZO nFETs"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The sub-40mV $\\sigma(V_{\\mathrm{TH,ON}})$ claim rests on the assumption that the more than 100 measured devices are a representative, unfiltered sample of the 300mm wafer, because the paper does not report the number of devices per dimension, their wafer locations, or confidence intervals.","fun_headline_variants_meta":{"raw":{"variants":["300mm-fab IGZO nFETs hit sub-40mV threshold spread","Back-gated IGZO: sub-40mV threshold variation in 300mm fab","New IGZO phase enables sub-40mV Vth in scaled nFETs","IGZO nFETs: sub-40mV Vth scatter, new spinel phase","Sub-40mV Vth spread in 300mm-fab IGZO nFETs"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000992,"raw_usage":{"total_tokens":4179,"prompt_tokens":897,"completion_tokens":3282,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":513,"completion_tokens_details":{"reasoning_tokens":3171}},"tokens_in":513,"tokens_out":3282,"duration_ms":24010,"temperature":1.0,"reasoning_tokens":3171,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T13:15:59.364047+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same 300mm process flow on a second wafer without changing the recipe, and extract $\\sigma(V_{\\mathrm{TH,ON}})$ from every functional device across the full wafer, including edge and corner dies; if the all-site $\\sigma$ exceeds 40mV, or if a reproducible edge-of-wafer tail appears above the 40mV threshold, the wafer-level sub-40mV claim would be falsified.","supporting_citations":[{"cited_title":"Physics and technology of crystalline oxide semiconductor CAAC-IGZO","cited_arxiv_id":null,"evidence_quote":"Establishes that oxygen vacancies act as n-type dopants in IGZO and that post-processing oxygen anneals can passivate them, the mechanism the paper tunes to control $V_{\\mathrm{TH,ON}}$."},{"cited_title":"High-Mobility and H2-Anneal Tolerant InGaSiO/InGaZnO/InGaSiO Double Hetero Channel Thin Film Transistor for Si-LSI Compatible Process","cited_arxiv_id":null,"evidence_quote":"Provides the finding that the weakest-bonded oxygen atoms in IGZO are released under hydrogen anneal to form OH, the basis for the hydrogen-doping and phase-dependent response in Fig. 3."},{"cited_title":"TCAD Simulation of Hydrogen Diffusion Induced Bias Temperature Instability in a‐IGZO Thin‐Film Transistors","cited_arxiv_id":null,"evidence_quote":"Supplies TCAD modeling of hydrogen diffusion and bias temperature instability in a-IGZO, which the paper uses to interpret hydrogen-related doping and $V_{\\mathrm{TH}}$ behavior."},{"cited_title":"IGZO integration scheme for enabling IGZO nFETs","cited_arxiv_id":null,"evidence_quote":"Defines the IGZO integration scheme with Ti/W metallization that the present 300mm flow builds on."},{"cited_title":"Pourtois, Phys","cited_arxiv_id":null,"evidence_quote":"Provides the amorphous-IGZO effective mass value from literature that the paper compares against its ab-initio values for the s-IGZO and CAAC phases."},{"cited_title":"Challenge of crystalline IGZO ceramics to silicon LSI - Its application to AI and displays","cited_arxiv_id":null,"evidence_quote":"Documents the zepto-ampere off-state leakage premise that motivates IGZO as a candidate channel for low-power 3D integration."}],"review_version":1}