{"id":"90ba5f4b-a648-450e-af5c-8d90baf8b60e","arxiv_id":"2411.18090","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":8,"one_line_summary":"A parallel fully feedforward neural network high-level surface code decoder achieves a 14.22% threshold and sub-440ns latencies in CIM simulation.","lead":"A fully parallel neural-network surface code decoder is proposed, with both decoding steps running at the same time on compute-in-memory hardware. It reports a 14.22% decoding threshold and sub-440 nanosecond latencies for code distances 3 through 9.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"14.22% threshold may be an artifact: with only d=3-9 and training at p=0.15 (0.8 points from the claim), the FFNN's 'threshold' needs stability checks at other training rates and d=11/13 before it can be said to surpass MWPM.","rationale":"The reader's conditional verdict is reasonable, but the weakest assumption is not primarily the co-achievable hardware parameters. The 14.22% threshold is the first quantitative claim and the stated basis for surpassing MWPM. It is extracted from four small distances with networks trained at p=0.15, only 0.8 percentage points above the claimed crossing. Such finite-size crossings are not thresholds in the asymptotic sense, and because the FFNN is a learned proxy for PED, the threshold is only as valid as the FFNN's coverage of the syndrome space. Training at a single rate near the claimed crossing makes coverage at higher error rates uncertain. The hardware-latency concern raised by the reader is real, but a slower-than-claimed decoder still leaves the architectural contribution intact; a spurious threshold would undermine the headline accuracy result. Both issues are testable, so the conditional verdict should stand, but the acceptance conditions should include the retraining and larger-distance checks above.","tokens_in":12489,"tokens_out":14344,"duration_ms":121803,"concrete_test":"Retrain the simple decoder and classifier from scratch with p_train=0.12 and p_train=0.18 (or 0.10 and 0.20), keeping all other protocol identical, and recompute the d=3-9 curve crossing; if the crossing shifts by more than about 0.5 percentage points, the 14.22% 'threshold' is an artifact of the training rate. Then generate PED-labelled datasets for d=11 (and, if feasible, d=13) using the open-source code from [14], and add those logical-error-rate curves to Fig. 6(a); if the crossing moves downward or the curves do not meet at a common point, the finite-distance crossing is not a true decoding threshold. Also report the FFNN-versus-PED prediction divergence as a function of physical error rate for each distance to confirm generalization beyond p_train.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The abstract's headline accuracy claim is the 14.22% decoding threshold. For that number to mean what it claims, two conditions must hold: (1) the crossing of logical-error-rate curves in Fig. 6(a) is a genuine threshold, stable as the code distance grows; and (2) the FFNN trained at p_train=0.15 reproduces the PED teacher across the full p in [0.03,0.3] evaluation range. Neither is demonstrated. Only d=3,5,7,9 are used; with four small distances, finite-size crossings are common and can shift or disappear at larger d. The choice p_train=0.15 is especially fragile because the claimed threshold is 14.22%, only 0.8 percentage points away. At p>0.15 the syndrome distribution contains high-weight errors that are absent or rare in training, so the learned modules may deviate from PED exactly in the regime that determines the crossing; the reported '<0.5%' non-ideality impact does not quantify FFNN-vs-PED divergence versus p. The text concedes that the actual decoding rules match the PED-based high-level decoder, so unless the FFNN is shown to generalize, the threshold is inherited and the 'surpassing MWPM' comparison is not independently established for the FFNN. Without a stability check, 14.22% reads as a finite-size/pseudo-threshold rather than a decoder threshold.","agreement_with_reader":"disagree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a parallel fully feedforward neural network (FFNN) high-level decoder for surface codes, in which both the simple decoder and the classifier are two-layer FFNNs trained on labels generated by the Pure Error Decoder (PED). The decoder is evaluated under a depolarizing noise model for distances 3, 5, 7, and 9, and its latency is simulated with the MNSIM 2.0 computing-in-memory (CIM) platform. The authors claim a decoding threshold of 14.22%, pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% for d=3, 5, 7, and 9, and sub-440 ns latencies on an NVM-based CIM architecture, with results extrapolated to a 4 K cryogenic environment.","tokens_in":12842,"tokens_out":5475,"duration_ms":47536,"significance":"If the threshold and latency claims are substantiated, the architectural contribution is significant: it would be the first demonstration of a fully neural-network high-level surface code decoder whose two modules run in parallel, and the first CIM-based evaluation of such a decoder with sub-440 ns latency. The use of MNSIM 2.0 to analyze hardware non-idealities and the discussion of hardware parameter impacts are useful for the quantum error correction architecture community. However, the headline accuracy numbers are inherited from the PED teacher rather than derived from the FFNN itself, and the threshold estimate relies on a small range of code distances; the significance is therefore conditional on additional validation.","major_comments":[{"comment":"The claimed 14.22% decoding threshold is determined from only four distances (3, 5, 7, 9) and a single training physical error rate p_train=0.15. The claimed threshold lies only 0.8 percentage points from p_train, and the pseudo-thresholds are non-monotonic (12% at d=7 vs. 11.6% at d=9), so the crossing in Fig. 6(a) has not been shown to be stable against finite-size effects. A genuine decoding threshold should persist to larger distances; the authors should add d=11 and d=13 results (even with reduced sample counts) and a sensitivity check over p_train in, say, [0.12, 0.18]. Without such evidence, the statement that the decoder 'surpasses MWPM' at threshold is not supported by the data presented.","section":"IV-C, Fig. 6(a)"},{"comment":"Table III mixes decoder thresholds with pseudo-thresholds. The column labeled Dth lists 14.22% for Ours next to '>12.49%' for PED+NN [14] and '>12.45%' for LUT+NN [2], which are pseudo-thresholds, while the MWPM entries 1.81% and 2.90% are thresholds under different noise models (self-modified and circuit-level, respectively). The 10.3% MWPM baseline quoted in the abstract appears nowhere in the table. A credible comparison requires a single noise model, a single metric, and separate columns for threshold and pseudo-threshold.","section":"Table III"},{"comment":"The paper states that 'the actual decoding rules match the PED-based high-level decoder', which means the 14.22% threshold is inherited from the PED teacher, not independently established by the FFNN. To substantiate the headline threshold as an FFNN property, the authors should quantify the FFNN-versus-PED output disagreement as a function of physical error rate across the full test range [0.03, 0.3], especially for p>0.15 where high-weight syndromes are rare in training. The '<0.5%' non-ideality impact reported in Fig. 6(e) is a hardware non-ideality measure and does not address this student-teacher divergence.","section":"III-C"},{"comment":"The 4K extrapolation applies the cooling-derived latency reduction of [36] to the entire decoder, but Table III reports 3.98W total power at d=9 and 0.4V, and the paper does not explain how this power is managed at 4K given the limited cooling power typical of cryostats for quantum processors. Moreover, Table I sets each of the five main hardware parameters to maxima taken from different sources (2GHz digital frequency, 256 GB/s inter-tile bandwidth, 19600-bit buffer, 256 ADC/DACs); no evidence is given that these values can be co-satisfied in a single CIM system. The sub-440ns latency claim should be presented as an optimistic upper-bound configuration and supplemented with an analysis of a realistic combined configuration.","section":"IV-C, 4K Cryogenic Environment; Table I"}],"minor_comments":[{"comment":"The abstract in the submission metadata includes the phrase 'surpassing the MWPM baseline of 10.3%', but the abstract in the paper body omits it; please reconcile the two versions.","section":"Abstract"},{"comment":"Figure 1 is difficult to read: the 'd=3' annotation and the Chinese characters appear to be artifacts of the source, and the legend is not self-contained. Please clean up the figure.","section":"Fig. 1"},{"comment":"There are several typos, including 'Suface code' in the Section III heading, 'it is easy to implement' in the Introduction, 'constructe' in Section III-C, and 'Larency' in the Fig. 6 legend.","section":"Throughout"},{"comment":"For d=9, the simple decoder has larger area and power (479.34 mm^2, 4.23 W) than the classifier (296.93 mm^2, 2.94 W) despite the classifier having a larger hidden-layer multiplier (n=80 vs. n=35). A sentence explaining this in terms of the output layer size (4*d^2 vs. 4 neurons) would help the reader.","section":"Table II"},{"comment":"The authors state that open-source code is provided in [14], but it is not clear whether the training and testing code of this paper will be released; please clarify the code availability statement.","section":"IV-A"}],"recommendation":"major_revision","confidential_remarks":"The paper's core contribution is the parallelization of an all-FFNN high-level decoder and the CIM-based latency analysis, not the threshold value itself, which is inherited from the PED teacher. I recommend asking the authors to reframe the threshold claims and add the requested stability checks; the current framing overstates the novelty of the accuracy numbers. The paper fits cs.AR/quantum architecture venues, but the comparison issues in Table III and the cryogenic extrapolation need careful attention."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The real contribution here is architectural: the authors replace the non-NN simple decoder in a high-level surface code decoder with an FFNN trained to imitate PED, so both the simple decoder and classifier run in parallel on a CIM platform. That is new and useful. The sub-440ns latency numbers for d=3–9 come from MNSIM simulation rather than silicon, but the simulation is detailed and the non-ideality analysis is honest.\n\nWhat the paper does well is break the serial bottleneck of fully NN high-level decoders. The latency breakdown and the discussion of ADC/DAC and bandwidth bottlenecks are informative. The authors also state plainly that the decoding rules match the PED-based decoder, so they are not claiming a new decoding rule.\n\nThe soft spots are real but addressable. The headline threshold of 14.22% is inherited from PED, not independently established for the trained FFNN. The paper trains at p=0.15, only 0.8 points from the claimed threshold, and shows only d=3–9. With non-monotonic pseudo-thresholds (d=9 at 11.6% below d=7 at 12%), a finite-size crossing is plausible; a stability check at d=11/13 and other training rates is needed before calling it a threshold. Table III also mixes thresholds with pseudo-thresholds, which flatters the comparison. The 4K extrapolation reports 3.98W at d=9; that is on the high side for a 4K stage and needs a stated cooling assumption. Finally, the sub-440ns latency relies on co-achieving several maximum hardware parameters; that is fine as a best-case study, but should be framed as such.\n\nThis paper is for hardware-oriented researchers who care about real-time decoding options. It will not change the theory of surface code decoding, but it provides a concrete architectural data point. A serious referee should engage with the threshold stability and the power analysis; neither is fatal, but both need tightening.\n\nRecommendation: send it to peer review, with explicit requests for larger-distance threshold checks and a corrected comparison table.","headline":"Useful engineering result on CIM-based parallel FFNN decoding, but the headline threshold is inherited from PED and needs stability checks at larger distances.","tokens_in":13401,"tokens_out":2704,"would_cite":false,"duration_ms":24130,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A fully feedforward high-level surface-code decoder can run both modules in parallel on compute-in-memory hardware, reaching a 14.22% decoding threshold and sub-440-nanosecond latencies for distances 3 through 9.","keywords":["surface code decoding","quantum error correction","feedforward neural network","high-level decoder","computing-in-memory","decoding latency","decoding threshold","cryogenic electronics"],"falsifier":"Measure the distance-9 decoder on an actual NVM-based CIM accelerator at 4 K with a 0.4 V supply: if end-to-end latency is above 221 ns, or if total power cannot be removed by the cryostat at 4 K, the cryogenic latency claim fails. Simpler still, rerun the same simulation with any one hardware parameter moved from its maximum to a conservative typical value, such as 1 GHz digital frequency or 64 GB/s inter-tile bandwidth, and check whether latency crosses 440 ns.","tokens_in":12309,"feed_emoji":"⚛️","tokens_out":7341,"duration_ms":60624,"temperature":0.7,"pith_summary":"The paper's central claim is that a high-level surface-code decoder built entirely from feedforward neural networks does not have to run serially. By training one small FFNN to imitate a pure-error decoder and running it alongside a second FFNN classifier on a computing-in-memory (CIM) platform, the two modules execute in parallel, so total latency is set by the slower module rather than their sum. Under a depolarizing noise model the decoder reaches a 14.22% threshold, above the 10.3% minimum-weight perfect matching (MWPM) baseline, with pseudo-thresholds of 10.4% to 12% and simulated latencies of 197 to 252 ns for distances 3, 5, 7, and 9 at room temperature. A 4K cryogenic extrapolation lowers the distance-9 latency to 221 ns. If these numbers hold on real hardware, fully neural decoders become competitive with matching-based decoders on the two metrics that matter for real-time quantum error correction: accuracy and speed.","feed_headline":"Parallel neural network decoder hits 14.22% threshold in under 440 ns","feed_subtitle":"All-neural surface-code decoders ran serially; this one runs two modules in parallel on in-memory chips.","key_machinery":"The load-bearing object is a pair of two-layer feedforward neural networks—a simple decoder and a classifier—each mapping the error syndrome to a fixed-category output, executed in parallel as matrix-vector multiplications on NVM-based compute-in-memory crossbars. A Pure Error Decoder (PED) is used only offline to generate training labels, converting syndrome-to-correction into a one-to-one classification task; the FFNN simple decoder learns to reproduce PED's output, so the decoder keeps PED-level accuracy while dropping PED from the latency path. Parallelism is what breaks the serial bottleneck: latency is max(t_simple, t_classifier), not t_simple + t_classifier. The CIM simulation supplies the hardware parameters—digital frequency, buffer bitwidth, inter-tile and intra-tile bandwidth, and number of ADC/DACs—and captures non-idealities such as stuck-at-faults, finite on/off ratio, and resistance variation.","core_discovery":"The paper establishes that replacing the non-neural simple decoder in a high-level decoder with an FFNN trained on labels generated by a Pure Error Decoder (PED) preserves the PED's decoding accuracy while making the whole decoder parallel and hardware-mappable. The classifier and simple decoder both take the same error syndrome as input and emit respectively the logical error and the data-qubit correction; because neither depends on the other's output, they can run concurrently. On an NVM-based CIM simulator configured with maximum currently available hardware parameters, the decoder achieves a threshold of 14.22% under depolarizing noise and pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% at distances 3, 5, 7, and 9. The simulated latencies are 197.03 ns, 234.87 ns, 243.73 ns, and 251.65 ns at 300K, all below the 440 ns real-time decoding budget; applying cryogenic scaling from a published CIM study at 4K and 0.4 V gives 221.07 ns at distance 9 with 3.98W power. Hardware non-idealities modeled by the simulator change the results by less than 0.5% at the chosen network sizes.","pith_inferences":["The decoder's logical accuracy is inherited from the PED rule used to label training data; the FFNN contribution is hardware acceleration and parallelization, so the 14.22% threshold should be read as 'PED accuracy, made fast,' not as a new decoding algorithm.","The room-temperature and 4K latency numbers assume a single chip simultaneously sustains the maximum values of all five hardware parameters; a real system will likely trade some of them off, so the 440 ns margin should be tested under parameter sweeps rather than only at the maxima.","If the same parallelization is applied to larger distances, the classifier and simple-decoder network widths would grow roughly with distance; whether the 4K cooling budget of a few watts can absorb that growth is an open question the paper does not answer."],"forward_implications":["Distance-3 to distance-9 decoders all complete in under 440 ns at 300K simulation, so a fully neural high-level decoder can meet the real-time QEC pace instead of only offline analysis.","The 14.22% decoding threshold exceeds the 10.3% MWPM baseline under depolarizing noise, and pseudo-thresholds stay above 10% for every tested distance.","Because PED is removed from the runtime path, latency growth with code distance is governed by the FFNN and CIM array sizes, not by exponential lookup or matching growth.","At 4K and 0.4V, the distance-9 latency drops to 221.07 ns and power to 3.98W, supporting the idea that such a decoder could sit inside a cryogenic quantum control stack."],"supporting_citations":[{"why":"Supplies the PED-based high-level decoder, the rule mapping each syndrome to a unique data-qubit error combination, and the 440 ns latency target; its open-source code and CPU/FPGA PED timings are used as baselines.","marker":"[14]"},{"why":"Provides the behavior-level CIM simulator used for all latency, area, power, energy, and hardware non-ideality results.","marker":"[20]"},{"why":"Earlier fully FFNN/CNN high-level decoder that runs serially; supplies the fully-neural serial baseline and the 3.5% threshold comparison.","marker":"[19]"},{"why":"Describes the LUT-based high-level decoder and the depolarizing-noise dataset generation procedure used to produce training and test sets.","marker":"[2]"},{"why":"Measures latency and energy changes of a CIM accelerator from 300K to 4K; its scaling factors are used for the cryogenic extrapolation.","marker":"[36]"},{"why":"Prior CIM-based recurrent-neural-network decoder; provides the closest earlier attempt at neural decoding on CIM hardware and its 0.1% pseudo-threshold.","marker":"[12]"},{"why":"High-bandwidth interconnect design that supplies the 256 GB/s inter-tile bandwidth value used in the latency simulations.","marker":"[30]"},{"why":"High-bandwidth memory specification that supplies the 19,600-bit buffer bitwidth value used in the latency simulations.","marker":"[31]"}],"fun_headline_variants":["Parallel FFNN beats MWPM: 14.22% threshold on CIM","Sub-440 ns surface code decoding with parallel FFNN on CIM","Neural decoder goes parallel, hits 14.22% threshold on CIM","CIM-based parallel FFNN meets 440 ns real-time decoding budget","14.22% threshold and sub-440 ns latencies with parallel FFNN"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The central assumption is that a single real CIM chip can simultaneously run at the maximum values assumed for every hardware parameter (about 2 GHz digital clock, 256 GB/s inter-tile bandwidth, 19,600-bit buffers, and up to 256 ADC/DACs) and that the published 300K-to-4K scaling of a smaller cryogenic CIM chip transfers unchanged to a decoder that dissipates about 4 W at distance 9.","fun_headline_variants_meta":{"raw":{"variants":["Parallel FFNN beats MWPM: 14.22% threshold on CIM","Sub-440 ns surface code decoding with parallel FFNN on CIM","Neural decoder goes parallel, hits 14.22% threshold on CIM","CIM-based parallel FFNN meets 440 ns real-time decoding budget","14.22% threshold and sub-440 ns latencies with parallel FFNN"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000817,"raw_usage":{"total_tokens":3667,"prompt_tokens":1119,"completion_tokens":2548,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":735,"completion_tokens_details":{"reasoning_tokens":2446}},"tokens_in":735,"tokens_out":2548,"duration_ms":14880,"temperature":1.0,"reasoning_tokens":2446,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T11:31:26.021255+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the distance-9 decoder on an actual NVM-based CIM accelerator at 4 K with a 0.4 V supply: if end-to-end latency is above 221 ns, or if total power cannot be removed by the cryostat at 4 K, the cryogenic latency claim fails. Simpler still, rerun the same simulation with any one hardware parameter moved from its maximum to a conservative typical value, such as 1 GHz digital frequency or 64 GB/s inter-tile bandwidth, and check whether latency crosses 440 ns.","supporting_citations":[{"cited_title":"Neural-network de- coders for quantum error correction using surface codes: A space explo- ration of the hardware cost-performance tradeoffs,","cited_arxiv_id":null,"evidence_quote":"Supplies the PED-based high-level decoder, the rule mapping each syndrome to a unique data-qubit error combination, and the 440 ns latency target; its open-source code and CPU/FPGA PED timings are used as baselines."},{"cited_title":"Mnsim 2.0: A behavior-level modeling tool for processing- in-memory architectures,","cited_arxiv_id":null,"evidence_quote":"Provides the behavior-level CIM simulator used for all latency, area, power, energy, and hardware non-ideality results."},{"cited_title":"Efficient Decoding of Surface Code Syndromes for Error Correction in Quantum Computing","cited_arxiv_id":"2110.10896","evidence_quote":"Earlier fully FFNN/CNN high-level decoder that runs serially; supplies the fully-neural serial baseline and the 3.5% threshold comparison."},{"cited_title":"Comparing neural network based decoders for the surface code,","cited_arxiv_id":null,"evidence_quote":"Describes the LUT-based high-level decoder and the depolarizing-noise dataset generation procedure used to produce training and test sets."},{"cited_title":"Cryo- genic performance for compute-in-memory based deep neural network accelerator,","cited_arxiv_id":null,"evidence_quote":"Measures latency and energy changes of a CIM accelerator from 300K to 4K; its scaling factors are used for the cryogenic extrapolation."},{"cited_title":"Nvidia grace hopper superchip architecture,","cited_arxiv_id":null,"evidence_quote":"High-bandwidth memory specification that supplies the 19,600-bit buffer bitwidth value used in the latency simulations."}],"review_version":1}