{"id":"6ad2446b-14dd-4260-b27e-405385417c29","arxiv_id":"2411.18354","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"A bit-insertion formula for controlled-gate iteration indices reduces scheduled kernel iterations, giving up to about 7x speedup for control-heavy circuits on FPGAs.","lead":"This paper presents a formula for scheduling only the memory updates needed by controlled quantum gates in full-state-vector simulation, so every scheduled iteration does useful work. On FPGAs this removes wasted clock cycles and, for control-heavy circuits, cuts simulation time by up to about 7x compared with the baseline.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Energy-efficiency claim rests on unmeasured rated power; if the FPGA board draws more than roughly 63W during the streaming run, the claimed win over the GPU reverses.","rationale":"The reader's weakest assumption is the rated-power basis of the energy comparison, and I agree that is the load-bearing issue. I spent most of the stress-test effort trying to break Eq. 5, because the entire scheduling contribution depends on it; manual and small-n checks over mixed target/control configurations, including controls both below and above the target and multiple controls, all reproduce exactly the set of global iteration indices that satisfy the control conditions, so the formula appears correct. The missing proof is a gap, but I did not find a counterexample. The energy claim is different: it has a concrete failure mechanism. The FPGA's 25W is a board rating rather than a measured draw, and the streaming-circuit win over the GPU hinges on the board averaging under roughly 63W; no measurement shows this. Using TDP values for CPU and GPU likely overstates their real consumption, especially under a single-compute-unit workload, so the comparison may be biased in the FPGA's favor. This does not invalidate the scheduling contribution, and it is empirically fixable, so the reader's CONDITIONAL verdict should stand unchanged.","tokens_in":9230,"tokens_out":18662,"duration_ms":172759,"concrete_test":"Measure the average AC power draw of each platform during the 29-qubit streaming run using a calibrated wattmeter or the FPGA board's power-monitoring interface, run the circuit at least three times, and recompute Table IV energy as time times measured mean power. The decisive threshold is whether the FPGA board's measured average power exceeds about 63W: if it does, the optimized FPGA no longer beats the GPU on streaming energy, and if the CPU or GPU draw substantially less than their 160W/250W ratings, their energy numbers improve correspondingly.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's headline energy result is computed in Section IV by multiplying measured runtimes by unmeasured rated power values: 25W for the FPGA, 160W for the CPU, and 250W for the GPU. This is not a harmless normalization. In Table IV, the optimized FPGA completes the 29-qubit streaming circuit in 3.78s and the GPU in 0.95s; with rated power the FPGA energy is 94.4J versus 238.3J for the GPU. The FPGA win therefore disappears if the FPGA board (FPGA, DDR3, PCIe interface) draws more than about 63W on average during the run, and no measurement is provided to show it stays below that threshold. Conversely, the CPU and GPU figures use thermal design power, which is a worst-case rating; running a single OpenCL compute unit likely draws less, so the comparison is probably biased in the FPGA's favor. The paper reports no wattmeter measurements, no on-board power monitoring, no repeated runs, and no error bars, so the claim that the FPGA outperforms both CPU and GPU in energy efficiency is not established at the claimed confidence. The scheduling formula itself, Eq. 5, appears sound in the configurations I checked, but the energy claim is the less secure link in the headline result.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a scheduling optimization for full-state-vector simulation of quantum circuits on FPGAs. Instead of always scheduling 2^(n-1) iterations for an n-qubit gate, the authors propose Eq. (5), an index-mapping formula that maps a reduced iteration set [0, 2^(n-nc-1)-1] to the global iteration set, taking into account the gate's control qubits. This reduces the number of scheduled kernel iterations that perform memory accesses to only those required by the controlled gate. The method is evaluated on three circuit families (QFT, squaring, streaming) using FPGA, CPU, and GPU OpenCL implementations. The reported results show speedups up to about 7x for the streaming circuit on the FPGA and, under the paper's energy model, the FPGA is claimed to outperform CPU and GPU in energy efficiency for that circuit.","tokens_in":9445,"tokens_out":2436,"duration_ms":25510,"significance":"If the scheduling formula and its generalization hold, the contribution is practically useful: it is a parameter-free transformation that removes wasted memory-access scheduling for controlled gates on FPGAs, while leaving resource usage essentially unchanged (Table I). The paper has the strength of implementing the method in a real OpenCL kernel and evaluating it on nontrivial circuits. However, the headline energy-efficiency claim is not established by the data as presented, because it relies on unmeasured rated power values rather than actual power measurements, and the generalization of Eq. (5) from small examples to arbitrary n and control sets is asserted without proof. The core scheduling idea is credible and worth publishing after these concerns are addressed.","major_comments":[{"comment":"The energy-efficiency claim is not supported by the evidence. The paper computes energy as measured runtime multiplied by rated power: 25 W for the FPGA, 160 W for the CPU, and 250 W for the GPU. No wattmeter measurements, on-board power monitoring, or repeated runs are reported. For the 29-qubit streaming circuit (Table IV), the FPGA advantage over the GPU disappears if the FPGA board draws more than roughly 63 W on average, and the rated-power values for CPU/GPU are likely worst-case thermal design powers. Thus the conclusion that the FPGA 'allows to outperform both CPU and GPU platforms in terms of energy efficiency' is not established at the claimed confidence.","section":"Section IV, Tables II-IV"},{"comment":"Eq. (5) is the core contribution, but the paper provides only worked examples for 3- and 4-qubit registers. There is no general proof that the iterative formula is a bijection from [0, 2^(n-nc-1)-1] to the subset of global iteration indices that satisfy the controls, for arbitrary n, arbitrary target qubit t, and arbitrary ascending control sets. Since the correctness of the entire optimization depends on this mapping, a proof or at least a rigorous inductive argument is needed.","section":"Section III-B, Eq. (5)"},{"comment":"The abstract and conclusion state that the approach 'allows to outperform both CPU and GPU platforms in terms of energy efficiency.' The data in Tables II and III show that the GPU has lower energy than the FPGA for both the QFT and the squaring circuits; the claimed advantage appears only for the streaming circuit. The paper should either restrict the claim to the streaming case or provide a broader energy evaluation supporting the general statement.","section":"Abstract and Conclusion"}],"minor_comments":[{"comment":"The affiliation 'University of Glagow' appears to be a typo for 'University of Glasgow'; this should be corrected.","section":"Author affiliations"},{"comment":"In Eq. (2) the summation runs from k=0 to 2^n, but for an n-qubit state vector the index range should be 0 to 2^n - 1. This is likely a typo.","section":"Eq. (2)"},{"comment":"The displayed equation uses floor notation, but the worked examples write expressions like '0/1 + 1' without floor brackets. It would be clearer to explicitly use integer division or floor notation in the examples.","section":"Eq. (5) and surrounding text"},{"comment":"The statement that the architecture 'could run on up to 4x smaller FPGA' and thereby achieve better energy efficiency is speculative, since no resource or power measurements for such a device are provided.","section":"Section IV-D"},{"comment":"The sentence 'which again can is verified by the figure' contains a grammatical error; it should read 'which can again be verified by the figure.'","section":"Figure 4"}],"recommendation":"major_revision","confidential_remarks":"The paper's main technical idea is interesting and likely correct for the demonstrated cases, but the energy claim is the weakest link and the missing formal correctness proof for Eq. (5) is a significant gap. A revision that supplies actual power measurements (or clearly labels the energy results as estimates under rated power) and a proof or rigorous argument for the mapping would make the paper suitable for publication."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The scheduling trick is real and the speedups on control-heavy circuits are credible, but the energy-efficiency headline leans on rated power rather than measured watts, and the index-mapping formula is a known bit-deposit operation in new clothing.\n\nThe paper does something useful: on FPGAs, checking controls at runtime wastes statically scheduled memory cycles. Their Eq.5 maps a reduced iteration index to the full index so that only iterations that will actually update memory are scheduled. The resource cost is negligible, and the measured speedups—roughly 2x on squaring, almost 7x on streaming—are consistent with the idea. The authors also correctly note that the extra indexing can make a CPU slower, which is the kind of honest result you want to see.\n\nThe soft spots are mostly in the energy claim. They multiply measured times by fixed rated powers: 25W for the FPGA, 160W CPU, 250W GPU. No wattmeter data. The streaming circuit is the only case where the FPGA beats the GPU, and that win reverses if the FPGA board draws more than about 63W on average. A board with DDR3 and PCIe could easily exceed that. Conversely, CPU and GPU TDP numbers likely overstate what a single OpenCL compute unit draws. So the paper's abstract-level claim that FPGAs 'outperform both CPU and GPU platforms in terms of energy efficiency' is not established. The circuit selection is also tilted: the streaming circuit is described as a best case.\n\nOn novelty, Eq.5 is equivalent to pdep (parallel bit deposit), the standard way to enumerate indices that satisfy a bitmask. Calling it a new memory access pattern overstates the math. The contribution is the application to FPGA static scheduling, which is a legitimate extension and worth publishing, but it is not a conceptual breakthrough.\n\nOther gaps: no general proof of Eq.5 (an induction would be trivial), no repeated runs or error bars, no released code or data. These are fixable.\n\nWho this is for: people implementing full-state-vector simulators on FPGAs, and anyone tracking energy claims in hardware acceleration. With measured power, a short proof, and error bars, it would be a solid paper. Even without those, the core scheduling idea is sound. I would send it to peer review—a serious referee should push on the power measurements and the proof, but the work deserves that attention. I would not cite it in my own work, because the math is standard and the energy claim is still open.","headline":"Scheduling trick is real and the speedups are credible, but the energy-efficiency headline leans on unmeasured power ratings and the core index-mapping formula is a known bit-deposit operation.","tokens_in":9967,"tokens_out":4149,"would_cite":false,"duration_ms":38724,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper claims that an index-mapping formula can schedule exactly the memory iterations a controlled quantum gate needs, delivering up to 7x faster FPGA simulation on circuits with many controls.","keywords":["quantum circuit simulation","FPGA acceleration","full-state-vector simulation","controlled quantum gates","iteration scheduling","memory access pattern","energy efficiency"],"falsifier":"For a register of $n=5$ to $n=10$ qubits, enumerate every target qubit and every strictly ascending control set, run the optimised kernel on a random state vector, and compare the exact pairs read and written against a reference kernel that checks controls directly; any mismatch would falsify the central claim. In parallel, measure the FPGA board's real power draw during the 29-qubit streaming circuit; if the measured energy no longer beats the CPU and GPU totals, the energy-efficiency conclusion fails.","tokens_in":1741,"feed_emoji":"⚡","tokens_out":4017,"duration_ms":122616,"temperature":0.7,"pith_summary":"This paper claims that an FPGA quantum simulator can run much faster by scheduling only the memory iterations that a gate actually needs, with the gate's control qubits taken into account. The standard kernel schedules $2^{n-1}$ pair accesses for every gate and then tests whether each pair satisfies the controls; on an FPGA those tests leave statically scheduled memory cycles unused. The paper derives an index-mapping formula, Equation 5, that sends each index in the reduced set $[0,2^{n-n_c-1}-1]$ to its correct global iteration index, where $n_c$ is the number of controls on the gate. As a result the control-flow guard can be removed and every scheduled iteration performs a useful memory access. The authors report almost $2\\times$ lower simulation time on squaring circuits and almost $7\\times$ on streaming circuits, and they argue this makes FPGA simulation competitive with CPU and GPU platforms in energy efficiency, which is the main constraint on scaling full-state-vector simulation.","feed_headline":"FPGA quantum simulators run up to 7x faster","feed_subtitle":"Scheduling only the amplitude pairs a controlled gate needs cuts FPGA simulation time by nearly 7x on streaming circuits.","key_machinery":"The central object is the iteration index set of a gate: the list of indices fed to the pair-indexing function that locates the two amplitudes to read and write. The baseline set is $I_g=[0,2^{n-1}-1]$; the optimised set is $I_r=[0,2^{n-n_c-1}-1]$, and the load-bearing identity is Equation 5, the iterative skip map built from adjusted control positions and skip intervals $2^{c_{\\mathrm{adj}}}$. Its job is to reconstruct the unique global iteration index for each reduced index, replacing a dynamic control-flow check with static integer arithmetic. Because FPGA memory cycles are scheduled statically, this substitution is what turns skipped iterations into time savings rather than wasted clock cycles.","core_discovery":"The central discovery is that the pair of amplitudes touched by a controlled gate is completely determined by a closed-form map from the reduced iteration set to the global iteration set. For each control qubit $c$, the paper defines an adjusted control $c_{\\mathrm{adj}}=c-1$ when $c>t$ and $c_{\\mathrm{adj}}=c$ otherwise, and the skip interval $2^{c_{\\mathrm{adj}}}$; the map is applied iteratively, once per control, in strictly ascending control order, using $i_{r_k}=i_{r_{k+1}}+(\\lfloor i_{r_{k+1}}/2^{c_{\\mathrm{adj}}}\\rfloor+1)2^{c_{\\mathrm{adj}}}$. This sends every index of $[0,2^{n-n_c-1}-1]$ to the unique index of $[0,2^{n-1}-1]$ that the baseline kernel would need, so the runtime check on controls can be dropped. The paper demonstrates the pattern on 3- and 4-qubit access tables and reports FPGA time reductions of roughly $2\\times$ for QFT and squaring circuits and $7\\times$ for streaming circuits, with the optimised kernel using essentially the same FPGA resources as the baseline.","pith_inferences":["A natural extension is to apply the same skip map to negative controls, where the control condition is satisfied by $|0\\rangle$ rather than $|1\\rangle$; the access-pattern symmetry in Figure 4 suggests the formula would only change which global indices are selected.","The formula's correctness is shown by exhaustive small-register patterns rather than a proof, so an independent check over all targets and ascending control sets for $n=5$ through $n=10$ would directly test whether it generalises.","Because the reduced iteration count shortens the serial gate schedule itself, combining this optimisation with multiple compute units, gate fusion, or fixed-point arithmetic should compound the savings rather than merely add to them.","The energy comparison multiplies measured runtimes by rated power values, so a direct power measurement on the FPGA board during the streaming circuit would show whether the claimed energy advantage over CPU and GPU holds under real operating conditions."],"forward_implications":["For a gate with $n_c$ controls, scheduled iterations fall from $2^{n-1}$ to $2^{n-n_c-1}$, so each additional control halves the work the simulator performs.","On FPGAs, where memory-access cycles are statically scheduled, the removed guard time translates directly into wall-clock gains: the paper measures almost $2\\times$ for QFT and squaring circuits and almost $7\\times$ for streaming circuits.","The optimised kernel uses nearly the same FPGA resources as the baseline and runs at a slightly higher maximum frequency, so the speedup is obtained without an area cost.","Energy per simulation falls in the same proportion as time under the rated-power model; in the streaming case the FPGA's total energy is below both the CPU and GPU totals reported by the authors.","Because streaming circuits contain gates with up to $n-1$ controls, they demonstrate the method's best case; any circuit dominated by multi-controlled gates would inherit this benefit."],"supporting_citations":[{"why":"Supplies the ithCleared pair-indexing function and the kernel template that the optimised schedule modifies.","marker":"[7]"},{"why":"Provides the squaring circuits used as a benchmark and the earlier comparison context for FPGA simulation.","marker":"[13]"},{"why":"Supplies the controlled ripple-carry adder that gives the squaring circuits their multi-control gates.","marker":"[4]"},{"why":"Provides the streaming circuit with up to n-1 controls, the best-case benchmark for the optimisation.","marker":"[20]"},{"why":"Provides the FPGA power rating used in the energy-efficiency calculation.","marker":"[15]"}],"fun_headline_variants":["FPGA quantum sims run up to 7x faster with new scheduling","Closed-form iteration map accelerates FPGA quantum simulation","Skipping redundant pairs speeds FPGA quantum simulation","New iteration map delivers 7x speedup on FPGA quantum circuits"],"cache_read_input_tokens":12160,"weakest_assumption_plain":"The argument depends on the unproven pattern claim that Equation 5 maps the reduced iteration set to the correct global iteration set for every target qubit and every strictly ascending control set; if any configuration gives the wrong global index, the optimised kernel would read and write the wrong amplitude pairs.","fun_headline_variants_meta":{"raw":{"variants":["FPGA quantum sims run up to 7x faster with new scheduling","Closed-form iteration map accelerates FPGA quantum simulation","Skipping redundant pairs speeds FPGA quantum simulation","New iteration map delivers 7x speedup on FPGA quantum circuits"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001204,"raw_usage":{"total_tokens":5029,"prompt_tokens":1083,"completion_tokens":3946,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":699,"completion_tokens_details":{"reasoning_tokens":3878}},"tokens_in":699,"tokens_out":3946,"duration_ms":22369,"temperature":1.0,"reasoning_tokens":3878,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T11:17:14.936675+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"For a register of $n=5$ to $n=10$ qubits, enumerate every target qubit and every strictly ascending control set, run the optimised kernel on a random state vector, and compare the exact pairs read and written against a reference kernel that checks controls directly; any mismatch would falsify the central claim. In parallel, measure the FPGA board's real power draw during the 29-qubit streaming circuit; if the measured energy no longer beats the CPU and GPU totals, the energy-efficiency conclusion fails.","supporting_citations":[{"cited_title":"Simulating Quantum Computers Using OpenCL","cited_arxiv_id":"1805.00988","evidence_quote":"Supplies the ithCleared pair-indexing function and the kernel template that the optimised schedule modifies."},{"cited_title":"Investigating hardware acceleration for simulation of CFD quantum circuits","cited_arxiv_id":null,"evidence_quote":"Provides the squaring circuits used as a benchmark and the earlier comparison context for FPGA simulation."},{"cited_title":"Todorova and Ren ´e Steijl","cited_arxiv_id":null,"evidence_quote":"Provides the streaming circuit with up to n-1 controls, the best-case benchmark for the optimisation."},{"cited_title":"High level programming of FPGAs for HPC and data centric applica- tions","cited_arxiv_id":null,"evidence_quote":"Provides the FPGA power rating used in the energy-efficiency calculation."}],"review_version":1}