{"id":"7d54ede3-c7cc-4da6-9412-20bf0b3f74a8","arxiv_id":"2411.18566","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"OASIS-UROS is an open-source 8-channel IEPE data acquisition system sampling at 36 kHz, validated to match a commercial system's eigenfrequencies within 0.27% in modal analysis.","lead":"This paper presents OASIS-UROS, a low-cost open-source data acquisition system for vibration sensors, built around an ESP32 microcontroller and an 18-bit ADC. The authors validate it against a commercial system in a modal analysis test, finding close agreement for eigenfrequencies and mode shapes up to about 3 kHz.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Unquantified PWM sampling-clock accuracy is the load-bearing unknown: the 'no significant differences up to 3 kHz' claim presumes an accurate time base, which the authors explicitly leave unresolved.","rationale":"The reader's weakest assumption identifies exactly the issue I find most load-bearing: the accuracy of the PWM-generated sampling clock is unknown and is explicitly flagged by the authors as unresolved. The central claim that OASIS-UROS is a viable low-cost alternative for experimental modal analysis depends on the FRF comparison being a valid measure of acquisition-system performance. A systematic sampling-clock error would corrupt the time axis, affecting eigenfrequency estimates and FRF phase/coherence in a way that could explain the deviations observed above 3 kHz and could also bias the sub-3 kHz agreement that the paper emphasizes. The paper provides extensive documentation, open-source design files, and raw measurement data, which is commendable, and the validation is honestly described with known confounds (different impacts, windows, and modal identification algorithms). However, the clock question is not resolved by the data presented, and the paper's own statement in Section 8.2 leaves it as an open risk. Therefore, the CONDITIONAL verdict is appropriate: the 'close performance' claim should be accepted only if the sampling-clock accuracy and stability are characterized. My read does not change the reader's verdict; it reinforces it. No ad hominem or manufactured issue is intended; this is a concrete, technically checkable assumption that the authors themselves acknowledge. The proposed test—a simultaneous reference-signal measurement or direct PWM frequency counting—would settle the concern directly and could be reported as a short addendum.","tokens_in":22784,"tokens_out":4807,"duration_ms":48359,"concrete_test":"Perform a simultaneous, split-signal validation: connect a precision function generator (or the LMS system's calibrated output) to one OASIS-UROS channel and one LMS channel, record a stable sine wave (e.g., 1 kHz and 5 kHz) with both systems at their nominal sample rates, and estimate the observed frequency from the recorded time series (e.g., via a sine-fit or high-resolution FFT peak). If the OASIS-estimated frequency deviates from the reference by more than 0.05% (or the specified crystal tolerance), the sample-rate error is large enough to bias the FRF frequency axis and would compromise the claimed agreement up to 3 kHz. Alternatively, probe the PWM output (ADC CONVST) with a frequency counter referenced to a calibrated timebase while OASIS is sampling at 25.6 kHz and record the Allan deviation to characterize both offset and jitter.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that OASIS-UROS 'performs close to the commercial one in some aspects' rests on the FRF comparison in Section 8. The time base of every OASIS measurement is set by the ESP32-S3 hardware PWM that generates the ADC CONVST signal; any frequency offset or jitter in this clock directly scales the frequency axis and adds frequency-dependent phase error. The paper states in Section 8.2: 'Whether this can be traced back to inaccuracies of the sampling frequency of OASIS-UROS is currently unknown.' This is the weakest load-bearing link. If the actual sample rate differs from the nominal 25.6 kHz by even 0.1%, a mode at 3 kHz shifts by 3 Hz, which is larger than the 0.27% eigenfrequency deviations reported in Table 7. The authors attempt to rule out a clock error by noting that higher modes do not show a consistent frequency shift, but this is a heuristic argument confounded by different modal-fit algorithms (PolyMAX vs. pLSCF/LSFD), different windows (exponential window applied only to OASIS), and different impact realizations. Moreover, the observed phase rise above 3 kHz could be caused by a time delay or clock jitter that is not visible in the eigenfrequency comparison. Without an independent measurement of the sampling-clock frequency and stability, the 'close performance' claim below 3 kHz is not quantitatively bounded, and the whole FRF-based validation is conditional on an unverified hardware assumption. The rest of the paper is honest about this gap, but the gap is load-bearing because it affects the validity of the primary metric used to support the central claim.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents OASIS-UROS, an open-source data acquisition system for IEPE sensors, building on a previous OASIS design. It documents the hardware (ESP32-S3 microcontroller, AD7606C-18 ADC, IEPE front-end), the firmware, a Python GUI, build instructions, and a bill of materials. The system is validated in an experimental modal analysis test case against a commercial Siemens LMS Scadas system, comparing frequency response functions (FRFs), eigenfrequencies, damping ratios, and mode shapes. The authors claim that OASIS-UROS performs close to the commercial system in some aspects for the utilized test case, with no significant FRF differences up to 3 kHz.","tokens_in":23062,"tokens_out":6640,"duration_ms":54441,"significance":"If the claims hold, the paper provides a valuable low-cost, fully open-source alternative for multi-channel IEPE acquisition, with detailed reproducibility materials (KiCad files, firmware, GUI, validation data, and analysis scripts). The eigenfrequency agreement (within 0.27%) and mode-shape correlation (Cross-MAC near unity for most modes) are encouraging. The paper is honest about several limitations, including the unresolved sampling-clock accuracy and the confounding factors in the comparison. The main risk is that the sampling-clock accuracy is unquantified despite being load-bearing for the FRF comparison; this is fixable with a direct measurement and does not invalidate the archival value of the hardware/software documentation.","major_comments":[{"comment":"The sampling clock accuracy is load-bearing and explicitly unresolved: the authors state 'Whether this can be traced back to inaccuracies of the sampling frequency of OASIS-UROS is currently unknown.' The time base of every OASIS measurement is determined by the ESP32-S3 hardware PWM that generates the ADC CONVST signal. Any frequency offset or jitter in this clock directly scales the frequency axis and adds frequency-dependent phase error. The claim of 'no significant differences up to 3 kHz' is therefore not quantitatively bounded. The authors should measure the actual sampling frequency (e.g., with a frequency counter or by recording a known reference sine wave) and report the deviation and its effect on the FRF phase and eigenfrequency estimates.","section":"Section 8.2"},{"comment":"The FRF comparison simultaneously varies multiple factors: different impacts with different force spectra (Fig. 19), different sample rates (25.6 kHz for OASIS vs 51.2 kHz for LMS), different analysis software (pyFRF vs Simcenter Testlab), and different windows (exponential window applied only to OASIS, with uncorrected energy loss). Consequently, observed differences such as the phase rise above 3 kHz cannot be attributed specifically to the OASIS acquisition hardware. A more controlled comparison—for example, recording the same transducer signals through a splitter or at least using the same excitation data—would be necessary to substantiate the 'close performance' claim quantitatively.","section":"Section 8.2"},{"comment":"The summary statement 'for frequencies up to 3 kHz, no significant differences were observable in the FRFs' is not consistent with the acknowledged reduced amplitudes of the OASIS FRFs due to the uncorrected exponential window (Section 8.2). The magnitude offset is a systematic difference, not a negligible effect. The claim should either be qualified (e.g., 'apart from a scale factor and increased noise') or the window should be corrected (or its effect quantified). Without this, the claim overstates the agreement.","section":"Section 8.3"},{"comment":"The eigenfrequency comparison is used to argue against a sampling-clock offset (modes 8-10 show smaller deviations, suggesting no consistent frequency shift), but this heuristic is confounded by the different modal fit algorithms (PolyMAX vs pLSCF/LSFD), different analysis bands, and different windowing applied to OASIS data. A direct measurement of the sampling clock or a comparison using a known-frequency source would provide a far stronger test. Additionally, the damping ratios differ by up to 0.51% absolute (modes 4 and 8), which is likely related in part to the exponential window; this should be discussed quantitatively rather than left as an unexplained discrepancy.","section":"Section 8.3, Table 7"}],"minor_comments":[{"comment":"The figure legends contain placeholder text 'Draft ... Commit SHA: DUMMY SHA File - RUN COMPILE ON GitLab!' which should be removed or replaced with proper captions before publication.","section":"Figures 19-21"},{"comment":"The cache selection logic is described inconsistently: first it says 'If the number is odd ... the data is written to OASISCacheA', then 'If CachePage is odd, then OASISCacheB is used.' The second sentence should presumably read 'If CachePage is even'.","section":"Section 3.2"},{"comment":"The voltage conversion uses BitDivider = 2^17; for an 18-bit ADC with a sign bit, the maximum positive code is 2^17-1, so the formula introduces a small gain error at full scale. Clarify the exact code mapping or reference the datasheet to confirm the intended scaling.","section":"Section 3.3, Eq. (1)"},{"comment":"The statement that a sampling frequency of 36 kHz is achievable 'with x16 oversampling' should be reconciled with the ADC throughput table (Table 5) and the abstract's 'up to 36 kHz' phrasing. Specify the oversampling setting used at 36 kHz and any limitations.","section":"Section 7.3"},{"comment":"In the 'Set oversampling factor' command description, the text says 'Sets the voltage range on a per-channel basis'; this appears to be a copy-paste error and should be corrected to 'oversampling factor'.","section":"Appendix A"}],"recommendation":"major_revision","confidential_remarks":"The paper is essentially a hardware/software documentation paper with a validation demonstration. The central claim is modest, but the validation is currently conditional on an unmeasured sampling-clock accuracy, which is explicitly admitted. This is fixable and does not require a redesign of the presented hardware/software. The placeholder text in figures suggests an early draft; the paper needs a careful revision before it can be accepted."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is a well-documented, honest open-hardware paper, and the main risk flagged by the stress-test—unquantified PWM sampling-clock accuracy—is real but not as load-bearing as stated. The paper's own eigenfrequency table actually argues against a constant clock error: modes 8–10 deviate by 0.04%, 0.02%, and 0.01%, and the deviations are not all one sign. If the sample rate were off by 0.1%, you would expect a systematic shift that grows with frequency. That does not prove the clock is perfect, but it weakens the claim that the whole FRF comparison is conditional on an unverified hardware assumption.\n\nWhat is genuinely new: a complete open-source IEPE acquisition system—eight simultaneous 18-bit channels at up to 36 kHz, SD-cache streaming, rewritten ESP32-S3 firmware—plus full KiCad files, BOM, build instructions, and an open validation dataset with Python scripts. The comparison against a Siemens LMS Scadas system is real experimental work, and the eigenfrequency agreement (within 0.27%) and MAC values are credible evidence that the system works for basic EMA. The paper earns credit for shipping reproducible artifacts and for being explicit about confounds.\n\nSoft spots: the validation entangles hardware, software, impact realization, sample rate, and windowing. The exponential window applied only to OASIS is uncorrected, so FRF magnitudes are lower; damping differences up to 0.51 percentage points are unexplained. The \"no significant differences up to 3 kHz\" claim is visual, not quantitative. And yes, the PWM clock accuracy is unknown—the authors say so in Section 8.2. That should be fixed with a simple characterization: measure the actual sample rate against a known reference and report jitter. But it is a gap in an otherwise usable validation, not a reason to reject.\n\nWho this is for: teaching labs, small companies, and researchers who want a low-cost, inspectable DAQ for vibration work. A serious referee should engage. Recommended revision: add clock measurement, tighten the validation by using same impacts (e.g., recorded signal playback) or at least same window settings, and quantify the 3 kHz FRF agreement.","headline":"Solid open-hardware paper with honest validation; the sampling-clock unknown is a fixable gap, not a fatal flaw.","tokens_in":23617,"tokens_out":3319,"would_cite":false,"duration_ms":31328,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Open-source DAQ matches commercial system to 3 kHz","keywords":["open-source hardware","IEPE sensors","data acquisition","experimental modal analysis","ESP32-S3","AD7606C-18","frequency response function","SD card caching"],"falsifier":"Split the same IEPE accelerometer signal between OASIS-UROS and a reference DAQ, drive the structure with a known 5 kHz tone, and compare the measured frequency and phase over a 10-second record; if OASIS-UROS reports a frequency error above about 0.1% or a progressive phase lag above 3 kHz that the reference does not, the PWM sampling clock is inaccurate and the close-agreement claim fails.","tokens_in":22589,"feed_emoji":"🎛️","tokens_out":7454,"duration_ms":62371,"temperature":0.7,"pith_summary":"OASIS-UROS is an open-source, eight-channel data acquisition system for IEPE vibration sensors that can be built for roughly $220 (€200). The paper documents the hardware, firmware, and GUI, then validates the system by comparing frequency response functions and modal parameters with a commercial acquisition system on an instrumented aluminum beam. Up to 3 kHz, the FRFs show no significant differences; eigenfrequencies match within 0.27% for modes up to 8 kHz, and mode shapes agree closely (near-unity MAC values), though damping ratios differ more. The authors conclude that while OASIS-UROS cannot match full commercial performance, it is a viable alternative for students, academics, and small companies with constrained budgets or the need for full insight into and adaptability of the hardware and software.","feed_headline":"Open-source DAQ matches commercial system to 3 kHz","feed_subtitle":"A $220 eight-channel IEPE recorder reproduces commercial modal frequencies within 0.3 percent.","key_machinery":"The load-bearing piece is the synchronous sampling chain: a hardware PWM signal from the ESP32-S3 sets the sampling frequency and triggers the AD7606C-18 ADC; on the ADC's BUSY falling edge a GPIO interrupt reads all eight channels' bits simultaneously through Octal SPI, an SPI variant using eight data lines, into a GPIO register; and the sample bytes are stored in one of two RAM caches while the second core writes the previous cache page to a microSD card. This double-buffered caching is what allows 18-bit, eight-channel acquisition at up to 36 kHz without a FIFO or PC streaming. Voltage reconstruction follows the AD7606C-18 bipolar transfer function, using the MSB as sign bit and dividing the remaining bits by $2^{17}$.","core_discovery":"The central claim is that a fully open, reproducible acquisition chain—hardware, firmware, and Python GUI—can deliver measurement quality close to a commercial system for experimental modal analysis. On a stiff aluminum beam excited by an automatic impact hammer, the OASIS-UROS system and a commercial reference system produced FRFs with essentially no observable differences up to 3 kHz. Modal eigenfrequencies extracted from 1–8 kHz differed by at most 0.27% (about 7 Hz on a 2.7 kHz mode), and the Cross-MAC values between the identified mode shapes were near unity except for one mode, while damping ratios showed larger absolute differences. The paper therefore positions OASIS-UROS as a low-cost, fully transparent alternative for teaching and small-scale applications, not as a replacement for high-end commercial hardware.","pith_inferences":["A stricter validation would split one analog IEPE signal into OASIS-UROS and the reference system simultaneously; if the phase and coherence deviations above 3 kHz persist under identical excitation, they come from the acquisition hardware, not from the different impact sets used in the paper.","The observed high-frequency phase rise and coherence drop are consistent with a small error in the PWM-derived sampling clock; if that is the cause, a calibrated or temperature-compensated clock could extend the usable bandwidth beyond 3 kHz, a testable firmware change.","The double-buffered SD writing implies a trade-off: for a fixed SD card, raising the oversampling factor lowers the sustainable sampling rate, so the quoted 36 kHz figure applies to low oversampling; this is a direct consequence of the caching design.","If the hardware and firmware are adopted by the community, reproducibility of the validation could be checked by ordering the same bill of materials and rerunning the beam test; the paper provides the manufacturing files, dataset, and scripts, so this is a concrete next step."],"forward_implications":["For FRF-based analyses below 3 kHz, OASIS-UROS can stand in for a commercial system in this class of test case, making modal analysis accessible in teaching labs.","Up to 8 kHz, identified eigenfrequencies stay within about 0.3% of the commercial reference, so the system is usable for mode tracking in that range.","Above roughly 4 kHz, FRF magnitude and phase deviate noticeably, so applications like substructuring that invert FRF matrices should not assume OASIS-UROS accuracy there without separate validation.","Because sampling time is limited only by SD card capacity, the system can record long-duration or triggered measurements with pre-trigger data without a live PC connection.","Users can adjust voltage ranges, oversampling, and trigger levels per channel, and combine the recorded data with open-source modal analysis software, giving a fully open workflow."],"supporting_citations":[{"why":"Supplies the hardware project files, manufacturing files, firmware, and GUI source needed to reproduce the board.","marker":"[1]"},{"why":"Provides the open-source modal identification routines used to extract modes from the OASIS measurement data.","marker":"[2]"},{"why":"Documents the previous OASIS version whose design and firmware this work extends, including the move to a hardware PWM sampling clock.","marker":"[3]"},{"why":"AD7606C-18 datasheet that specifies the ADC timing, oversampling modes, voltage ranges, and transfer function used throughout the paper.","marker":"[4]"},{"why":"Supplies the open-source frequency response function estimation code used to compute the OASIS FRFs.","marker":"[8]"},{"why":"Provides the validation measurement data and Python processing script, making the comparison reproducible.","marker":"[9]"},{"why":"Motivates why high-frequency FRF errors matter for applications like substructuring that require FRF matrix inversion.","marker":"[10]"},{"why":"Defines the PolyMAX frequency-domain estimator used by the commercial modal identification chain.","marker":"[11]"},{"why":"Describes the poly-reference least-squares complex frequency-domain estimator used by the open-source modal fit.","marker":"[12]"}],"fun_headline_variants":["Open-source DAQ matches commercial to 3 kHz","Open DAQ achieves 3 kHz parity with commercial","Budget open DAQ reproduces commercial modal analysis","Open IEPE DAQ rivals commercial at 3 kHz","$220 open DAQ matches commercial modal testing"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The claim depends on the assumption that the ESP32-S3's PWM-generated sampling clock is accurate enough that the measured eigenfrequencies are not distorted by sampling-time errors; the paper itself notes that the cause of high-frequency phase deviations is currently unknown.","fun_headline_variants_meta":{"raw":{"variants":["Open-source DAQ matches commercial to 3 kHz","Open DAQ achieves 3 kHz parity with commercial","Budget open DAQ reproduces commercial modal analysis","Open IEPE DAQ rivals commercial at 3 kHz","$220 open DAQ matches commercial modal testing"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000368,"raw_usage":{"total_tokens":1967,"prompt_tokens":931,"completion_tokens":1036,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":547,"completion_tokens_details":{"reasoning_tokens":962}},"tokens_in":547,"tokens_out":1036,"duration_ms":9298,"temperature":1.0,"reasoning_tokens":962,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T11:04:04.761692+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Split the same IEPE accelerometer signal between OASIS-UROS and a reference DAQ, drive the structure with a known 5 kHz tone, and compare the measured frequency and phase over a 10-second record; if OASIS-UROS reports a frequency error above about 0.1% or a progressive phase lag above 3 kHz that the reference does not, the PWM sampling clock is inaccurate and the close-agreement claim fails.","supporting_citations":[{"cited_title":"M., Maierhofer, J., K¨ ostler, A., and Rixen, D","cited_arxiv_id":null,"evidence_quote":"Supplies the hardware project files, manufacturing files, firmware, and GUI source needed to reproduce the board."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the open-source modal identification routines used to extract modes from the OASIS measurement data."},{"cited_title":"AD7606C-18 - 8-Channel DAS with 18-Bit, 1 MSPS Bipolar Input, Simultaneous Sam- pling ADC - Datasheet","cited_arxiv_id":null,"evidence_quote":"AD7606C-18 datasheet that specifies the ADC timing, oversampling modes, voltage ranges, and transfer function used throughout the paper."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the open-source frequency response function estimation code used to compute the OASIS FRFs."},{"cited_title":"M., Maierhofer, J., K¨ ostler, A., and Rixen, D","cited_arxiv_id":null,"evidence_quote":"Provides the validation measurement data and Python processing script, making the comparison reproducible."},{"cited_title":"S., Rixen, D., Seijs, M","cited_arxiv_id":null,"evidence_quote":"Motivates why high-frequency FRF errors matter for applications like substructuring that require FRF matrix inversion."},{"cited_title":"The PolyMAX Frequency-Domain Method: A New Standard for Modal Parameter Estimation?","cited_arxiv_id":null,"evidence_quote":"Defines the PolyMAX frequency-domain estimator used by the commercial modal identification chain."},{"cited_title":"A poly-reference implementation of the least-squares complex frequency-domain estimator","cited_arxiv_id":null,"evidence_quote":"Describes the poly-reference least-squares complex frequency-domain estimator used by the open-source modal fit."}],"review_version":1}