{"id":"2d2c10e9-10f3-436b-9c14-d33c72ddd8c1","arxiv_id":"2411.19575","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"low","formal_verification":"none","parameter_count":0,"one_line_summary":"Buried TiN bottom gates with 60 nm pitch, made by trench filling and mechanical polishing, electrostatically define quantum dots in InAs nanowires, showing Coulomb blockade at cryogenic temperatures.","lead":"Researchers built flat, buried gate electrodes by filling etched trenches in silicon with titanium nitride and polishing the surface, then used them to create quantum dots in indium arsenide nanowires. The devices show single-electron tunneling and Coulomb blockade, suggesting the gates could serve as a scalable platform for nanowire-based qubits.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The main unresolved risk is that the Coulomb diamonds may come from a parasitic dot rather than the intended buried barrier gates; the authors' own device-D note explicitly concedes this possibility.","rationale":"The reader's weakest assumption is that the Coulomb diamonds originate from the intended gate-defined dot rather than a parasitic dot, and the reader's verdict is CONDITIONAL. My reading converges on exactly the same load-bearing concern, with the same evidence: the paper's own supplementary note about device D. This is not a manufactured objection; it is an admitted limitation in the manuscript. The main-text device-C data (VPG near 0 V with barriers at -4.5 V) are more consistent with an intended dot, and the detailed fabrication characterization and low leakage support the process claim, so outright rejection is not warranted. However, because a parasitic dot can mimic all the transport signatures shown, the functionality claim should stay conditional until barrier-gate sweeps demonstrate gate control. I would keep the reader's CONDITIONAL verdict and add the concrete barrier-sweep test as the condition. A secondary observation: the abstract and conclusion state leakage below 1 nA at +/-10 V while Figure 4's caption reports 1-2 nA; this wording discrepancy should be corrected but does not change the verdict.","tokens_in":9503,"tokens_out":6984,"duration_ms":65201,"concrete_test":"On a device such as device C, set VSD to about 200 µV (above the induced gap), fix VBR at -4.5 V, and record dI/dV as a function of VPG and VBL. If the intended barriers form the dot, the Coulomb peak positions in VPG should shift linearly with VBL, with slope -C_BL/C_PG, and the diamond vertices should move smoothly. Repeat with VBL fixed and VBR swept; the two slopes should agree with the capacitance model. If VBL and VBR only change transmission amplitudes without the predicted peak shifts, the observed dot is not controlled by the intended gates and the parasitic-dot scenario is confirmed.","verdict_should_be":"UNCHANGED","load_bearing_attack":"For the central claim to hold, the Coulomb diamonds in Figure 6 and Supplementary Figures 5-6 must be formed by the intended barrier gates. The paper's only support is the statement in 'Formation of Quantum Dots in Nanowires' that 'the contribution from the quantum dot is expected to be largely dominant.' That is a plausibility argument, not a measurement: no data show the barrier gates independently controlling tunnel coupling, and no scan localizes the dot between the intended gates. The supplementary text for device D states that the plunger voltage (-7.45 V) is more negative than the barriers (-5 V), which 'could suggest that the quantum dot observed here is actually not formed as intended by barrier gate electrodes.' A disorder-defined dot in the InAs nanowire would also produce Coulomb diamonds, charging energies around 1.5-2 meV, and gate hysteresis. Thus the present data do not yet exclude the parasitic-dot scenario. This does not invalidate the fabrication achievement, but it leaves the core functionality claim conditional.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports a buried bottom gate technology for semiconductor nanowire quantum dots: trenches etched into a Si substrate are filled with sputtered TiN and mechanically polished to a flat surface, achieving gate pitches down to 60 nm. The authors characterize the leakage between neighboring gates at room temperature and at 4.2 K, and present transport measurements on InAs nanowires placed on these gates, showing Coulomb blockade in gate sweeps and stability diagrams at temperatures of 60 and 600 mK. Charging energies around 1.5–2.1 meV and plunger gate lever arms between 0.008 and 0.05 are extracted. The manuscript claims that these results demonstrate the suitability of buried bottom gates for defining quantum dots in semiconductor nanowires.","tokens_in":62,"tokens_out":3238,"duration_ms":92484,"significance":"If the central claim holds, this buried gate process is a valuable alternative to lift-off bottom gates for nanowire qubit devices, offering a flatter surface that may reduce charge noise and permit smaller gate pitches. The paper's concrete strengths are the detailed fabrication description, the leakage data that directly address a practical concern, and the clear Coulomb diamond features in Fig. 6 and the supplementary figures. However, the functionality claim is currently conditional: the manuscript does not establish that the observed quantum dots are the ones intentionally defined by the buried barrier gates, and the authors themselves raise the parasitic dot possibility in the supplementary material. The fabrication achievement is solid, but the proof-of-principle demonstration requires additional measurements or analysis to rule out dot formation by disorder or surface states.","major_comments":[{"comment":"The central claim that the buried barrier gates define the observed quantum dot is not established. The only supporting statement is that \"the contribution from the quantum dot is expected to be largely dominant\" (Formation of Quantum Dots in Nanowires), but this is a plausibility argument rather than a measurement. The supplementary text for device D explicitly concedes that the plunger voltage below the barrier voltages \"could suggest that the quantum dot observed here is actually not formed as intended by barrier gate electrodes.\" The manuscript contains no data showing the barrier gates independently controlling tunnel coupling, nor any measurement localizing the dot between the intended gates. A disorder-defined or surface-state-defined dot in the InAs nanowire would produce the same Coulomb diamond features. To support the proof-of-principle claim, please provide, for example, conductance traces as a function of barrier gate voltage, stability diagrams at several barrier gate settings, or a control experiment without intentional barriers, to demonstrate that the dot is tunable by the intended gates.","section":"Formation of Quantum Dots in Nanowires / Supplementary Fig. S5"},{"comment":"The stability diagram in Fig. 6 was \"corrected for sudden jumps in the plunger gate potential by removing double features.\" Since the jumps are in the effective gate potential, removing them can alter the diamond slopes and hence the extracted lever arm α and charging energy EC. Please show the uncorrected data or provide a detailed, quantitative description of the correction procedure, including how many features were removed. In addition, the EC and α values in Table I are reported without error bars or a description of the fitting procedure, which is necessary given that the diamonds do not fully close due to the induced superconducting gap.","section":"Fig. 6 and Table I"},{"comment":"The text states that the induced superconducting gap (2Δ ≲ 0.15 meV) prevents the Coulomb diamonds from closing at charge degeneracy points. Because the lever arm is extracted from the diamond slopes VSD/ΔVPG, the finite gap introduces a systematic truncation that can bias the extracted slopes. The paper does not quantify this effect or describe how the open diamonds were used to determine α. Please provide an uncertainty estimate for the extracted parameters and explain how the finite gap was accounted for in the slope extraction.","section":"Formation of Quantum Dots in Nanowires, paragraph on EC and α"}],"minor_comments":[{"comment":"There are several typographical errors: \"dieletric\" in the Introduction, \"mirco-scope\" in the caption of Fig. 2, \"strutures\" in the Conclusion, and \"the induced superconducting gap ... is manifests\" in the Formation of Quantum Dots section. These should be corrected.","section":"Throughout"},{"comment":"The hysteresis measurement is described qualitatively. For reproducibility, please specify the sweep rate and direction of the plunger gate voltage in the caption or text, since the magnitude of the observed offset (about 0.08 V) depends on these parameters.","section":"Fig. 5b"},{"comment":"The caption states \"charging energies around 1.7 − 1.9 mV\"; the unit should be meV, consistent with the rest of the paper. Also check the main text for consistent use of \"meV\" versus \"mV\" when referring to EC.","section":"Supplementary, Fig. S6"},{"comment":"The notation for the gate electrodes (I through VII) and the terms \"barrier gates,\" \"plunger gate,\" and \"source-drain\" would benefit from a brief definition, especially since the paper uses both Roman numerals and names (e.g., VBL and VBR) in the schematic and in the text.","section":"Experimental, Quantum Dot Device Fabrication"}],"recommendation":"major_revision","confidential_remarks":"The fabrication results are solid and likely of interest to the nanowire quantum dot community, but the paper's title and abstract promise a proof of principle for quantum dot formation, and that claim is currently undermined by the authors' own admission of a possible parasitic dot in device D. The major revision should focus on adding measurements that localize the dot or otherwise exclude the parasitic dot scenario. I would not recommend rejection because the issue appears addressable within the scope of a revised manuscript."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThis is a fabrication paper with a concrete new result: buried bottom gates made by etching Si trenches, filling with sputtered TiN, polishing flat, then ALD dielectric, used to define QDs in InAs nanowires. The 60 nm pitch and low leakage at 4.2 K are real, and the Coulomb diamonds in Fig. 6 and gate sweeps in Fig. 5 look clean. The idea of replacing lift-off gates with polished trench fill is sensible and the authors show it works at the device level. Credit where due: the polishing process is described with honest supplementary images of under/over-polished structures, and the FIB cross sections help.\n\nThe soft spots are in proportion. The main one is the parasitic dot risk, and the authors half-admit it in the supplementary: for device D they note that the plunger voltage being more negative than the barriers 'could suggest that the quantum dot observed here is actually not formed as intended by barrier gate electrodes.' That is a load-bearing caveat for the central claim that the buried gates define the dots. The main-text support for the intended dot is the statement that the quantum dot contribution 'is expected to be largely dominant' - a plausibility argument, not a measurement. No data show the barrier gates independently controlling tunnel coupling, and no measurement localizes the dot between the intended gates. Since surface states in InAs are known to create parasitic dots, this is not a minor concern, but it does not invalidate the fabrication achievement. The other issues are minor: the stability diagram was corrected by removing features without showing the raw data, EC and alpha have no error bars, and the extracted alphas vary a lot between gates.\n\nThe citation pattern is fine, and the authors cite the prior lift-off gate work. The paper is honest about its limitations; device D's caveat is a sign of that. I would send this to a serious referee. The fabrication community gets a new route, and the QD demonstration, while not conclusive against parasitic dots, is enough to warrant follow-up with better control measurements.\n\nMy recommendation: engage with it, ask for additional data on barrier control and raw stability diagrams, but do not desk reject.\n\nCheers.","headline":"A genuinely new fabrication route for flat buried gates that works, with a real but disclosable caveat about parasitic dots.","tokens_in":10204,"tokens_out":1441,"would_cite":true,"duration_ms":12923,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Buried polished TiN gates form quantum dots in InAs nanowires.","keywords":["buried bottom gates","TiN gates","InAs nanowire","quantum dot","Coulomb blockade","single-electron tunneling","mechanical polishing","bottom gate fabrication"],"falsifier":"Measure the same nanowire with the two outer barrier gates held at 0 V so no intended dot should form; if Coulomb diamonds still appear, the observed blockade is dominated by a parasitic dot rather than the buried gates, which would refute the central claim.","tokens_in":9321,"feed_emoji":"⚛️","tokens_out":4892,"duration_ms":41908,"temperature":0.7,"pith_summary":"This paper tries to establish that bottom gates for semiconductor nanowire quantum dots can be made by a planar buried-gate process: trenches etched into silicon are filled with sputtered TiN and mechanically polished flat, instead of being patterned by metal lift-off. If it works, this gives a smooth, scalable gate platform that avoids the roughness and dielectric charge traps typical of lift-off gates. As proof, the paper reports a gate pitch down to 60 nm, leakage below 1 nA at ±10 V at 4.2 K, and Coulomb diamonds in InAs nanowires placed on the gates, which it reads as single-electron tunneling through a gate-defined quantum dot.","feed_headline":"Polished TiN gates hit 60 nm pitch and define quantum dots","feed_subtitle":"A flat, low-leakage alternative to lift-off bottom gates for InAs nanowire qubits, shown via Coulomb diamonds.","key_machinery":"The key object is the buried bottom gate: a trench etched 120 nm deep into high-resistivity silicon, thermally oxidized to isolate adjacent lines, filled with sputtered TiN, and planarized by mechanical polishing with a SiO2 abrasive. The flatness of the resulting surface carries the argument because it removes the valleys and metal roughness that in lift-off gates create charge traps in the dielectric. To form a quantum dot, a triplet of these gates is used, with the two outer gates biased negative to create tunnel barriers and the middle gate acting as a plunger, and the device is read out in a two-terminal configuration through Coulomb diamond analysis.","core_discovery":"The central claim is that buried bottom gate electrodes, made by filling silicon trenches with sputtered TiN and planarizing with mechanical polishing, are a working alternative to lift-off bottom gates for defining quantum dots in InAs nanowires. The paper shows flat gate arrays in electron micrographs, measures leakage currents between neighboring gates, and presents differential-conductance stability diagrams. In the best device, clear Coulomb diamonds yield a charging energy around 1.5 meV and a plunger-gate lever arm around 0.009, with the interpretation that the dot forms between two negatively biased barrier gates under a plunger gate. Multiple gate triplets and a second device give charging energies of 1.5 to 2 meV, supporting the conclusion that buried gates reliably form quantum dots.","pith_inferences":["A direct test of whether the observed dots are the intended barrier-defined dots would be to map how each gate's voltage shifts the Coulomb diamond edges and compare with a capacitive model; the paper's lever arms vary from 0.009 to 0.045, hinting that parasitic dots or gate crosstalk may contribute.","The measured hysteresis of about 0.08 V indicates trapped charge in the HfO2 layer, so a side-by-side noise comparison with lift-off gates would quantify the flat-surface advantage the authors expect.","The estimated induced superconducting gap (2Δ ≲ 0.15 meV) is far below bulk aluminum, suggesting the half-shell acts as a weak tunnel-coupled reservoir; this could be exploited for superconductor-mediated coupling of two dots, as the paper states as a future step."],"forward_implications":["Gate pitch can be scaled to 60 nm and below, matching the spacing needed for dense nanowire qubit arrays.","Cryogenic gate leakage is low enough (around 1 nA at ±10 V) that gate operation is not limited by the insulator.","The flat surface removes a major source of dielectric charge traps, so gate hysteresis and charge noise should be smaller than for lift-off gates, though some hysteresis remains.","The process decouples gate metal choice from lift-off constraints, allowing sputtered superconductors such as TiN to be used directly.","The platform extends to gating two-dimensional materials and, with a doped substrate, to additional half-pitch gate sections."],"supporting_citations":[{"why":"Defines the 60–100 nm gate pitch needed for nanowire quantum dots, the target this process meets.","marker":"[8]"},{"why":"Earlier InAs nanowire quantum dot work using lift-off bottom gates, providing the baseline this process replaces.","marker":"[15]"},{"why":"Supplies comparative data on gate-defined quantum dots in InAs nanowires and discusses surface states and parasitic dots.","marker":"[12]"},{"why":"Documents dielectric traps and hysteresis in nanowire gate stacks, used to interpret the observed hysteresis.","marker":"[16]"},{"why":"Explains the induced superconducting gap effect that widens the Coulomb blockade window in the stability diagrams.","marker":"[23]"},{"why":"Interprets residual transport near charge degeneracy via Andreev reflection, which the paper uses to estimate the gap.","marker":"[24]"}],"fun_headline_variants":["Polished TiN gates in trenches reach 60 nm pitch","Coulomb blockade in InAs dots via polished buried gates","Trench-filled TiN gates hit 60 nm pitch for quantum dots","Buried TiN gates enable 60 nm pitch for nanowire qubits","Mechanically polished TiN gates define InAs quantum dots"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the Coulomb diamonds come from a quantum dot deliberately formed between the two barrier gates, and not from a parasitic dot created by disorder, surface states, or trapped charge in the InAs nanowire.","fun_headline_variants_meta":{"raw":{"variants":["Polished TiN gates in trenches reach 60 nm pitch","Coulomb blockade in InAs dots via polished buried gates","Trench-filled TiN gates hit 60 nm pitch for quantum dots","Buried TiN gates enable 60 nm pitch for nanowire qubits","Mechanically polished TiN gates define InAs quantum dots"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000802,"raw_usage":{"total_tokens":3452,"prompt_tokens":797,"completion_tokens":2655,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":413,"completion_tokens_details":{"reasoning_tokens":2575}},"tokens_in":413,"tokens_out":2655,"duration_ms":16055,"temperature":1.0,"reasoning_tokens":2575,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T10:02:32.427996+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the same nanowire with the two outer barrier gates held at 0 V so no intended dot should form; if Coulomb diamonds still appear, the observed blockade is dominated by a parasitic dot rather than the buried gates, which would refute the central claim.","supporting_citations":[{"cited_title":"Hassler, G","cited_arxiv_id":null,"evidence_quote":"Defines the 60–100 nm gate pitch needed for nanowire quantum dots, the target this process meets."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Earlier InAs nanowire quantum dot work using lift-off bottom gates, providing the baseline this process replaces."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies comparative data on gate-defined quantum dots in InAs nanowires and discusses surface states and parasitic dots."},{"cited_title":"Zhang, H","cited_arxiv_id":null,"evidence_quote":"Documents dielectric traps and hysteresis in nanowire gate stacks, used to interpret the observed hysteresis."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Explains the induced superconducting gap effect that widens the Coulomb blockade window in the stability diagrams."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Interprets residual transport near charge degeneracy via Andreev reflection, which the paper uses to estimate the gap."}],"review_version":1}