{"id":"f0465f10-00ab-486c-9c47-c11640a601c9","arxiv_id":"2412.00289","paper_version":4,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"Running a non-Clifford surface-code circuit requires controller-decoder latency of tens of microseconds and parallel decoding tasks; a 1000-qubit, 0.1%-error processor could factor 21 with over 90% logical fidelity.","lead":"This paper derives what a classical control and decoding system must do to run a small error-corrected quantum algorithm, using Shor's factoring of 21 on a surface code. It concludes that decoder latency must stay below tens of microseconds, and that about 1000 qubits with 0.1% gate errors could suffice.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The >90% fidelity claim may be conditional on post-selection: the paper does not report the probability that all 14 nFT injections pass their all-zero syndrome checks, so per-shot success could be far below 90%.","rationale":"The reader correctly identifies the S-for-T substitution and omitted feed-forward as a modeling gap. However, the most direct threat to the abstract's unconditional '>90% fidelity' claim is the unaccounted post-selection acceptance rate. Section III explicitly states that post-selection keeps 'cases with only `0` stabilizer measurements during the surface expansion'; the reported ~5% logical error is therefore conditional on passing that filter. With 14 nFT injections, the joint acceptance probability is p_accept^14; the paper never reports p_accept. If p_accept is, say, 0.99, the overall success is ~83%; if it is 0.9, the success is ~22%. Either way the headline claim, as worded, is not supported. This is not a question of noise-model fidelity but a missing probability in the reported result. The S-substitution concern is important for extrapolating to the real non-Clifford circuit, but even the simulated Clifford-substituted circuit only achieves >90% fidelity conditional on an unstated PS acceptance. The provided code makes the test trivial: compute the PS acceptance fraction, raise to 14, multiply by the conditional success. This should be a required condition for acceptance; hence the verdict remains CONDITIONAL (UNCHANGED category) with this additional condition.","tokens_in":13742,"tokens_out":9731,"duration_ms":82717,"concrete_test":"Run the nFT injection simulation (Figure 3b) at p_phys=0.1%, d=5 using the public code (github.com/YanivKurman/factorization_paper_simulations). Count the fraction of trials in which every stabilizer measurement during the surface expansion is zero; call this p_accept. Compute p_accept^14 and multiply by the conditional success fraction (1 - P_logical) from Figure 4b (or from the full simulation). If the product is below 0.90, the abstract's claim of >=90% logical fidelity for a single execution is unsupported. Also report the expected number of repetitions (1/p_accept^14) and the resulting expected wall-clock time to judge whether the latency requirements still hold.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's headline fidelity claim ('>90% logical fidelity', total logical errors below 10%) is derived from simulations that include post-selection (PS) during each non-fault-tolerant magic-state initialization. Section III states: 'we included post-selection (PS) that we applied within the nFT initialization procedure, keeping cases with only `0` stabilizer measurements during the surface expansion.' The reported logical error of ~5% (Figure 4b) is therefore conditional on every nFT injection passing its PS check. For a circuit with 14 nFT initializations (Figure 3c), the unconditional success probability is p_accept^14 × (1 - P_logical_cond), where p_accept is the per-injection acceptance probability. The manuscript nowhere reports p_accept or the joint acceptance probability. If p_accept is 0.99, the 14-injection acceptance is 0.87, and with P_logical=0.05 the overall success is about 0.83, below the promised 90%. If p_accept is lower (e.g., 0.9), the overall success drops to ~0.22. Because the abstract states that 0.1% error and 1000 qubits 'are sufficient for the successful execution of the circuit,' this missing acceptance probability is directly load-bearing: it determines whether the central claim is true unconditionally or only for runs that survive an unstated amount of discarding. Moreover, repeated runs change the latency/resource estimates; the 'less than a millisecond' run time does not include the expected number of repetitions. The paper's acknowledged substitution of S for T gates and omission of feed-forward (also flagged by the reader) is a real limitation, but the post-selection accounting is a more immediate, quantifiable gap.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper derives controller-decoder system (CDS) requirements for executing a non-Clifford circuit, using Shor's algorithm for factoring 21 as a concrete case. The authors compile a 5-logical-qubit circuit to a surface-code layout (18 surfaces, 13 decoding tasks, 40 timestamps) and then to a physical-level circuit, simulate it with stim, and estimate logical errors from a binomial budget of 14 non-fault-tolerant (nFT) magic-state initializations and 296 fault-tolerant (FT) gates. They conclude that a physical error rate of 0.1% and about 1000 physical qubits (distance 5) suffice for >90% logical fidelity, and that the closed-loop feed-forward latency must stay within tens of microseconds, achievable by parallelizing decoders and fast controller-decoder communication.","tokens_in":13963,"tokens_out":3736,"duration_ms":34407,"significance":"If the results hold, this is a valuable end-to-end case study that moves the discussion of QEC control requirements from abstract decoder benchmarks to a concrete compiled circuit. The paper provides explicit resource estimates (Table 2), an open-source simulation repository, and a clear decomposition of decoding tasks into parallel, interdependent units (Figure 5). The claimed tens-of-microseconds latency budget and the identification of nFT-initialization error as the dominant bottleneck are useful guidelines for near-term experimental demonstrations. However, the headline fidelity and 'successful execution' claims are conditional on (i) an unstated post-selection acceptance probability and (ii) a Clifford approximation that omits T gates and feed-forward, so the significance is currently bounded by these caveats.","major_comments":[{"comment":"The >90% logical fidelity claim is conditional on post-selection during nFT initialization, but the manuscript does not report the per-injection acceptance probability or the joint acceptance probability over the 14 nFT initializations. The text states that post-selection keeps only cases with all-'0' stabilizer measurements during the surface expansion, and Figure 4b shows 'with PS' error rates. For a single execution, the success probability is p_accept^14 × (1 − P_logical_cond), where p_accept is the per-injection acceptance rate. If p_accept = 0.99, the joint acceptance is about 0.87, so even with P_logical = 0.05 the overall success is about 0.83, below the promised 90%; if p_accept is lower, the success rate drops sharply. The abstract's statement that 0.1% error and 1000 qubits 'are sufficient for the successful execution of the circuit' is therefore not established unconditionally. The authors should report p_accept, the unconditional success probability, and the expected number of repetitions, which also affects the latency and resource estimates in Table 2 and Section V.","section":"Section III, paragraph 2"},{"comment":"The simulation omits two features of the actual non-Clifford circuit: decoding-dependent mid-circuit feed-forward and non-Clifford T gates, which are replaced by S gates and |S> initializations. The abstract and Section I claim that the paper simulates 'the complete fault-tolerant factorization circuit at the physical level,' which is an overstatement. The simulated circuit is a Clifford approximation, and the error budget in Figure 3c assumes 14 nFT gates and 296 FT gates, but the actual simulated circuit has different nFT operations (S injection instead of T injection) and no feed-forward. The authors should either revise the claim to 'approximate simulation' or provide a quantitative argument, e.g., by simulating the T-gate injection with a stabilizer-based approximate sub-circuit or by showing that the S-for-T substitution and removal of feed-forward do not change the logical error rate beyond the reported error bars.","section":"Abstract and Section III"},{"comment":"There is an internal inconsistency in the number of feed-forward operations: Section I states '12 feed-forward operations and 13 decoding tasks,' while Table 1 lists 'Feed-forward gates 13.' If the discrepancy arises from counting the final measurement differently, that should be stated explicitly; otherwise the count should be corrected. This matters because the number of feed-forward operations directly determines the number of decoding tasks and the latency analysis in Section IV.","section":"Table 1 and Section I"}],"minor_comments":[{"comment":"Typo: 'Toal measurements' should be 'Total measurements.'","section":"Table 1"},{"comment":"The text says 'Figure 4b shows these dependencies and the active time of each task,' but the dependencies appear in Figure 5b; Figure 4 is the simulation results figure. Please correct the reference.","section":"Section IV, paragraph 1"},{"comment":"The equation for the additional error due to decoding delay is garbled in the typeset text (P_delay = N⋅P_FT^T_delay/d⋅T_round is not rendered clearly). Please typeset the equation properly, e.g., P_delay = N · P_FT · T_delay / (d · T_round) or with the intended exponent, and define each variable in the text.","section":"Section IV, paragraph 4"},{"comment":"The paper states that logic was verified through 3 out of 5 logical stabilizers; please explain why only 3 were verified and state the implication for the reported logical error estimate, since untracked stabilizers could in principle hide additional errors.","section":"Section III, paragraph 3"}],"recommendation":"major_revision","confidential_remarks":"The paper is from a quantum control company (Quantum Machines) and includes a self-citation (Ref. [35]) as background; this is not problematic. The main concern is the gap between the stated claims and the approximations used: the post-selection acceptance probability is load-bearing for the central fidelity claim and is not reported. If the authors can supply the acceptance probability and show that the Clifford approximation does not change the error budget, the paper would be a solid contribution. I recommend major revision rather than rejection because the underlying framework and resource analysis are sound and the missing information appears obtainable within the manuscript's scope."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Worth a look: this is the most concrete public analysis I've seen of what a controller-decoder system must actually do to run a small non-Clifford surface-code circuit. The headline targets—tens of microseconds end-to-end latency, up to ~5 parallel dependent decoding tasks, 0.1% physical error and ~1000 qubits for >90% logical fidelity—are useful engineering figures for both control-system and decoder design. The decoding-task dependency graph (Figure 5) is genuinely new and the paper gives a clear breakdown of what parallel decoding and inter-task communication entail.\n\nThe authors do real work: they compile Shor-21 to surface code, count FT and nFT gates, form a binomial error budget, and then verify it with a physical-level stim simulation at the thousand-qubit scale. Code is on GitHub. The latency analysis (Figure 5d) is a reasonable linear estimate, and the central observation that nFT magic-state initialization errors dominate and saturate fidelity for d>=5 is well supported.\n\nTwo soft spots, one of which is load-bearing. First, the simulation replaces every T gate with S and removes feed-forward. The paper acknowledges this, but phrases like \"complete fault-tolerant factorization circuit\" in the abstract overstate what was actually simulated. The numbers are for a Clifford proxy, not the real circuit. That is acceptable as an engineering estimate, but it should be labeled as such.\n\nSecond, the more immediate problem: the reported ~5% logical error is conditional on every nFT injection passing its post-selection check. The paper never reports the per-injection acceptance probability, so the unconditional success rate could be well below 90%. If p_accept is 0.99, the probability all 14 injections survive is 0.87, already failing the headline claim; if p_accept is 0.9, only ~22% of runs succeed. The abstract's statement that 0.1% error and 1000 qubits are \"sufficient for successful execution\" is misleading without this accounting. This is not fatal to the latency and parallelism requirements, but it changes the fidelity claim from unconditional to post-selected.\n\nMinor: the intro says 12 feed-forward operations while Table 1 says 13, and the text vacillates between \"up to four\" and \"about five\" parallel tasks. Needs cleanup.\n\nWho it's for: control-system architects, decoder hardware developers, and experimental groups planning the first non-Clifford QEC demonstrations. It deserves peer review—referees should push for explicit post-selection acceptance numbers and a clear distinction between the Clifford-proxy simulation and the actual circuit. I would cite the decoding-task analysis and bring the paper to a reading group focused on QEC system engineering.","headline":"Concrete CDS requirements for a small non-Clifford circuit, but the >90% fidelity claim is conditional on unstated post-selection acceptance.","tokens_in":14617,"tokens_out":2234,"would_cite":true,"duration_ms":22657,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":["81P68","68Q12"],"pacs":["03.67.Lx"],"model":"deepseek-v4-flash","headline":"A full end-to-end Shor-21 circuit shows that non-Clifford error-corrected computation is within reach if the decoding feedback loop stays within tens of microseconds.","keywords":["Shor's algorithm","surface codes","non-Clifford circuits","quantum error correction","feed-forward latency","decoding tasks","controller-decoder system","magic-state initialization"],"falsifier":"Simulate or run the actual non-Clifford circuit with real T gates and real-time feed-forward at $d=5$ and 0.1% physical error, and check whether the total logical error stays under 10%; a deviation from the predicted ~5% floor that grows with the number of feed-forward operations would show the substitution missed correlated errors. A second check: measure logical fidelity with the total controller-decoder latency set to tens of microseconds and then to, say, 100 microseconds; the delay-error formula predicts a specific added error, and data that contradict that scaling would falsify the latency budget.","tokens_in":13445,"feed_emoji":"⏱️","tokens_out":9473,"duration_ms":79580,"temperature":0.7,"pith_summary":"The paper works out, end to end, what a classical control system must do to run the next milestone in quantum error correction: a non-Clifford circuit with real-time feedback. Using Shor's algorithm factoring 21 as a representative case, it compiles the logical circuit through a surface-code layout down to physical gates and simulates the whole thing. The result is a concrete specification: the controller-decoder loop must finish its decoding-dependent feed-forward within tens of microseconds, which calls for several decoders working in parallel with fast links to the controller. The same simulation indicates that roughly 1000 physical qubits at a 0.1% physical error rate, with surface-code distance 5, are enough to factor 21 with above 90% logical fidelity. This matters because it turns “non-Clifford circuits need fault tolerance” into numbers a hardware or control-system team can design against.","feed_headline":"Shor with error correction needs decoding in tens of microseconds","feed_subtitle":"A full end-to-end simulation shows 0.1% physical error and d=5 surface codes suffice if feedback is fast enough.","key_machinery":"The machinery is the full compilation stack from logical algorithm to physical pulse-level circuit: the logical Shor circuit is converted into a surface-code-compatible form, laid out as an explicit 18-surface lattice-surgery circuit, and then compiled to physical gates and simulated with an extended stabilizer-circuit simulator. The argument is carried by three quantitative tools: a binomial error budget that counts 14 non-fault-tolerant magic-state initializations and 296 fault-tolerant gates; a decomposition of the circuit into 13 inter-dependent decoding tasks whose space-time volumes set the classical processing load; and a delay-error formula $P_{\\text{delay}}=N \\cdot P_{\\text{FT}} \\cdot T_{\\text{delay}}/T_{\\text{round}}$ that converts feed-forward latency into added logical error. These tools turn a single example into system-level specifications for controller, decoder, and communication channel.","core_discovery":"The central claim is that a non-Clifford QEC circuit of the scale of 15-to-20 non-Clifford gates can be executed successfully on near-term hardware, provided the classical controller-decoder system meets a set of well-defined real-time requirements. For the 5-logical-qubit Shor circuit, the compiled surface-level circuit contains 18 surfaces, 13 feed-forward gates, and 13 decoding tasks, with up to five decoding tasks active in parallel and dependencies between tasks that must be communicated. The end-to-end physical simulation, which substitutes S gates for T gates and omits feed-forward, shows logical fidelity above 90% at a physical error rate of 0.1% with distance $d=5$ (about 1000 physical qubits), while 0.3% error is insufficient. The error budget is dominated by the 14 non-fault-tolerant magic-state initializations, which cause logical error to saturate near 5% as distance grows; therefore the same framework implies that larger distances will not help until magic-state initialization fidelity improves. The authors state the results as general guidelines for any non-Clifford circuit with a few thousand physical qubits and roughly 15 non-Clifford gates, and in particular for 15-to-1 magic-state distillation.","pith_inferences":["If the T-to-S substitution hides correlated errors that real feed-forward logic would introduce, the 90% fidelity threshold could move; a natural extension is to run the same compiled circuit with a non-stabilizer simulator at small distance to quantify the gap.","The 13-task, five-parallel decoding workload derived here could serve as a standardized stress test for controller-decoder systems, complementing the paper's own benchmark by giving competitors a concrete circuit to run.","The microsecond latency budget scales with stabilizer-round time, so slower qubit platforms such as trapped ions would need different absolute budgets; the paper's numbers are specific to superconducting hardware.","Because non-fault-tolerant initialization dominates the error budget, hardware roadmaps that focus on raw qubit count may be less effective than roadmaps that improve magic-state injection fidelity; the paper's framework suggests prioritizing the latter."],"forward_implications":["A 1000-qubit superconducting processor with 0.1% physical error can execute a non-Clifford error-corrected circuit with about 15 non-Clifford gates at above 90% logical fidelity.","Controller-decoder systems must support real-time conditional gates, a local pre-decoding stage, and up to five parallel decoding tasks with inter-task communication; the total feed-forward latency budget is tens of microseconds.","Increasing code distance beyond $d=5$ gives no fidelity benefit at 0.1% physical error until the error in non-fault-tolerant magic-state initialization is reduced, so qubit scaling alone is not the bottleneck.","Magic-state distillation circuits with similar non-Clifford gate counts inherit the same latency and decoding-parallelism requirements.","For superconducting stabilizer rounds of about one microsecond, the full Shor factoring-21 run completes in under a millisecond, so the classical system, not the quantum circuit duration, sets the real-time challenge."],"supporting_citations":[{"why":"Supplies the surface-code error threshold framework and the logical-error scaling formula the paper uses for fault-tolerant gates.","marker":"[22]"},{"why":"The stabilizer-circuit simulator used to compile, simulate, and decode the full physical-level factorization circuit.","marker":"[53]"},{"why":"The hook-injection method for non-fault-tolerant magic-state initialization whose measured error dominates the circuit budget.","marker":"[51]"},{"why":"Lattice-surgery constructions that define the fault-tolerant parity-measurement and logical-gate building blocks used in the surface-level circuit.","marker":"[36]"},{"why":"The known decomposition of Toffoli gates into seven T gates plus Clifford operations that sets the non-Clifford gate count for the Shor circuit.","marker":"[43]"},{"why":"The lattice-surgery and magic-state distillation framework used for decoding-task shape/frame dependencies and for the claim that distillation circuits inherit the latency requirements.","marker":"[38]"},{"why":"The earlier holistic controller-decoder benchmark that motivates the end-to-end latency analysis and whose approach this paper extends to a concrete circuit.","marker":"[35]"},{"why":"The local pre-decoder proposal the paper points to as a way to reduce controller-decoder bandwidth and latency.","marker":"[61]"}],"fun_headline_variants":["Shor on surface code demands microsecond decoding","Error-corrected Shor needs decoding under 100 µs","Real-time decoding key to fault-tolerant Shor on 1000 qubits","Simulation: 0.1% error and 1000 qubits suffice for Shor","Controller-decoder latency sets pace for non-Clifford QEC"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The claim that the real circuit reaches above 90% fidelity rests on the assumption that replacing the non-Clifford T gates with S gates and removing the decoding-dependent feed-forward operations leaves the circuit's error behavior essentially unchanged, so the binomial error budget computed from the substituted circuit applies to the actual non-Clifford circuit.","fun_headline_variants_meta":{"raw":{"variants":["Shor on surface code demands microsecond decoding","Error-corrected Shor needs decoding under 100 µs","Real-time decoding key to fault-tolerant Shor on 1000 qubits","Simulation: 0.1% error and 1000 qubits suffice for Shor","Controller-decoder latency sets pace for non-Clifford QEC"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000203,"raw_usage":{"total_tokens":1448,"prompt_tokens":1071,"completion_tokens":377,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":687,"completion_tokens_details":{"reasoning_tokens":282}},"tokens_in":687,"tokens_out":377,"duration_ms":3904,"temperature":1.0,"reasoning_tokens":282,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T05:31:44.029373+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Simulate or run the actual non-Clifford circuit with real T gates and real-time feed-forward at $d=5$ and 0.1% physical error, and check whether the total logical error stays under 10%; a deviation from the predicted ~5% floor that grows with the number of feed-forward operations would show the substitution missed correlated errors. A second check: measure logical fidelity with the total controller-decoder latency set to tens of microseconds and then to, say, 100 microseconds; the delay-error formula predicts a specific added error, and data that contradict that scaling would falsify the latency budget.","supporting_citations":[{"cited_title":"Surface codes: Towards practical large-scale quantum computation,","cited_arxiv_id":null,"evidence_quote":"Supplies the surface-code error threshold framework and the logical-error scaling formula the paper uses for fault-tolerant gates."},{"cited_title":"Stim: a fast stabilizer circuit simulator,","cited_arxiv_id":null,"evidence_quote":"The stabilizer-circuit simulator used to compile, simulate, and decode the full physical-level factorization circuit."},{"cited_title":"Surface code quantum computing by lattice surgery,","cited_arxiv_id":null,"evidence_quote":"Lattice-surgery constructions that define the fault-tolerant parity-measurement and logical-gate building blocks used in the surface-level circuit."},{"cited_title":"A meet-in-the-middle algorithm for fast synthesis of depth-optimal quantum circuits,","cited_arxiv_id":null,"evidence_quote":"The known decomposition of Toffoli gates into seven T gates plus Clifford operations that sets the non-Clifford gate count for the Shor circuit."},{"cited_title":"A Game of Surface Codes: Large-Scale Quantum Computing with Lattice Surgery,","cited_arxiv_id":null,"evidence_quote":"The lattice-surgery and magic-state distillation framework used for decoding-task shape/frame dependencies and for the claim that distillation circuits inherit the latency requirements."},{"cited_title":"Benchmarking the ability of a controller to execute quantum error corrected non-Clifford circuits","cited_arxiv_id":"2311.07121","evidence_quote":"The earlier holistic controller-decoder benchmark that motivates the end-to-end latency analysis and whose approach this paper extends to a concrete circuit."},{"cited_title":"A local pre-decoder to reduce the bandwidth and latency of quantum error correction,","cited_arxiv_id":null,"evidence_quote":"The local pre-decoder proposal the paper points to as a way to reduce controller-decoder bandwidth and latency."}],"review_version":1}