{"id":"a4d04873-48f8-49b1-a163-60204d0b9dc0","arxiv_id":"2412.01575","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"Routing-aware DeepR, which enforces per-hop connection sparsity targets, yields mappable spiking networks that match an L1 baseline's accuracy with about 10x less simulated routing memory on the Mosaic architecture.","lead":"To reduce the memory spent on routing in neuromorphic chips, this paper trains networks with a per-distance sparsity constraint: the fraction of active connections at each hop count must fit the hardware's routing tables. On a spoken-digit task, they report comparable accuracy with roughly ten times less routing memory than an L1-based baseline, though the comparison is not fully isolated.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"","rationale":"","tokens_in":6463,"tokens_out":4422,"duration_ms":38795,"concrete_test":"","verdict_should_be":"UNCHANGED","load_bearing_attack":"","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper addresses the problem of optimizing on-chip routing memory when deploying spiking neural networks on the Mosaic neuromorphic architecture. The authors extend the DeepR training algorithm so that, instead of enforcing only a global connection sparsity, it enforces a per-hop sparsity profile P(θ), which they propose as a computationally efficient proxy for the memory and routability constraints of the Mosaic routing fabric. They evaluate the method on the Spiking Heidelberg Digits (SHD) classification benchmark, sweeping over target profiles and comparing against a non-routing-aware baseline from prior work. The reported results claim that the routing-aware trained network is fully mappable to the hardware, achieves 5% higher accuracy at the same memory count, and achieves iso-accuracy with about 10x less memory compared to the non-routing-aware baseline.","tokens_in":6477,"tokens_out":2546,"duration_ms":24538,"significance":"The problem is genuinely important: on-chip routing memory is a scarce resource in neuromorphic processors, and connecting training-time constraints to hardware mappability is a useful direction. The central idea of replacing an expensive mapping check with a per-hop sparsity profile is plausible and, if properly validated, would be a practical contribution. The paper also has positive reproducibility features: it reports 30-seed runs for each profile and a parameter sweep over profiles. However, the current empirical validation is not yet convincing because the baseline comparison does not isolate the routing-aware mechanism, and the proxy sufficiency claim is supported only by a single figure without quantitative detail. The contribution is therefore promising but needs stronger evidence before the central claims can be accepted.","major_comments":[{"comment":"The main quantitative claims ('5% more accuracy using the same number of parameters' and 'iso-accuracy with 10x less memory usage') are made against a non-routing-aware baseline taken from reference [10], which uses an L1-regularized training objective. This comparison does not isolate the effect of routing-aware per-hop constraints, because the routing-aware method also replaces the global-sparsity DeepR mechanism with a different training algorithm. A proper control would be DeepR with a global sparsity constraint matched to the same total memory or parameter budget, with the same network size, dataset, and training setup. Without such a control, the reported gains could be due to DeepR itself rather than to the per-hop routing constraint, and the central claim that routing-aware training is responsible for the improvement is not established.","section":"§IV, Fig. 3b; Abstract"},{"comment":"The entire method rests on the claim that the per-hop sparsity profile P(θ) is a sufficient proxy for routing memory, i.e., that networks with identical P have near-identical memory footprints. The only support is Fig. 2d, which shows a plot but no description of how the networks were sampled, how many networks were used, what architecture sizes were covered, or what 'minimal' standard deviation means quantitatively. The paper should report the distribution of memory counts for identical profiles, including worst-case deviations, across multiple architecture sizes and profile values, and should specify the exact metric used to judge sufficiency. Without this, the proxy may fail for profiles not tested, which would invalidate the mappability and memory-savings claims.","section":"§III, Fig. 2d"},{"comment":"The paper does not specify how the routing memory is actually computed: how the shared-path routing is implemented, how occupancy rates in Fig. 2c are derived from a connectivity matrix, how the required NT and RT crossbar sizes are determined, and what condition defines 'fully mappable'. Since the memory count is a central quantitative output and the proxy is supposed to approximate this mapping, the mapping procedure must be described precisely enough to be reproduced and checked. As written, the reader cannot verify the memory counts or the claim that the trained network is fully mappable.","section":"§III, 'Routing in Mosaic' and 'Approximating the Routing constraints'"},{"comment":"Algorithm 2 is underspecified in a way that affects reproducibility. In particular, the initialization step 'Initialize network weights θ such that P(θ) = P_hat' is nontrivial for arbitrary target profiles, and the pruning and reassignment steps f and g must preserve per-hop sparsity constraints simultaneously, not just a global count. The paper should describe how connections are pruned and reassigned while maintaining the element-wise conditions P(θ) ≤ P_hat and P(θ) = P_hat, and how this interacts with the L1 penalty and threshold selection. Additionally, the parameter sweep in Fig. 3a only varies p1 and p3 while setting all other hop sparsities to zero; the choice of this restricted family and its coverage of the feasible profile space should be justified.","section":"§III, Algorithm 2; §IV"}],"minor_comments":[{"comment":"The abstract says '5% more accuracy using the same number of parameters,' but Section IV compares memory count, not parameter count; the wording should be aligned with the actual comparison.","section":"Abstract; §IV"},{"comment":"The horizontal axis is labeled 'Memory count ×10^6' but the unit (memory elements, bytes, or bits) is not defined, and there are no error bars on either method; adding confidence intervals or standard deviations would strengthen the comparison.","section":"Fig. 3b"},{"comment":"The definition of p_d(θ) uses notation 'S(θ_{i,j})|_{H(NT_i,NT_j)=d}' that is not fully defined; in particular, the meaning of θ_{i,j} as a submatrix or block and how S is applied to that block should be stated explicitly.","section":"Eq. (1)"},{"comment":"The caption states 'RT and NT sizes refer to input size of a square crossbar array,' but the relationship between crossbar input size and memory count is not explained; a brief definition in the text would clarify the memory metric.","section":"Fig. 2d caption"},{"comment":"The global sparsity S(θ) = |θ|_0 / N^2 and the per-hop profile P(θ) = {p_d(θ)} are both called 'sparsity'; to avoid confusion, the text should explicitly state that P is a vector of per-hop sparsities and show how it relates to the global sparsity.","section":"§III, 'DeepR' background"}],"recommendation":"major_revision","confidential_remarks":"The paper is within the scope of the journal and addresses a timely topic. The main risk is that the reported advantages may be an artifact of comparing DeepR-based training against an L1-regularized baseline, rather than a genuine benefit of the routing-aware profile. I would strongly encourage the authors to add the missing control experiment and to provide quantitative validation of the proxy, since the current evidence is a single figure. If those are added, the paper could become a solid contribution; as it stands, the central quantitative claims are not yet supported."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"You should know two things about this one. First, the per-hop sparsity profile P(θ) is a new and genuinely useful idea: it turns the non-differentiable routing constraint into a per-distance sparsity target that DeepR can enforce during training. That is a clean, simple contribution, and the paper does it honestly. Second, the headline numbers are not yet backed up by the experiments as written. The comparison baseline is a non-routing-aware network trained with an L1 regularizer, not DeepR with a global sparsity constraint. So the reported 5% accuracy gain and 10x memory reduction could just as easily come from DeepR's rewiring dynamics as from the routing-awareness. That is a confound the authors need to address with a proper control. The paper's strengths are real. Adapting DeepR's prune-and-reassign loop to element-wise per-hop constraints is straightforward and the pseudocode is clear. The SHD results show low accuracy variance across seeds for a fixed profile, which supports the claim that the profile, rather than the exact connectivity, drives performance. That is an interesting observation with implications for hardware design. The use of an actual neuromorphic architecture (Mosaic) as a case study keeps the work grounded. The soft spots are mostly about verification. Figure 2d asserts that memory usage variance across networks with identical P is minimal, but no variance data or error bars are shown. That is load-bearing because the whole method treats P as a sufficient proxy. The abstract says the resulting network is fully mappable, but the paper never shows a direct routing/mapping check on trained networks; mappability is inferred from the profile. Also, the abstract says \"same number of parameters\" while the body says \"same memory count\" — those are different claims, since memory count includes routing memory, and the discrepancy should be fixed. None of this is fatal. The central derivation is correct, the idea is genuinely new, and the flaws are addressable with a few experiments: a DeepR-global-sparsity control, proxy variance measurements, and a direct mappability check. I would send this to peer review. It is a solid case study that will be useful to anyone building hardware-aware training for neuromorphic chips, provided the authors tighten the comparisons.","headline":"A sensible, incremental extension of DeepR to per-hop sparsity profiles for neuromorphic routing, but the headline gains over the baseline need an ablation and the mappability claim needs direct verification.","tokens_in":634,"tokens_out":655,"would_cite":true,"duration_ms":22616,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper proposes a hardware-algorithm co-design method that trains spiking neural networks against a per-hop sparsity profile, making them fully mappable to the Mosaic architecture and cutting routing memory by 10x at equal SHD accuracy.","keywords":["hardware-aware training","routing-aware training","dynamic architecture search","DeepR","Mosaic architecture","spiking neural networks","memory optimization","Spiking Heidelberg Digits"],"falsifier":"Run the exact Mosaic placement-and-routing algorithm on many random networks that all satisfy the same per-hop sparsity profile but concentrate long-distance connections on different tiles. If any of them exceeds a routing tile's capacity, or if required memory varies widely across the set, then the sparsity profile is not a sufficient proxy and the reported mappability guarantee would not hold.","tokens_in":6272,"feed_emoji":"🧠","tokens_out":6951,"duration_ms":55146,"temperature":0.7,"pith_summary":"The paper tries to establish that routing memory on a neuromorphic chip can be optimized during neural-network training rather than only during hardware design. It extends the DeepR dynamic-pruning algorithm to enforce a per-hop sparsity profile, meaning a budget on the fraction of active connections at each routing distance, and uses that profile as a cheap proxy for the exact placement-and-routing cost on the Mosaic small-world architecture. On the Spiking Heidelberg Digits task, networks trained this way are fully mappable to the hardware and, compared with non-routing-aware training, gain about 5% accuracy at equal memory or match accuracy with an order of magnitude less memory. The paper also observes that test accuracy is nearly constant across seeds that share the same profile, suggesting the connectivity profile itself, not the exact wiring, dominates performance.","feed_headline":"Routing-aware training fits networks to Mosaic with 10x less memory","feed_subtitle":"A per-distance connectivity budget gives 5% higher accuracy on SHD at equal memory, or equal accuracy with far fewer routing elements.","key_machinery":"The load-bearing object is the hop-distance sparsity profile $P(\\theta) = \\{p_d(\\theta) \\mid d \\in \\{0,\\dots,d_{\\max}\\}\\}$, defined as the fraction of active connections between neuron tiles whose routing distance is $d$ hops. The paper argues that this profile is a computationally cheap and reliable proxy for the exact Mosaic mapping function, because memory usage across networks with identical profiles has minimal variance. The DeepR algorithm supplies the mechanism: each epoch performs SGD on the loss with an $\\ell^1$ penalty, prunes weak connections, and randomly re-assigns inactive connections so that the element-wise profile constraint $P(\\theta) \\leq \\hat{P}$ is restored, turning a non-differentiable hardware constraint into a trainable sparsity budget.","core_discovery":"The central claim is that the routing-memory cost of mapping a network onto the Mosaic architecture is well approximated by a per-hop sparsity profile $P(\\theta) = \\{p_d(\\theta)\\}$, where $p_d(\\theta)$ is the fraction of active connections between neuron tiles at hop distance $d$, and that this profile can be enforced during training. Extending DeepR so that pruning and random re-assignment keep $P(\\theta) \\leq \\hat{P}$ elementwise yields networks that satisfy the routing constraints of the hardware. The paper reports that, on SHD, this routing-aware training reaches about 5% higher accuracy than non-routing-aware training at the same memory count, and that at matched accuracy (68.5%) it requires about ten times fewer memory elements. The supporting observation is that the standard deviation of memory usage across networks with identical $P$ is minimal, which is what makes the profile trustworthy as a proxy.","pith_inferences":["A testable extension is to compute hop-distance profiles for other network-on-chip topologies, such as mesh or hierarchical routing; if the proxy logic transfers, routing-aware training becomes a general recipe instead of a Mosaic-specific fix.","The profile-determines-accuracy observation points toward reverse co-design: choose a routing architecture whose feasible profiles match the natural connectivity statistics of a task, then train against that profile.","The same pruning-and-reassignment mechanism could be combined with learned placement, since the proxy decouples training from the exact placement step; the paper does not explore this direction."],"forward_implications":["Routing constraints on mesh-like neuromorphic hardware can be imposed during training through pruning and re-assignment, avoiding costly evolutionary search or a differentiable mapping function.","At a fixed memory count, routing-aware training improves SHD test accuracy by about 5 percentage points over L1-regularized non-routing-aware training.","At matched accuracy, the routing-aware network uses roughly ten times fewer routing-memory elements, which could allow larger networks on the same chip.","Because accuracy varies little across seeds with the same profile, the profile can be treated as a design variable, giving a memory-accuracy trade-off curve before committing to a particular chip configuration.","The near-constant accuracy across identical profiles suggests the exact connectivity matrix is less important than its distance statistics, so training could target profiles rather than individual connections."],"supporting_citations":[{"why":"Supplies the Mosaic architecture, its neuron-tile and routing-tile memory model, and the non-routing-aware training baseline that relies on an L1 regularizer.","marker":"[10]"},{"why":"Supplies the DeepR dynamic pruning and random re-assignment algorithm that the paper extends with per-hop sparsity constraints.","marker":"[15]"},{"why":"Supplies the Spiking Heidelberg Digits dataset and the vanilla recurrent spiking network baseline accuracy that the experiments are compared against.","marker":"[17]"},{"why":"Supplies the 1-turn routing scheme that determines hop distances and routing paths used to define the per-hop sparsity profile.","marker":"[16]"},{"why":"Supplies the context that routing memory is a large share of on-chip memory (32% on DYNAP-SE), motivating memory-optimal routing-aware training.","marker":"[4]"}],"fun_headline_variants":["Routing-aware training: same accuracy, 10x less memory","Train networks to fit hardware: 10x memory cut","Co-designing training and routing for 10x memory savings","Routing-aware nets: 5% better or 10x smaller","Memory-optimal neural nets via routing-aware training"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the routing memory a network needs is determined almost entirely by how many active connections it has at each routing distance; if two networks with the same distance profile can need very different amounts of memory, a network accepted by the proxy might still not fit on the chip.","fun_headline_variants_meta":{"raw":{"variants":["Routing-aware training: same accuracy, 10x less memory","Train networks to fit hardware: 10x memory cut","Co-designing training and routing for 10x memory savings","Routing-aware nets: 5% better or 10x smaller","Memory-optimal neural nets via routing-aware training"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000214,"raw_usage":{"total_tokens":1451,"prompt_tokens":997,"completion_tokens":454,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":613,"completion_tokens_details":{"reasoning_tokens":371}},"tokens_in":613,"tokens_out":454,"duration_ms":3847,"temperature":1.0,"reasoning_tokens":371,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T04:17:28.276853+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the exact Mosaic placement-and-routing algorithm on many random networks that all satisfy the same per-hop sparsity profile but concentrate long-distance connections on different tiles. If any of them exceeds a routing tile's capacity, or if required memory varies widely across the set, then the sparsity profile is not a sufficient proxy and the reported mappability guarantee would not hold.","supporting_citations":[{"cited_title":"Mosaic: in-memory com- puting and routing for small-world spike-based neuromorphic systems","cited_arxiv_id":null,"evidence_quote":"Supplies the Mosaic architecture, its neuron-tile and routing-tile memory model, and the non-routing-aware training baseline that relies on an L1 regularizer."},{"cited_title":"The heidelberg spiking data sets for the systematic evaluation of spiking neural networks","cited_arxiv_id":null,"evidence_quote":"Supplies the Spiking Heidelberg Digits dataset and the vanilla recurrent spiking network baseline accuracy that the experiments are compared against."},{"cited_title":"Near- optimal worst-case throughput routing for two-dimensional mesh net- works","cited_arxiv_id":null,"evidence_quote":"Supplies the 1-turn routing scheme that determines hop distances and routing paths used to define the per-hop sparsity profile."},{"cited_title":"A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (dynaps)","cited_arxiv_id":null,"evidence_quote":"Supplies the context that routing memory is a large share of on-chip memory (32% on DYNAP-SE), motivating memory-optimal routing-aware training."}],"review_version":1}