{"id":"39114f1c-381d-44ac-9553-170fd9ca8a81","arxiv_id":"2412.02394","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"PETAT introduces a time-sorted daisy-chain readout and serial powering for PET SiPM ASICs, replacing per-module FPGAs and reducing supply current.","lead":"A new readout chip for PET scanners, PETAT, chains detector chips in a daisy chain so data flows through them without needing a local FPGA for each module. It also powers chips in series to cut supply current, and early tests with three chips show the approach working.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The half-period wrap guarantee for the time-sorted merger is asserted rather than proven, and the idealized simulation does not exercise the worst-case latency and FIFO imbalance that could silently corrupt the sorted stream.","rationale":"The reader's weakest assumption correctly identifies the time-sorted merge and the TE-based wrap guarantee as the load-bearing element of the central claim. My stress-test agrees and adds a sharper technical point: the paper never proves that the timestamp difference between FIFO heads stays below half the wrap period when a sparse link delivers a TE after an arbitrarily long stall. The idealized simulation in Sec. 2.2, using back-to-back gammas with no absorption or scatter, generates relatively uniform traffic and cannot expose the pathological burst-plus-idle case. This is not a speculation about the authors' integrity; it is a gap between the asserted guarantee and the provided evidence. The proposed concrete test, an adversarial HB simulation with FIFO-depth and TE-rate parameters taken from the implementation, would either confirm the guarantee or reveal a violation that forces larger FIFOs, a higher TE rate, or a different arbitration scheme. Because the paper is already conditionally accepted with a request for further validation, this concern reinforces the condition rather than changing the verdict. The abstract's 'does not require any additional FPGA' overstatement is secondary; the body correctly limits the claim to eliminating per-module FPGAs, and the central technical contribution remains plausible if the time-sorted merge holds up.","tokens_in":7279,"tokens_out":20972,"duration_ms":223400,"concrete_test":"Run the cycle-accurate HDL simulation (Sec. 2.2) with an adversarial input trace: one branch carrying a 1 ms burst at the link bandwidth limit and a second branch delivering only one hit at the start of the burst, with all FIFO depths and TE periods as implemented. Record the maximum difference between the timestamps that the merger compares, and verify it stays below half the wrap period and that no out-of-order words appear at the output. Repeat with clock offsets of ±1 µs between chips. If the bound is exceeded or the output order is broken, the TE guarantee in Sec. 2.1 is insufficient.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section 2.1's merger is correct only if, at every arbitration step, the timestamps of the FIFO heads can be ordered without wrap-around ambiguity, i.e. the true time difference between the oldest and newest head is less than half the 52 µs wrap period. The paper asserts this is guaranteed by injecting timeout events at least once every quarter period, but it gives no bound on the stall duration of the merge: if one FIFO is empty, the merger waits until that link delivers data, and the delivery time of a TE from an upstream chip includes serialization latency, intermediate FIFO buffering, and merge scheduling at each level. No analytical bound is derived, and the Sec. 2.2 simulation uses uniform back-to-back gamma pairs, so the pathological case—a busy branch draining slowly while a sparse branch delivers a TE late—is never exercised. If the half-period bound is exceeded, the wrap-around comparison selects the wrong order, the output stream is no longer time-sorted, and the Section 2.3 FPGA coincidence filter would silently discard valid coincidences or accept invalid ones. This is the load-bearing assumption of the claimed FPGA-less time-sorted readout.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes PETAT, a new ASIC generation in the PETA family for SiPM-based PET readout, with two main architectural novelties: (i) a hierarchical serial readout in which front-end chips daisy-chain or tree-merge hit data without local module FPGAs, producing a time-sorted output stream via FIFO merging and periodically injected 'timeout events'; and (ii) a serial powering scheme using shunt regulators to reduce supply currents and cable losses. The digital readout architecture is validated by a cycle-accurate HDL simulation of 64 and 1024 chips in several topologies, and a first test chip (PETAT1) demonstrates the shunt regulators, a 3-chip serial chain, and data transfer across voltage domains. The full analogue readout path with a standard crystal array was not tested because PETAT1's analogue section was configured for a different SiPM readout concept; a follow-up chip PETAT2 has been submitted but its test results are not yet available.","tokens_in":7466,"tokens_out":9027,"duration_ms":111545,"significance":"If the readout concept holds, it would simplify detector construction for large-area PET scanners by removing per-module FPGAs, reducing auxiliary power distribution circuitry, and enabling a time-sorted data stream that allows early coincidence filtering and data reduction in a single downstream FPGA. The paper's strengths include cycle-accurate HDL simulation rather than abstract modelling, performance numbers derived from the clock frequency and packet size rather than fitted parameters, and an honest, clearly separated report of which features were silicon-verified (shunt regulators, 3-chip chain, inter-voltage-domain links) versus simulation-only or still pending (full PET readout on PETAT2). The serial-powering analysis is a useful quantitative comparison even if the exact trace-resistance accounting needs clarification.","major_comments":[{"comment":"The correctness of the time-sorted merger is load-bearing, but the paper only asserts that injecting timeout events every quarter period 'guarantees' that the difference between two time stamps never exceeds half the wrap-around period. No proof or invariant is given. Please provide a concise formal argument showing that, if each input stream (including the local hit FIFO) delivers packets whose timestamps are spaced by at most T/4, then at every merge step the head timestamps of all FIFOs lie within a window smaller than T/2, and that a temporarily empty FIFO cannot invalidate this bound. Also specify where timeout-event removal takes place: if TEs are dropped inside intermediate chips before the final merge, the per-stream packet-rate guarantee used for the wrap-around correction is violated.","section":"Section 2.1"},{"comment":"The cycle-accurate simulation uses an idealized phantom with uniform back-to-back gamma pairs and no Compton scattering or absorption, so it does not exercise the pathological load patterns that stress the time-sorted merger: for example, a hot branch with sustained high hit rate and a cold branch that contributes only timeout events, or bursts that cause one FIFO to fill while another is empty. Since the paper claims loss-free operation up to a well-defined activity limit, please add stress-test simulations with asymmetric per-region rates and temporal bursts, and report the FIFO depths and any overflows. This would substantiate the claim that the half-period wrap guarantee and the chosen FIFO sizes are sufficient in realistic conditions.","section":"Section 2.2"},{"comment":"The paper's title and abstract present PETAT as an ASIC for PET readout, but the only silicon results reported are for the shunt regulators, a 3-chip serial chain, and digital link operation across voltage domains. The full readout path with a standard crystal array was not tested because PETAT1's analogue section could not read such an array, and PETAT2 has not yet been tested. Please state this limitation prominently in the abstract and conclusions, and clearly differentiate the 'validated on silicon' claims from the 'simulated' and 'planned' claims, so that readers do not mistake the simulated performance for measured end-to-end performance.","section":"Section 4"}],"minor_comments":[{"comment":"The serial-powering voltage-drop calculation appears to count only one inter-chip resistance per segment (0.02 Ω total drop per segment), whereas the parallel-powering example counts both power and ground traces (2 × 0.02 Ω per segment). Please state explicitly whether the serial-chain resistance includes both conductors and, if so, recompute the total drop (which would then be 0.16 V rather than 0.08 V in the example).","section":"Section 3.1 / Figure 8"},{"comment":"The sentence 'we add sufficient TEs to ensure a data packet at least once every ¼ of the period' should specify whether this guarantee applies to each serial input link individually and to the local hit FIFO, and whether a 'packet' includes real hits as well as timeout events.","section":"Section 2.1"},{"comment":"The proposed FPGA processing pipeline in Figure 7 is described as 'not yet implemented nor simulated in detail'. Since this pipeline is part of the claimed readout chain, please clarify in the text whether the time-sorted end-to-end coincidence filtering is conceptual only or is supported by simulation.","section":"Section 2.3"},{"comment":"The statement 'This is still work in progress' at the end of Section 3.2 is in tension with the earlier statement that 'the shunt regulators work as expected'. Please clarify which aspects of the shunt regulation remain unverified.","section":"Section 3.2"},{"comment":"Reference [4] gives 'DOI: 1908.05878', which is an arXiv identifier rather than a DOI; please correct the reference format.","section":"References"},{"comment":"The text says 'The single-ended cells are uses for a standard JTAG'; this should be 'are used for'.","section":"Section 3.3"}],"recommendation":"major_revision","confidential_remarks":"The paper is an honest design study with interesting architectural ideas and partial silicon validation. The main technical risk is the unproven wrap-around guarantee for the time-sorted merger; this is fixable by adding a short proof and a stress-test simulation, so I recommend major revision rather than rejection. The authors should also be asked to make the simulation-only status of the full readout chain explicit in the abstract."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"You should know this is a solid, honest instrumentation paper, not a breakthrough. The genuinely new bit is the time-sorted daisy-chain readout with timeout events, which lets you merge hit streams from many PET ASICs without a local FPGA per module, together with serial powering applied to a PET front-end. Both are real ideas, and the authors are candid about what is and isn't tested.\n\nWhat's good: the digital architecture is simulated with full cycle-accurate HDL code for a 64-chip and a 1024-chip scanner, and they have a working three-chip hardware chain demonstrating serial powering and data transfer across voltage domains. That's concrete evidence for the powering scheme. They also plainly admit that PETAT1's analogue section couldn't read a standard crystal array and that the real test comes with PETAT2. That honesty is worth respecting.\n\nThe weak spot is the time-sorted merge guarantee. The paper says that injecting timeout events at least once every quarter of the wrap period guarantees the half-period bound for the wrap-around comparison. But no bound is derived on queueing latency: if a busy branch delays a sparse branch's timeout event, the timestamp difference at the merger could exceed half the wrap period and silently corrupt the sort. The simulation uses idealized back-to-back gammas with no Compton scatter or absorption, so it does not exercise that worst-case load imbalance. This is a genuine gap, but it's addressable—either a formal latency bound, a worst-case simulation, or a higher timeout rate. It doesn't kill the concept.\n\nTwo smaller notes. The \"no FPGA\" wording is stronger than the actual system, which still uses a central FPGA for aggregation and filtering. That's a wording issue, not a design flaw. And the device is an incremental advance in detector instrumentation, not a new physics capability—useful if you work on large PET scanners, less so if you don't.\n\nThe citation pattern looks fine: self-citations to the PETA family and to serial powering in HEP are legitimate prior work.\n\nThis paper deserves a serious referee. For JINST, I'd recommend a conditional acceptance with a request to fix the wrap-around analysis and soften the overclaims. If you work in PET readout or serial data aggregation, it's worth a careful read; I'd cite it as prior art for the timeout-event mechanism.","headline":"A useful, honest engineering proposal for a PET readout ASIC; the time-sorted daisy-chain with timeout events is new, but the wrap-around proof and the silicon validation are lighter than the claims.","tokens_in":8006,"tokens_out":5913,"would_cite":true,"duration_ms":65325,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A readout chip that daisy-chains PET detector data could drop per-module FPGAs and cut supply losses.","keywords":["PET readout ASIC","SiPM","daisy-chain readout","serial powering","time-sorted merging","timeout events","total-body PET","front-end electronics"],"falsifier":"Feed one PETAT input link a silent gap longer than a quarter of the 52 microsecond wrap period while the other input carries a sustained full-rate stream; if the timeout injection cannot keep the merger's FIFOs non-empty, hits will overflow or the time order will be corrupted. The paper's uniform, idealized simulation does not cover this overload case.","tokens_in":7054,"feed_emoji":"🔌","tokens_out":3611,"duration_ms":37827,"temperature":0.7,"pith_summary":"PETAT is a proposed front-end ASIC for silicon-photomultiplier PET scanners that moves data aggregation out of per-module FPGAs and into the chips themselves. Each chip receives serial hit streams from neighbouring chips, merges them by time stamp, and forwards a single time-sorted stream down a daisy chain, using injected timeout events to keep the merge correct when some links are quiet. The paper also proposes powering the chips in series with shunt regulators, so the whole chain draws one current instead of many parallel currents, sharply reducing resistive losses in supply traces. If these two ideas work at scanner scale, large PET systems would need fewer auxiliary boards, less power-distribution hardware, and simpler data acquisition.","feed_headline":"Daisy-chained PET readout cuts FPGAs and supply losses","feed_subtitle":"A serial readout chip and shunt-regulator powering promise simpler large PET scanners with lower cable losses.","key_machinery":"The two load-bearing mechanisms are the time-sorted daisy chain and serial powering. In the daisy chain, each chip's serial input links are buffered in FIFOs, a merger compares the oldest time stamp of every FIFO and always forwards the smallest, and periodically injected timeout events keep FIFOs non-empty and resolve the wrap-around of the 20-bit, roughly 52 microsecond time-stamp counter. In serial powering, chips are connected in a current chain, and each chip is shunted by a regulator that compares its supply voltage to an external reference, so the whole chain draws a single current and trace voltage drops scale with that one current instead of the sum of all chip currents.","core_discovery":"The paper claims that by moving data aggregation into the front-end ASIC itself, so that each PETAT chip receives serial hit streams from neighbouring chips, merges them by time stamp, and forwards a single time-sorted stream, the per-module FPGA can be eliminated. It further claims that the resulting low pin count makes serial powering practical: chips stacked in series with shunt regulators draw one common current, so resistive losses in supply traces and cables fall far below the parallel-powering case, at the cost of a higher total supply voltage. The authors' goal is to show that these two changes together make large PET scanners simpler, less power-hungry, and easier to build.","pith_inferences":["If the time-sorted merge holds at scale, the same daisy-chain idea could apply to other time-stamped detector arrays, such as Cherenkov or time-of-flight systems, not just PET.","The serial-powering benefit grows quadratically with the number of chips in a parallel chain, so this design is most attractive exactly where PET scanners are largest; a total-body scanner with thousands of chips is the natural stress test.","A realistic validation would need a simulation with Compton scattering, attenuation, and nonuniform activity to confirm that the chosen timeout-event rate and FIFO depths cover worst-case load imbalance; the paper's idealized back-to-back gammas leave this open."],"forward_implications":["A large PET scanner built from PETAT chips needs no FPGA on each detector module; one downstream FPGA or computer can ingest several time-sorted links.","Because the output stream is time-sorted, coincidence filtering, epoch extension, and cluster building can be done in a single downstream processor without re-sorting.","Serial powering reduces supply current and cable cross-section; in the paper's example, trace loss drops from 1.2 W to 0.08 W for five 1 A, 2 V chips.","Cycle-accurate simulation of a 64-chip tree indicates that the link can be filled to its bandwidth limit of about 3.9 million hits per second per link up to roughly 2.1 MBq activity before hits are lost."],"supporting_citations":[{"why":"Establishes the large-channel-count and data-volume challenge of total-body PET that this readout addresses.","marker":"[1]"},{"why":"Supplies the PETA front-end circuit blocks, such as time stamping and amplitude measurement, that PETAT inherits and extends.","marker":"[3]"},{"why":"Provides the serial-powering scheme and proof-of-principle demonstration that PETAT adapts to front-end ASICs.","marker":"[5]"},{"why":"Offers recent characterization data justifying serial powering for large detectors.","marker":"[6]"},{"why":"Presents the switched-mode step-down converter approach that serial powering is designed to replace, giving the comparison baseline.","marker":"[2]"}],"fun_headline_variants":["PETAT chip daisy-chains hits, kills FPGA, slashes cable loss","Serial-powering PET front-end: no FPGA, lower losses","One chip streamlines PET readout: no FPGA, series power","PETAT: front-end merges hits, cuts FPGAs and supply drops","Self-aggregating ASIC simplifies PET scanners, cuts power waste"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The readout stays correct only if hits arriving on each serial link are already time-sorted and if timeout events are frequent enough that no time-stamp gap ever exceeds half the wrap-around period; the paper's simulation of idealized gammas does not bound the worst-case burst that could fill a FIFO.","fun_headline_variants_meta":{"raw":{"variants":["PETAT chip daisy-chains hits, kills FPGA, slashes cable loss","Serial-powering PET front-end: no FPGA, lower losses","One chip streamlines PET readout: no FPGA, series power","PETAT: front-end merges hits, cuts FPGAs and supply drops","Self-aggregating ASIC simplifies PET scanners, cuts power waste"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000712,"raw_usage":{"total_tokens":3206,"prompt_tokens":951,"completion_tokens":2255,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":567,"completion_tokens_details":{"reasoning_tokens":2159}},"tokens_in":567,"tokens_out":2255,"duration_ms":20087,"temperature":1.0,"reasoning_tokens":2159,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T23:30:00.652260+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Feed one PETAT input link a silent gap longer than a quarter of the 52 microsecond wrap period while the other input carries a sustained full-rate stream; if the timeout injection cannot keep the merger's FIFOs non-empty, hits will overflow or the time order will be corrupted. The paper's uniform, idealized simulation does not cover this overload case.","supporting_citations":[{"cited_title":"8, December 2013, DOI: 10.1088/1748-0221/8/12/c12013","cited_arxiv_id":null,"evidence_quote":"Supplies the PETA front-end circuit blocks, such as time stamping and amplitude measurement, that PETAT inherits and extends."},{"cited_title":"al.: Serial powering: Proof of principle demonstration of a scheme for the operation of a large pixel detector at the LHC, Nucl","cited_arxiv_id":null,"evidence_quote":"Provides the serial-powering scheme and proof-of-principle demonstration that PETAT adapts to front-end ASICs."},{"cited_title":"al.: Serial powering characterisation for the CMS Inner Tracker at the High Luminosity LHC, Journal of Instrumentation, Vol","cited_arxiv_id":null,"evidence_quote":"Offers recent characterization data justifying serial powering for large detectors."},{"cited_title":"al.: Compact MR-compatible DC-DC converter module, Journal of Instrumentation, Vol","cited_arxiv_id":null,"evidence_quote":"Presents the switched-mode step-down converter approach that serial powering is designed to replace, giving the comparison baseline."}],"review_version":1}