{"id":"5b59f3bf-39bd-4011-b564-b1393e367654","arxiv_id":"2412.03443","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"BOSS uses union-find circuit blocking and a half-block tape schedule to cut shuttle operations in linear-tape trapped-ion compilation, achieving up to 96.1% fewer shuttles on tested benchmarks.","lead":"This paper presents BOSS, a compiler algorithm that groups quantum circuit gates into blocks to reduce how often ions must be moved inside a linear-tape trapped-ion computer. The authors report up to 96.1% fewer shuttle operations and large simulated speedups on several benchmark circuits.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The headline shuttle/time reductions rest on an unshipped and unspecified baseline: Table II's 'Previous' counts and Eq. (9)'s dist model must be reproduced from [77] before the 96.1% and 179.6x claims can be accepted.","rationale":"I read the paper as claiming an algorithmic improvement in TILT shuttling scheduling whose evidence is relative to [77]. For that claim to hold, the baseline comparison must be faithful and reproducibly specified. The reader's weakest assumption identifies exactly this point, and I agree with it. My additional check of the table confirms that the reported average shuttle improvement does not match the listed numbers, which strengthens the concern without changing the verdict: the paper already merits a conditional rather than unconditional acceptance. I found no definitive internal inconsistency in Algorithms 2 or 3 themselves, so the core idea may be salvageable, but the quantitative claims cannot be accepted until the baseline and the distance accounting in Eq. (9) are pinned down and an artifact is provided.","tokens_in":808,"tokens_out":804,"duration_ms":164482,"concrete_test":"Obtain the original TILT implementation accompanying [77] (or reimplement it precisely from the HPCA 2021 paper) and run it on the same seven QASM benchmarks with AOM sizes 16 and 32. Recompute `Spre` using the same tape-move semantics as BOSS, and recompute `tpre` from Eq. (9) using the exact same definition of `dist` as used for BOSS. If the original TILT reproduces Table II's `Spre` and `tpre` values, the concern is resolved; if the original counts are materially lower, the reported 96.1% shuttle reduction and 179.6x time ratio are inflated. Independently, recompute the average shuttle improvement from Table II and reconcile it with the claimed 16.6%.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claims are relative to prior work [77], but that baseline is not reproducible from this paper. Table II reports `Spre` and `tpre` for \"Previous\" without stating whether the numbers came from the original TILT implementation or from a private reimplementation, and no code or artifact is shipped. The problem is sharpened by Eq. (9): `texec = vm*dist + sum(td) + t1 + t2 + t3`, where `dist` is never defined operationally (total ion displacement? number of tape-move instructions? distance in ion spacings?). If the previous method is counted with a different `dist` convention, or if the reimplementation under-optimizes the TILT heuristic, the headline 96.1% shuttle reduction and 179.6x execution-time ratio are inflated. The paper's claimed 16.6% average shuttle improvement also does not match a recomputation from Table II (the 14 listed per-benchmark improvements average roughly 18%, or 34% if the two negative RCS rows are excluded), which further signals that the numbers are not internally checkable. Since the strongest claim is precisely that BOSS reduces shuttles and thereby improves execution time and success rate relative to [77], this baseline ambiguity is load-bearing: without a faithful baseline, none of the headline ratios can be evaluated. No definitive algorithmic flaw was found in the BOSS blocking scheme itself, but its claimed quantitative advantage is currently unverifiable.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript proposes BOSS, a blocking-based compiler for the linear-tape trapped-ion (TILT) architecture. The compiler first partitions a circuit's two-qubit gates into blocks of at most Z qubits using a union-find-style greedy procedure (Algorithm 2), then schedules each block by moving ions so that the block's qubits lie within the AOM execution zone (Algorithm 3). The authors report reductions in shuttle count, compilation time, and estimated execution time relative to the prior TILT compiler [77] on seven benchmark circuits, with claimed maximum reductions of 96.1% in shuttles and 179.6x in execution time, together with a success-rate analysis based on new gate and shuttle fidelity models.","tokens_in":21746,"tokens_out":10404,"duration_ms":88381,"significance":"If the quantitative claims are reliable, the blocking idea is a useful and plausible contribution: it is simple, has claimed O(ng) complexity versus O(ng^2) for [77], is evaluated on standard benchmarks, and extends prior compilation work with explicit execution-time and cooling models. The comparison is not circular, since BOSS outputs are compared with independent benchmarks and a baseline, but the baseline itself is not reproducible from the text, and several internal numerical inconsistencies affect the headline numbers. The core algorithmic concept of grouping gates into AOM-sized blocks to reduce shuttling is worth serious consideration, provided the comparison is made reproducible and the reported aggregates are corrected.","major_comments":[{"comment":"The 'Previous' columns (Tpre, Spre, tpre) are load-bearing for every headline claim, but the manuscript never states whether these numbers come from the original TILT implementation [77], from a reimplementation by the authors, or from a third-party implementation. No code or artifact is provided, and the previous compiler's swap-insertion heuristic is only summarized in Section III.B rather than specified. Without a faithful and stated baseline, the claimed 96.1% shuttle reduction and 179.6x execution-time improvement cannot be evaluated. Please state the provenance of these numbers, describe or reference the exact baseline algorithm used, and ship an artifact or detailed pseudocode.","section":"Section V, Table II"},{"comment":"The term 'dist' in Eq. (9) is undefined. The text says only that 'dist is the total shuttle distance'; the units, how the distance is accumulated over a schedule, and whether it is computed identically for BOSS and the baseline are not given. Figure 1's caption states that in TILT 'each shuttle enables the tape to move any distance,' which makes a distance-proportional time model ambiguous. Since the tpre/tboss ratios in Table II depend on this term, the execution-time improvements are not checkable. Define dist operationally (for example, the sum over shuttles of the tape displacement in ion spacings, converted to micrometers) and provide the per-benchmark values used.","section":"Section V.B, Eq. (9)"},{"comment":"The abstract and introduction claim an average shuttle reduction of 16.6%, but no reasonable aggregation of Table II yields this number. The arithmetic mean of the 14 per-benchmark DeltaS/Spre percentages is about 18.1%; excluding the two RCS rows gives about 33.9%; and the total shuttle count falls from 626 to 322, a 48.6% reduction. In addition, the SQRT/AOM32 row reports tpre=40.817s and tboss=0.207s with tpre/tboss=107.1, but 40.817/0.207 is approximately 197.2, which would exceed the claimed maximum of 179.6. These inconsistencies suggest the numbers in Table II and the summary statistics were not cross-checked; please correct them and state explicitly how the average improvement is computed.","section":"Section I and Table II"},{"comment":"The success-rate model is internally inconsistent. Eq. (11) defines Fshuttle = 1 - epsilon_shuttle * m, and Eq. (12) then multiplies product_{m=1}^{S}(1 - epsilon_shuttle * m), so each successive shuttle has a larger error; this is not the usual per-shuttle error model and should be justified. The text in Section V.C.a also says 'the fidelity of a single shuttle operation decreases linearly with the number of times it is performed,' which appears to contradict a constant per-shuttle error and is not what Eq. (11) states. The claim in Section V.C.b that for QFT/AOM16 the previous success rate is below 1e-14 while BOSS exceeds 4e-3 is not supported by any figure or table that includes the previous method. Please clarify the model, report per-benchmark success rates for both methods, and state explicitly that epsilon_laser and epsilon_shuttle are hand-set parameters.","section":"Section V.C, Eqs. (10)-(12)"},{"comment":"The scheduling algorithm is underspecified. The pseudocode moves 'the left half qubit of bi to the right of mi' without defining the TILT primitives used to reorder ions or the number and type of swap gates inserted; Figure 4 shows swap gates, but Algorithm 3 contains no swap-gate insertion. The statement that 'the swap gates that need to be introduced will not exceed floor(m/2) * s' is asserted without derivation. Since the shuttle-count reduction is the central mechanism, please give a complete formal description of the schedule, including how qubit order changes and how swap gates are counted, and prove the stated bounds.","section":"Section III.C, Algorithm 3"}],"minor_comments":[{"comment":"The variable G is used both for the dependency graph and for the group list; these should be disambiguated to avoid confusion.","section":"Algorithm 2"},{"comment":"The pseudocode does not show how the dependency-graph frontier is updated after a gate is placed into a group; please complete the pseudocode so the control flow is unambiguous.","section":"Algorithm 2"},{"comment":"There is a typo 'ha euristic' (should be 'heuristic'), and the statement that the worst case requires at least Omega(4^(n-m)) shuttles is stated without a derivation and with unclear notation.","section":"Section III.C"},{"comment":"The sentence 'the fidelity of a single shuttle operation decreases linearly with the number of times it is performed' needs rewording; the mathematical statement should follow directly from the equation.","section":"Section V.C.a"},{"comment":"The phrase 'because we make good use of the cooling process' is misleading, since the success-rate model in Eqs. (10)-(12) contains no cooling term; the improvement should be attributed to fewer shuttles.","section":"Section V.C.b"}],"recommendation":"major_revision","confidential_remarks":"The paper is within scope and the central blocking idea is worth considering after revision. The main obstacle is that the quantitative claims in the abstract and Table II are not reproducible or internally consistent; if the authors cannot provide the baseline provenance and code, the claims should be substantially softened. I see no evidence of circular reasoning or misattribution; the self-citation to [56] is not central to the results."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: the algorithmic idea is real, and the paper is worth engaging; the quantitative case is not yet reproducible. The union-find blocking with FIFO frontier and the half-block shuttle schedule are a genuinely new combination for TILT compilation, and the O(ng) complexity argument is clean. The comparison with the ILP-based scheduling [78] and the discussion of why minimum-cut is unnecessary are sensible. The paper also seems honest: it reports RCS cases where BOSS is worse, and it acknowledges extra swap gates.\n\nWhat the paper does well: the blocking idea is simple and plausible, the bound on shuttles between blocks (≤ 2nL/m) is useful, and the benchmark suite is standard. The reported compilation-time advantage (e.g., QFT 64 qubits from 64.8 s to 0.064 s) is consistent with the complexity difference and is the most trustworthy part of the evaluation.\n\nThe soft spots are exactly where the reader and stress-test put them. Table II's \"Previous\" numbers come from an unshipped reimplementation of [77], so all delta claims—the 96.1% shuttle reduction, the 179.6x execution-time ratio, and even the 16.6% average—are conditional on that reimplementation being faithful. The execution-time model in Eq. (9) uses dist without defining what it measures operationally, and that term drives the headline time ratios. The average improvement claim also does not recompute from Table II by my count; that is a small internal-consistency flag. The fidelity comparison is weaker still: hand-set epsilon_laser and epsilon_shuttle, and a different gate-fidelity formula than [77], so the success-rate superiority is more a modeling choice than an empirical result. The authors do flag that their fidelity model differs, which is in their favor.\n\nNone of this invalidates the core algorithm. The blocking and scheduling scheme is formal enough—clear complexity, clear bound, pseudocode—that a referee can check it without code. What is missing is a reproducible baseline and a precise definition of the distance term. I would send this to peer review with a request for the artifact (or at least a detailed statement of how Spre and tpre were generated and what dist counts), plus a corrected average if the table is the source of truth.\n\nBottom line: the paper is a solid technical contribution that needs a reproducibility pass. It deserves a serious referee, not a desk reject. I would read it again after those points are addressed.","headline":"A genuinely new blocking heuristic for TILT compilation with plausible shuttle reductions, but the headline numbers cannot be trusted until the baseline reimplementation and the distance model in Eq. (9) are made reproducible.","tokens_in":22227,"tokens_out":2107,"would_cite":true,"duration_ms":20371,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":["68Q12","81P68"],"pacs":["03.67.Lx"],"model":"deepseek-v4-flash","headline":"BOSS, a blocking algorithm for trapped-ion TILT compilation, cuts shuttle operations by up to 96.1% on benchmark circuits by grouping gates into execution-zone-sized blocks and scheduling qubit movement in half-zone chunks.","keywords":["quantum compilation","trapped-ion quantum computing","TILT architecture","shuttling scheduling","circuit blocking","union-find partitioning","execution time estimation","success rate estimation"],"falsifier":"Compile the SQRT benchmark with AOM size 32 using the original TILT compiler of [77] and count shuttle operations; if that count is materially below the 76 shuttles reported as the previous result, the claimed 96.1% reduction is inflated.","tokens_in":21213,"feed_emoji":"⚛️","tokens_out":14395,"duration_ms":113672,"temperature":0.7,"pith_summary":"The paper argues that shuttling ions in a linear trapped-ion tape is the dominant source of fidelity loss and slowdown, and that compilation should therefore minimize shuttle count rather than gate count. It introduces BOSS, which cuts a circuit into blocks that fit inside the execution zone (AOM), then moves qubits in half-zone chunks so each shuttle carries as many needed qubits as possible. On seven benchmark applications with 64–78 qubits and AOM sizes 16 and 32, BOSS reduces shuttles by up to 96.1% compared with the prior TILT compiler, and cuts estimated execution time by up to 179.6x. It also evaluates success rates under sympathetic cooling, reporting higher fidelity than prior estimates. The broader claim is that blocking gives a scalable $O(ng)$ compilation path for TILT and future modular ion-trap systems.","feed_headline":"Blocking cuts trapped-ion shuttles by up to 96.1%","feed_subtitle":"A new compiler groups gates into execution-zone blocks, cutting shuttles by up to 96.1% and estimated runtimes by 180x","key_machinery":"The load-bearing mechanism is block decomposition plus half-zone shuttling. First, the dependency graph's frontier is processed FIFO, and two-qubit gates are merged into a group when their qubit-index union stays within the AOM size; groups are emitted as blocks, which the paper argues lowers the vacancy rate of qubits in the execution zone. Second, for each block, Algorithm 3 selects the middle index of the block's qubits on the tape and shuttles the left half to the right of it and the right half to the left, requiring at most $\\lceil d/(m-k)\\rceil$ shuttles for moving $k$ qubits distance $d$, and bounding total shuttles between blocks by $2nL/m$ with at most $\\lfloor m/2\\rfloor$ swap gates per shuttle. This combination gives $O(ng)$ overall compilation time and turns shuttle reduction into a structural property of the scheduling, not a per-gate heuristic.","core_discovery":"The paper's central claim is that on a linear trapped-ion tape (TILT) architecture, the number of shuttle operations—not the number of gates—is the quantity a compiler should minimize, because each shuttle heats the ion chain and adds error. BOSS does this by partitioning the circuit's dependency graph into blocks of at most $m$ qubits, where $m$ is the AOM execution-zone size, using a union-find/FIFO grouping; it then schedules each block by moving the left and right halves of the required qubits toward the block's middle index, so no shuttle carries more than $\\lfloor m/2\\rfloor$ ions. On seven applications with 64–78 qubits and AOM sizes 16 and 32, the method reduces shuttle count by up to 96.1% (SQRT, AOM 32) and cuts estimated execution time by up to 179.6x (SQRT, AOM 16) versus the prior TILT compiler. The paper further estimates success rates under sympathetic cooling and reports substantially higher success rates than prior estimates, because fewer shuttles mean less accumulated error.","pith_inferences":["An extension left implicit is that the same dependency-graph blocking pass could serve as an inner scheduler for multi-zone or QCCD ion-trap layouts, where each linear tape segment is compiled by BOSS and inter-segment transport is handled separately.","Because the paper's FIFO grouping is one of many possible partitioning strategies, replacing step 7 of Algorithm 2 with a heuristic that anticipates the next block's qubit positions could cut shuttles further while keeping the same $O(ng)$ complexity.","A direct hardware measurement of whether fidelity loss scales with shuttle count rather than shuttle distance would determine how much of the reported success-rate gain transfers to real devices.","If gate fidelity degrades more slowly with execution-zone size than the $N^2$ model assumed, the shuttle reduction becomes the dominant error term and BOSS's relative advantage over the previous compiler would widen as technology improves."],"forward_implications":["Most benchmark circuits compile to fewer shuttles, with a maximum reduction of 96.1% and an average of 16.6% fewer shuttles than the prior TILT compiler.","Compilation time scales as $O(ng)$; the paper shows a 180-qubit QFT compiling in under 1.2 seconds, while the prior method took over 60 seconds for a 64-qubit QFT.","Estimated execution times fall by up to 179.6x and on average 61.5x, mainly because more gates execute during each visit of the execution zone, reducing idle qubit time.","Estimated success rates improve sharply; for example, QFT at AOM 16 exceeds $4\\times 10^{-3}$, while the prior model put it below $1\\times 10^{-14}$, because shuttle-induced error is lowered.","The improvement is not uniform: on RCS at AOM 32 BOSS uses 21 shuttles versus 11 for the prior method, and BOSS sometimes inserts more swap gates (336 vs 120 for QFT at AOM 16), a cost the paper argues is outweighed by the shuttle reduction."],"supporting_citations":[{"why":"Supplies the previous TILT compiler, benchmark methodology, and the shuttle/execution-time numbers that BOSS is compared against.","marker":"[77]"},{"why":"Establishes the ILP scheduling approach for TILT that BOSS avoids because it scales poorly with qubit count.","marker":"[78]"},{"why":"Provides the amplitude-modulated gate time model and the gate-fidelity scaling used in execution-time and success-rate estimates.","marker":"[79]"},{"why":"Supplies the faster Trout AM gate time model used for the reported execution-time comparisons.","marker":"[73]"},{"why":"Provides the phase-modulated gate time model used to show PM gates favor long-distance applications.","marker":"[45]"},{"why":"One source for the gate-fidelity formula used in the success-rate evaluation.","marker":"[22]"},{"why":"Supplies the sideband-cooling time used in the initial cooling term.","marker":"[12]"},{"why":"Supplies the mid-circuit sympathetic cooling time after each shuttle used in the execution-time estimate.","marker":"[39]"},{"why":"Supplies the shuttling speed used to convert shuttle distance into time.","marker":"[10]"}],"fun_headline_variants":["BOSS blocks shuttles: 96% fewer moves, 180x faster","Ion-trap compiler cuts shuttles 96%, runtimes 180x","Shuttle scheduling breakthrough: 96% less shuffling","Cut trapped-ion shuttles 96% with BOSS block scheduler"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The reported reductions are measured against the authors' own reimplementation of the prior TILT compiler, which is not shipped; if that reimplementation is suboptimal or uses a different distance model, the headline improvements would be overstated.","fun_headline_variants_meta":{"raw":{"variants":["BOSS blocks shuttles: 96% fewer moves, 180x faster","Ion-trap compiler cuts shuttles 96%, runtimes 180x","Shuttle scheduling breakthrough: 96% less shuffling","Cut trapped-ion shuttles 96% with BOSS block scheduler"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000245,"raw_usage":{"total_tokens":1541,"prompt_tokens":958,"completion_tokens":583,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":574,"completion_tokens_details":{"reasoning_tokens":502}},"tokens_in":574,"tokens_out":583,"duration_ms":6223,"temperature":1.0,"reasoning_tokens":502,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T22:24:21.377146+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Compile the SQRT benchmark with AOM size 32 using the original TILT compiler of [77] and count shuttle operations; if that count is materially below the 76 shuttles reported as the previous result, the claimed 96.1% reduction is inflated.","supporting_citations":[{"cited_title":"Noise analysis for high-fidelity quantum entangling gates in an anharmonic linear paul trap,","cited_arxiv_id":null,"evidence_quote":"Provides the amplitude-modulated gate time model and the gate-fidelity scaling used in execution-time and success-rate estimates."},{"cited_title":"Simulating the performance of a distance-3 surface code in a linear ion trap,","cited_arxiv_id":null,"evidence_quote":"Supplies the faster Trout AM gate time model used for the reported execution-time comparisons."},{"cited_title":"Phase-modulated entangling gates robust to static and time- varying errors,","cited_arxiv_id":null,"evidence_quote":"Provides the phase-modulated gate time model used to show PM gates favor long-distance applications."},{"cited_title":"Optimized fast gates for quantum computing with trapped ions,","cited_arxiv_id":null,"evidence_quote":"One source for the gate-fidelity formula used in the success-rate evaluation."},{"cited_title":"Efficient-sideband-cooling protocol for long trapped-ion chains,","cited_arxiv_id":null,"evidence_quote":"Supplies the sideband-cooling time used in the initial cooling term."},{"cited_title":"Suppression of heating rates in cryogenic surface-electrode ion traps,","cited_arxiv_id":null,"evidence_quote":"Supplies the mid-circuit sympathetic cooling time after each shuttle used in the execution-time estimate."}],"review_version":1}