{"id":"a65ee53b-d309-4b2d-ba22-5b284b41f6f2","arxiv_id":"2412.05327","paper_version":1,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A Y-Flash in-memory computing architecture for coalesced Tsetlin machine inference is presented, simulating 96.3 percent MNIST accuracy with improved energy efficiency.","lead":"IMPACT is a two-crossbar in-memory computing design that runs a logic-based Tsetlin machine classifier on Y-Flash memory cells, storing both the classifier's clauses and its weights in the memory arrays. It reports 96.3 percent accuracy on MNIST and roughly twofold better energy efficiency than several prior memory-based AI accelerators.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Claimed 24.56 TOPS/W cannot be reproduced from the paper's own metrics: a column read is one operation, 510 column reads per image at 84.21 pJ/image give 6.06 TOPS/W (0.174 from 5.76 pJ/op), so the Table 6 efficiency claims are unsupported.","rationale":"The reader's weakest_assumption (intermediate analog conductance programmability) is a legitimate reliability concern, but it is not the most decisive: Figure 3 does show analog tunability curves, and the two-stage tuning procedure with a fine-tuning window of ±5 segments gives at least a partial basis for the mapping, so the 96.3% accuracy claim could survive even if that assumption is imperfect. The efficiency claim, by contrast, is already contradicted by the paper's own tabulated numbers. The TOPS/mm2 value (0.17) is consistent with 413.6 GOPS divided by roughly 2.49 mm2, but the TOPS/W value cannot be derived from the stated energy per operation or energy per data point. The advertised improvements over ReRAM-CNN, NOR-Flash, and PCM accelerators are ratios of the unsupported 24.56 value, so the central advertised contribution of the paper is at risk. I credit the paper's experimental content: Y-Flash C2C/D2D endpoint measurements, CSA corner/process-variation analysis, and analog conductance curves are real evidence, and the TA-to-crossbar mapping is described in enough detail to be reproduced in simulation. But the headline efficiency metric is an internal inconsistency, not a matter of external consensus. A corrected, fully specified operation-count is a necessary condition for the conditional accept; if no consistent count can produce the claimed TOPS/W, the efficiency comparison should be rejected.","tokens_in":22209,"tokens_out":15311,"duration_ms":136482,"concrete_test":"Recompute TOPS/W from Section 5 and Table 4 under every stated definition: (a) 1/(5.76 pJ per operation) = 0.174 TOPS/W; (b) 510 column operations per image at 84.21 pJ per image = 6.06 TOPS/W; (c) 'equivalent to two MACs' = 0.347 TOPS/W. Then check whether any explicit operation-count convention yields the advertised 24.56 TOPS/W (which requires 2068 operations per image). If none does, Table 6's improvement factors should be recomputed with the consistent TOPS/W values; the central efficiency claim would not survive.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The central quantitative claim is the energy-efficiency advantage: 24.56 TOPS/W and the 2.23X/2.46X/2.06X improvements listed in Table 6 and the abstract. This claim fails an internal consistency check against the paper's own reported numbers. Section 5 defines one operation as a 2048-cell column read and reports 5.76 pJ/operation as the worst-case energy; 1/(5.76e-12 J) = 0.174 TOPS/W, not 24.56. Using the reported inference energy (67.99 + 16.22 = 84.21 pJ per image) and the architecture's column reads per image (500 clause columns + 10 class columns = 510 operations), TOPS/W = 510/(84.21e-12)/1e12 = 6.06 TOPS/W. If the stated 'equivalent to two MAC operations' is taken literally, each operation costs 2.88 pJ/MAC, giving 0.347 TOPS/W. None of these definitions yields 24.56; that value implies roughly 2068 operations per image or 0.0407 pJ/operation, a counting convention stated nowhere. Because the 2.23X/2.46X/2.06X comparisons are simply ratios of this 24.56 number against the baselines, a consistent accounting reverses the claimed advantage (e.g., 0.174 TOPS/W vs. 11.014 TOPS/W for ReRAM-CNN is a factor of 63 in the opposite direction). The 'Data Accessibility' section says no additional data are available, so the reader cannot independently inspect the counting convention.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes IMPACT, an in-memory computing architecture that uses two Y-Flash crossbar arrays to accelerate inference of a coalesced Tsetlin machine (CoTM). The clause crossbar tile (2048x500) operates in Boolean mode to compute clauses via column currents, while the class crossbar tile (500x10) operates in analog mode to compute weighted class sums. The authors report 96.3% accuracy on MNIST, 24.56 TOPS/W, 0.17 TOPS/mm2, and energy-efficiency improvements of 2.23X, 2.46X, and 2.06X over ReRAM-CNN, NOR-Flash neuromorphic, and PCM-DNN accelerators, respectively. The paper also presents CSA design and corner analysis, C2C and D2D variability measurements of Y-Flash endpoints, and a two-stage weight-to-conductance tuning procedure.","tokens_in":22577,"tokens_out":12787,"duration_ms":123826,"significance":"If the reported efficiency numbers were reproducible, the paper would be a valuable first demonstration of CoTM inference on a Y-Flash crossbar, with the practical strengths of using measured device data, a detailed CSA worst-case analysis, and a transparent two-stage mapping of trained weights to conductance levels. The architectural idea of splitting CoTM into a Boolean clause crossbar and an analog class crossbar is interesting and worth pursuing. However, the central quantitative claims about energy efficiency and the comparative speedups are not supported by the paper's own definitions and numbers, and the accuracy claim relies on an unverified assumption about the reliability of intermediate analog conductance states. These issues need to be resolved before the paper can be accepted.","major_comments":[{"comment":"The reported TOPS/W figure is not reproducible from the paper's own definitions. Section 5 defines an operation as reading one column of the crossbar and reports 5.76 pJ/operation as the worst-case column energy. For one MNIST image, the architecture performs 500 clause-column reads and 10 class-column reads, i.e., 510 operations, and Table 4 reports 67.99 pJ + 16.22 pJ = 84.21 pJ per image. These values give 510/(84.21e-12) = 6.06 TOPS/W, or 1/(5.76e-12) = 0.17 TOPS/W if the stated per-operation energy is used, not the claimed 24.56 TOPS/W. The claimed value is only reproducible if each of the 2048 cells in a column is counted as two operations (multiply and accumulate), a convention that contradicts the stated definition and is not used for the pJ/MAC entries of the comparison systems in Table 6. The Table 6 speedups (2.23X, 2.46X, 2.06X) are ratios of this unreproducible number and therefore do not support the abstract's efficiency claims. Please state the exact operation-counting convention, recompute all efficiency metrics consistently, and redo the comparisons on an apples-to-apples basis.","section":"Section 5, Table 4, Table 6"},{"comment":"The class crossbar mapping in Section 3(b) divides the Y-Flash conductance range into up to 420 uniform segments and requires each cell to be tuned within a ±5-segment margin. However, the variability evidence in Section 4(a) characterizes only the endpoint states LCS and HCS; no cycle-to-cycle or device-to-device statistics are provided for intermediate analog conductance levels. Because the 96.3% accuracy result depends on the class tile accurately reproducing trained weights, the authors should provide per-segment variability data (or simulations using measured intermediate-state distributions) and show that the ±5-segment fine-tuning acceptance criterion is met across devices and cycles. Without this, the accuracy claim under realistic device mismatch is not established.","section":"Section 4(a), Section 3(b), Figures 7-8"},{"comment":"The reported GOPS value of 413.6 and the TOPS/mm2 value of 0.17 are not tied to a stated timing model. The paper gives a 5 ns read cycle for a clause column but does not state whether the 500 clause columns and 10 class columns are read sequentially, in parallel, or in a pipelined fashion. The statement that one clause/class computation 'is equivalent to two MAC operations' is asserted without derivation. Please provide a concrete throughput model and justify the MAC equivalence, since these metrics are central to the performance claims.","section":"Section 5, Table 4"}],"minor_comments":[{"comment":"The text says the pre-tuning process 'reduced the cost error by 0.62%' and then 'reduce the 0.62% cost error to 1%'; if the cost error increased from 0.62% to 1%, the word 'reduced' is misleading and should be corrected.","section":"Section 4(b)"},{"comment":"The sentence 'IMPACT outperforms other technologies in terms of TOPS/W by a factor of X' is followed by a list that includes '0.61X compared to [26]', which is underperformance, not outperformance; the phrasing should be revised.","section":"Section 5, Table 6 discussion"},{"comment":"The equivalence between a clause computation and two MAC operations appears without derivation or citation; please either justify it formally or replace it with a metric whose definition is explicit.","section":"Section 5"},{"comment":"The paper states that no additional data are available; given that the efficiency claims cannot be reproduced from the text alone, providing a detailed calculation sheet or simulation scripts as supplementary material would be necessary during revision.","section":"Data Accessibility"},{"comment":"The hyperparameters (number of epochs, TA states, literal encoding) for the additional datasets in Table 5 are not specified; please add them or clearly label these as preliminary feasibility results.","section":"Table 5"}],"recommendation":"major_revision","confidential_remarks":"The efficiency comparison is the paper's main advertised contribution, and the current manuscript does not supply a consistent basis for the 24.56 TOPS/W figure or for the 2.23X/2.46X/2.06X comparisons. This is not a cosmetic issue; if the authors cannot reconstruct these numbers from a clearly stated and fairly compared operation count, the comparative claims should be removed or substantially revised. I also note that the manuscript still contains placeholder ethics/disclaimer text and would benefit from a completed data-availability statement before resubmission."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Dear colleague,\n\nThe short version: the mapping of CoTM onto two Y-Flash crossbars is a genuine and interesting idea, and the accuracy simulation looks honest. The efficiency headline does not survive arithmetic. The paper reports 24.56 TOPS/W while also reporting 5.76 pJ per column operation; those two numbers are incompatible by a factor of about 140. Using their own inference energy (84.21 pJ/image) and their operation count (510 column reads/image) gives about 6 TOPS/W, and using their J/op directly gives 0.174 TOPS/W. The claimed 2.23X/2.46X/2.06X improvements over ReRAM/NOR-Flash/PCM accelerators are simply ratios built on that 24.56 number, so they are unsupported. The paper cannot be taken at face value for energy efficiency until this is redone with a consistent definition of an operation.\n\nWhat is genuinely new: this is the first IMC implementation of a coalesced Tsetlin machine, the two-crossbar split (Boolean clause tile, analog class tile) is a clean mapping, and the authors validate it with measured Y-Flash conductance statistics rather than assumed device models. The CSA corner and mismatch analysis is thorough, and the worst-case clause current bounding is a nice piece of circuit reasoning. The accuracy of 96.3% being preserved under simulated device variability is a legitimate result.\n\nThe softer concern is the class crossbar: analog programmability of intermediate conductance states is demonstrated, but variability is only characterized at the endpoints, and the ±5 segment fine-tuning margin is an assumption. That matters, but it is secondary to the efficiency problem. The paper also says no data are available, so the reader cannot inspect the operation-counting convention.\n\nWho it is for: people working on Tsetlin machine hardware or on non-von-Neumann inference accelerators. The architecture idea itself deserves discussion. But as it stands, the central comparative claim is broken; a serious referee would have to send it back for a careful recomputation. I would still accept it for review because the underlying work is substantial and the flaw is fixable.","headline":"The Y-Flash/CoTM mapping is real and interesting, but the 24.56 TOPS/W headline is off by ~140x against the paper's own numbers.","tokens_in":23159,"tokens_out":2831,"would_cite":false,"duration_ms":25966,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper presents IMPACT, an in-memory computing architecture that maps coalesced Tsetlin machine inference onto two Y-Flash crossbars and reports 96.3% accuracy on MNIST with 24.56 TOPS/W.","keywords":["coalesced Tsetlin machine","in-memory computing","Y-Flash memristor","non-volatile memory","inference accelerator","MNIST","crossbar array","edge AI"],"falsifier":"Program a batch of Y-Flash cells to each of the 420 weight-corresponding conductance segments using the paper's pre-tune/fine-tune sequence, then cycle each cell and record the spread of achieved conductance; if a material fraction of cells falls outside the $\\pm5$-segment acceptance band, the mapped weights would deviate from the software weights and the 96.3% MNIST accuracy would not hold in hardware.","tokens_in":22009,"feed_emoji":"⚡","tokens_out":8034,"duration_ms":65223,"temperature":0.7,"pith_summary":"This paper proposes an in-memory computing architecture, IMPACT, that maps the inference path of a coalesced Tsetlin machine (CoTM) onto two Y-Flash memristor crossbars: a 2048x500 clause tile operating in Boolean conductance mode and a 500x10 class tile operating in analog mode. The goal is to show that the logic-based CoTM can be evaluated entirely inside memory, eliminating von Neumann data movement while keeping the model's interpretable propositional rules. On MNIST the architecture reaches 96.3% accuracy, matching software training within 25 epochs, with 24.56 TOPS/W and 0.17 TOPS/mm2. The paper also claims energy-efficiency advantages of 2.23x, 2.46x, and 2.06x over ReRAM-CNN, NOR-Flash neuromorphic, and PCM-DNN accelerators. A sympathetic reader would care because this points toward low-power, non-volatile, transparent edge inference.","feed_headline":"Y-Flash crossbars run Tsetlin machine inference at 96.3%","feed_subtitle":"Two in-memory tiles compute Boolean clauses and weighted votes, beating three prior accelerators in energy efficiency.","key_machinery":"The load-bearing object is the Y-Flash cell, a two-terminal floating-gate memristor fabricated in 180 nm CMOS, with a read transistor and an injection transistor sharing a floating gate; it can be programmed to two Boolean conductance states or to intermediate analog levels. The carrying idea is to encode logical values as physical quantities: TA actions become HCS/LCS, input literals become 2 V or floating, weights become conductance segments, and Kirchhoff's current law performs the summation. The clause tile's current sense amplifier with a 4.1$\\,\\mu$A threshold turns the analog column current into the Boolean clause, while the class tile's two-step tuning (wide pulses for pre-tuning within $\\pm20$ segments, narrow pulses for fine-tuning within $\\pm5$ segments) maps the 0-419 weight range onto conductance. This mapping is what lets a propositional-logic model run as analog current sums in a memory array.","core_discovery":"The central claim is that a CoTM model can be decomposed into two physical crossbar operations and still preserve software accuracy. In the clause tile, each Tsetlin automaton's final include/exclude action is stored as a high or low conductance state (HCS or LCS), and each Boolean input literal is applied as either a floating node or a 2 V read voltage; Ohm's law at each cell then performs the required AND/OR interaction, and a current sense amplifier converts the column current into a Boolean clause using a 4.1$\\,\\mu$A threshold. In the class tile, the trained clause weights are shifted to unipolar values, segmented into 420 conductance levels, and written with a pre-tune/fine-tune pulse sequence; currents summed along each column realize the weighted vote for each class. With this mapping, the paper reports 96.3% MNIST accuracy and the energy and throughput figures above, and argues that Y-Flash's self-selecting behaviour removes sneak-path currents and the need for selectors.","pith_inferences":["Editorial extension: the paper validates inference only; if the same Y-Flash cells can absorb TA state updates as program/erase pulses, the architecture could plausibly support online CoTM learning, since the device endurance of $10^5$ cycles is demonstrated.","Editorial extension: because the variability study measures only the LCS and HCS endpoints, a direct measurement of intermediate conductance-state reproducibility under the $\\pm5$-segment fine-tuning tolerance would be the quickest test of whether the 96.3% accuracy survives in a manufactured class tile.","Editorial extension: the same Boolean-to-current mapping could be reused for other logic-based learners whose inference is a conjunction of literals, not only CoTM, potentially broadening Y-Flash IMC beyond Tsetlin machines."],"forward_implications":["If IMPACT is correct, a full MNIST inference pass needs no transfers between separate memory and compute units: one crossbar evaluates all 500 clauses and the second computes the 10 class votes.","The 2.32% include-action ratio means most clause cells sit in the low-conductance state, so inference energy stays near the LCS reading energy for typical inputs, making the sparse logic of CoTM directly pay off in hardware.","Because Y-Flash is non-volatile with retention over 10 years and endurance of $10^5$ cycles, the trained model can be stored and re-read without refresh, supporting always-on edge inference after a single programming step.","The modular crossbar partitioning shown for clauses and classes implies the same two-tile scheme can scale to larger datasets by splitting literals or weights across multiple arrays and combining partial results digitally.","Against the published baselines, IMPACT's 24.56 TOPS/W gives a 2.23x, 2.46x, and 2.06x energy-efficiency improvement over ReRAM-CNN, NOR-Flash neuromorphic, and PCM-DNN accelerators, respectively."],"supporting_citations":[{"why":"Supplies the Y-Flash device demonstration, its measured variability data, and the per-device area figure used in the footprint calculation.","marker":"[16]"},{"why":"Establishes the two-terminal floating-gate operation and low-power analog mode that IMPACT relies on for the class tile.","marker":"[17]"},{"why":"Provides the compact model used to simulate Y-Flash programming, erasing, and conductance behaviour for the crossbar tests.","marker":"[18]"},{"why":"Defines the coalesced Tsetlin machine with clause sharing, the algorithm whose inference IMPACT implements.","marker":"[19]"},{"why":"Introduces the original Tsetlin machine and its clause-voting structure, from which CoTM and the crossbar mapping derive.","marker":"[12]"},{"why":"Prior in-memory Boolean-to-current Tsetlin inference architecture that IMPACT extends to Y-Flash and analog weights.","marker":"[20]"},{"why":"Baseline ReRAM-CNN accelerator used for the 2.23x energy-efficiency comparison.","marker":"[24]"},{"why":"Baseline NOR-Flash neuromorphic accelerator used for the 2.46x energy-efficiency comparison.","marker":"[25]"},{"why":"Baseline PCM DNN accelerator used for the 2.06x energy-efficiency comparison.","marker":"[27]"}],"fun_headline_variants":["Y-Flash crossbars compute Tsetlin logic in memory","Y-Flash IMC for Tsetlin inference hits 96.3%","Y-Flash array achieves 96.3% Tsetlin accuracy","Energy-efficient Tsetlin inference on Y-Flash IMC","Two crossbars run Tsetlin inference with Y-Flash"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The class crossbar assumes that each Y-Flash cell can be programmed to any of the roughly 420 intermediate conductance levels within a tolerance of about $\\pm5$ segments, but the variability data in the paper characterize only the two endpoint states, LCS and HCS.","fun_headline_variants_meta":{"raw":{"variants":["Y-Flash crossbars compute Tsetlin logic in memory","Y-Flash IMC for Tsetlin inference hits 96.3%","Y-Flash array achieves 96.3% Tsetlin accuracy","Energy-efficient Tsetlin inference on Y-Flash IMC","Two crossbars run Tsetlin inference with Y-Flash"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000945,"raw_usage":{"total_tokens":4084,"prompt_tokens":1041,"completion_tokens":3043,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":657,"completion_tokens_details":{"reasoning_tokens":2951}},"tokens_in":657,"tokens_out":3043,"duration_ms":20614,"temperature":1.0,"reasoning_tokens":2951,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T22:35:40.175252+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Program a batch of Y-Flash cells to each of the 420 weight-corresponding conductance segments using the paper's pre-tune/fine-tune sequence, then cycle each cell and record the spread of achieved conductance; if a material fraction of cells falls outside the $\\pm5$-segment acceptance band, the mapped weights would deviate from the software weights and the 96.3% MNIST accuracy would not hold in hardware.","supporting_citations":[{"cited_title":"A memristive deep belief neural network based on silicon synapses,","cited_arxiv_id":null,"evidence_quote":"Supplies the Y-Flash device demonstration, its measured variability data, and the per-device area figure used in the footprint calculation."},{"cited_title":"Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing,","cited_arxiv_id":null,"evidence_quote":"Establishes the two-terminal floating-gate operation and low-power analog mode that IMPACT relies on for the class tile."},{"cited_title":"Physical based compact model of Y-Flash memristor for neuromorphic computation,","cited_arxiv_id":null,"evidence_quote":"Provides the compact model used to simulate Y-Flash programming, erasing, and conductance behaviour for the crossbar tests."},{"cited_title":"IMBUE: In-memory boolean-to-current inference architecture for tsetlin machines,","cited_arxiv_id":null,"evidence_quote":"Prior in-memory Boolean-to-current Tsetlin inference architecture that IMPACT extends to Y-Flash and analog weights."},{"cited_title":"Fully hardware- implemented memristor convolutional neural network,","cited_arxiv_id":null,"evidence_quote":"Baseline ReRAM-CNN accelerator used for the 2.23x energy-efficiency comparison."},{"cited_title":"High-performance mixed-signal neurocomputing with nanoscale floating-gate memory cell arrays,","cited_arxiv_id":null,"evidence_quote":"Baseline NOR-Flash neuromorphic accelerator used for the 2.46x energy-efficiency comparison."},{"cited_title":"Accurate deep neural network inference using computational phase-change memory,","cited_arxiv_id":null,"evidence_quote":"Baseline PCM DNN accelerator used for the 2.06x energy-efficiency comparison."}],"review_version":1}