{"id":"93786dad-daaa-4eac-b26f-b8ec05679f85","arxiv_id":"2412.06330","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"An FPGA transceiver serializes time-encoded bit patterns at 10 Gbps to produce a calibration-free 100 ps-resolution digital-to-time converter.","lead":"This paper builds a digital-to-time converter (DTC) using an FPGA's high-speed transceiver, encoding time intervals as serial bit patterns at 10 Gbps. It reports 100 ps resolution, a 1 ns to 40 microsecond range, and below 3 ps jitter without calibration, which could simplify timing generation in test and measurement systems.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The reported DNL/INL are measured on the digital data frame, not on physical output pulses; the entire-range linearity claim is therefore unverified for the actual DTC output.","rationale":"I read the paper as claiming that a GTX serializer can generate calibration-free timing pulses whose width is the number of encoded 1-bits times 100 ps, with <3 ps precision and excellent linearity over 1 ns–40 µs. For that to be true, the physical output must have low pattern-dependent jitter and accurate bit spacing. The paper's strongest evidence is endpoint precision (<3 ps) and a 100 ps resolution step, plus Fig. 12's DNL/INL. The problem is that Fig. 12 is explicitly a test of the data frame's nonlinearity, i.e., the digital encoding logic, which is deterministic and essentially linear by construction; it cannot reveal serializer-induced timing distortion. This is not an internal inconsistency, but it is a missing verification that the headline numerical claims require. The reader's weakest_assumption points at the same underlying physical premise, but the sharper issue is evidential: the reported DNL/INL are not measurements of the output signal. Since the design is plausible and the gap is addressable with a physical pulse-width sweep, I do not reject the paper; the conditional verdict stands. Adding a physical linearity measurement and jitter decomposition would be the necessary condition for acceptance.","tokens_in":8265,"tokens_out":4567,"duration_ms":47625,"concrete_test":"Sweep all or a dense representative subset of timing codes from 1 ns to 40 µs, and for each code capture at least 100 output pulses on the same 13 GHz, 40 GSPS oscilloscope used for Fig. 9; measure the actual pulse width at a fixed threshold, compute physical DNL/INL versus code, and plot the deviation against run length and number of one-bits. If physical DNL/INL stay within -0.02/0.02 and -0.04/0.03 LSB across the range, the linearity claim is supported; if not, the digital-frame-only measurement cannot stand in for output linearity.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claim, DNL of -0.02/0.02 LSB and INL of -0.04/0.03 LSB across 1 ns to 40 µs, is supported in §3 only by Fig. 12, which is described as testing the linearity of the 32-bit data frame ('We tested the INL and DNL of the data frame'). The data frame is an arithmetic encoding of the number of one-bits; its linearity is a property of the counter/logic, not of the generated pulse widths. The physical output linearity depends on GTX serializer bit positions, pattern-dependent jitter, output-driver duty-cycle distortion, and reference-clock jitter, none of which is characterized. The two precision measurements (Fig. 9, Fig. 10) cover only the endpoints, and Fig. 11 demonstrates resolution at one code. Thus the abstract's 'entire range' linearity figures are not tied to measured analog timing intervals. This is the load-bearing gap: without physical-width DNL/INL, the headline numbers could be trivially perfect for the frame code while the actual output deviates by many LSBs at specific codes.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a digital-to-time converter (DTC) implemented with a Xilinx Kintex-7 GTP/GTX-class high-speed transceiver. Time information is encoded in real time into 32-bit parallel data frames whose run of 1-bits determines the output pulse width after serialization at 10 Gbps, giving a nominal 100 ps resolution. The design also supports timing-sequence and random-interval outputs via a phase accumulator and multiple LFSRs. Experimental results report a minimum interval of 1.0179 ns, a maximum interval of 40.000109 µs, a <3 ps standard deviation at those endpoints, a 100 ps resolution step, and DNL/INL of -0.02/0.02 LSB and -0.04/0.03 LSB, respectively. The paper claims calibration-free operation and variable resolution through clock reconfiguration.","tokens_in":8505,"tokens_out":3429,"duration_ms":34359,"significance":"If the central claims hold, the paper offers an unusually simple and attractive DTC architecture: the output time interval is defined directly by the serialized bit pattern, with no fitted parameters, no lookup-table calibration, and no analog delay-line tuning. The measured oscilloscope traces are consistent with the claimed resolution and endpoint behavior, and the real-time encoding strategy is clever for avoiding large on-chip memories. The main significance would be a low-resource FPGA DTC with a very wide dynamic range and good linearity. However, the headline linearity and precision numbers are currently supported only by data-frame simulations and two endpoint measurements, not by physical output-edge characterization across the range, so the significance is not yet established at the claimed level.","major_comments":[{"comment":"The DNL/INL values quoted in the abstract and conclusion (-0.02/0.02 LSB and -0.04/0.03 LSB) are measured on the 32-bit data frame, not on the physical output timing edges, as the text explicitly states: \"We tested the INL and DNL of the data frame.\" The linearity of the frame composition logic is a property of digital arithmetic and is not the same as the linearity of the realized pulse widths, because the serializer bit positions, pattern-dependent jitter, output-driver duty-cycle distortion, and clock path can all add code-dependent timing errors. This gap is load-bearing: the claim that these values hold \"across the entire range\" is not supported by the measurements shown. The authors should measure DNL/INL on the actual output pulse widths (e.g., by time-interval measurements over a dense set of codes spanning 1 ns to 40 µs) and report those results as the DTC linearity.","section":"Section 3, Fig. 12"},{"comment":"The precision claim of \"standard deviation less than 3 ps\" over the entire dynamic range is supported only by two static measurements at 1.0179 ns and 40.000109 µs. In a serializer-based DTC, output jitter and timing error can be pattern-dependent and code-dependent, because different codes produce different bit patterns and different transition positions in the serial stream. Two endpoints do not establish consistency across the full range. Please provide precision/jitter measurements at several intermediate code values and describe the acquisition procedure (number of samples, measurement method), or restrict the claim to the measured endpoints.","section":"Section 3, Figs. 9 and 10"}],"minor_comments":[{"comment":"The phrase \"across the entire range\" is used in the abstract and in Table 2's comparison, but the supporting measurement (Fig. 12) is explicitly a data-frame test. Consider rewording to avoid confusing digital-frame linearity with analog-output linearity until the physical-edge measurements are available.","section":"Abstract and Section 3"},{"comment":"The claim that the random timing signal obeys a uniform distribution is not quantified; provide a histogram of the measured intervals, the sample size, and a statistical test (e.g., chi-square) rather than only a label on the oscilloscope trace.","section":"Section 3, Fig. 14"},{"comment":"The timing-sequence demonstration shows a repeating nine-pulse pattern, but no expected-versus-measured interval table is given. Adding quantitative values would strengthen the multifunctionality claim.","section":"Section 3, Fig. 13"},{"comment":"The sentence \"To keep the data original, the 8B/10B encoding function will not be used\" should explain how this is configured in the transceiver and whether disabling 8B/10B affects transmitter constraints such as DC balance or run-length limits.","section":"Section 2.3"},{"comment":"There is a typo in the title: \"conver ter\" should be \"converter.\"","section":"Title"}],"recommendation":"major_revision","confidential_remarks":"The manuscript is within scope and the basic idea is appealing, but the central quantitative claims (whole-range DNL/INL and <3 ps precision) are currently supported only by a data-frame test and two endpoint measurements. This is a fixable deficiency: if the authors add physical output-edge DNL/INL and intermediate-code jitter measurements, the paper could become acceptable. I would not reject outright because the concept appears sound and the oscilloscope traces are consistent with the intended mechanism."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThis is a genuine new FPGA trick: use a GTX transceiver as a DTC, with real-time frame encoding so you don't need a large lookup table. The measured min/max intervals (1.0179 ns, 40.000109 µs) with ~2 ps sigma are plausible and the resource use is small. The multifunction output (sequences and random intervals) is a nice practical add.\n\nThe important caveat is exactly what the stress-test says: the INL/DNL numbers in the abstract come from Fig. 12, which tests the data frame, not the physical output edges. The frame is just an arithmetic count of one-bits; its linearity is a property of the logic, not of the analog pulse widths. Pattern-dependent jitter in the serializer, output driver duty-cycle distortion, and reference clock jitter are all uncharacterized. So the \"entire range\" linearity claim is unsupported. The precision is also only shown at the two endpoints, not across the range. Reconfigurability (variable resolution) is stated but not demonstrated. There's also a minor internal inconsistency: the abstract and intro say dynamic range starts at 1 ns, while Sec. 2.1 says 2 ns. No code or data is released.\n\nThe core idea holds up as a concept. The fix is straightforward: measure output pulse widths directly across codes, report edge-to-edge INL/DNL, and document the jitter budget. The random signal section would also benefit from a histogram and a uniformity test.\n\nWho is this for? People building FPGA-based time-domain instrumentation who want a wide-range, moderately-resolved, calibration-free generator. It is not a field-changer, since 100 ps resolution is modest, but it's a useful engineering data point.\n\nI'd send it to review: the architecture is novel enough relative to the cited FPGA DTC work, and the weaknesses are addressable. The authors should be pushed to provide physical-output linearity and release code/data. My verdict would be conditional acceptance after major revision.","headline":"Clever repurposing of an FPGA GTX transceiver as a DTC, but the headline linearity numbers come from the digital frame, not the physical output edges.","tokens_in":9022,"tokens_out":2863,"would_cite":false,"duration_ms":28743,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"An FPGA's high-speed transceiver can act as a calibration-free digital-to-time converter with 100 ps resolution.","keywords":["digital-to-time converter","high-speed transceiver","FPGA","timing signal generation","calibration-free","pulse generator","real-time encoding","time interval"],"falsifier":"Measure the output pulse width for every 32-bit frame (or a dense subset covering run lengths from 1 to 32 and all transition positions) with a reference time base whose jitter is below 1 ps, and check whether any width deviates from the integer-multiple prediction by more than the claimed sub-3 ps precision; a single pattern-dependent deviation above that bound would falsify the calibration-free claim.","tokens_in":8092,"feed_emoji":"⏱️","tokens_out":9411,"duration_ms":83697,"temperature":0.7,"pith_summary":"This paper claims that an FPGA's high-speed transceiver can serve as a calibration-free digital-to-time converter with 100 ps resolution, a dynamic range from 1 ns to 40 µs, and linearity of about 0.02-0.04 LSB. The key idea is to encode each desired time interval as a number of consecutive 1s in a parallel data frame, serialize that frame at 10 Gbps, and let the output pulse width equal the 1-count times the 100 ps bit period. A real-time encoding scheme stitches intervals across 32-bit frames, so arbitrary-length sequences and random intervals can be produced without large memory tables. On the tested FPGA the authors report sub-3 ps standard deviation across the full range and both sequence and random-signal output modes. If this holds, it gives a simple, reconfigurable DTC that avoids the calibration burden of delay-line designs.","feed_headline":"FPGA transceiver makes 100 ps timing pulses, no calibration","feed_subtitle":"Serializing runs of 1s at 10 Gbps yields 1 ns-40 µs intervals with sub-3 ps precision.","key_machinery":"The load-bearing mechanism is the real-time frame encoder feeding the FPGA's GTX, a high-speed serial transceiver. Each timing parameter Ti is turned into Ti/100 ps consecutive 1s; because the serializer emits one bit every 100 ps at 10 Gbps, the high level duration equals the 1-count times 100 ps. To handle intervals longer than 32 bits or starting mid-frame, the encoder splits each 32-bit output into Part1 (high bits, current interval) and Part2 (low bits, next interval), and the decode pseudocode (Fig. 6) selects among three cases: the frame completes the interval exactly, the interval overflows the frame, or the frame has spare bits, in which case the remainder is carried into Part2. The transceiver's serializer then outputs the frame unchanged (8B/10B bypassed), so the encoded 1-run becomes the pulse width.","core_discovery":"The central claim is that a standard high-speed serializer with 8B/10B encoding disabled can synthesize timing signals directly: the output pulse's high time is the number of consecutive 1s times the 100 ps serial bit period. The paper's real-time decoding algorithm converts time parameters into 32-bit frames composed of a Part1 field (current interval) and a Part2 field (next interval) whose valid bit widths always sum to 32, so the bitstream never pauses and no deep memory is needed. The authors measure a 10 Gbps transceiver implementation and obtain 100 ps resolution, 1.0179 ns to 40.000109 µs range, DNL between -0.02 and 0.02 LSB, INL between -0.04 and 0.03 LSB, and a standard deviation below 3 ps. They also demonstrate two output modes: a timing sequence with user-defined variable intervals and a random timing signal whose intervals are uniformly distributed.","pith_inferences":["An unstated sensitivity is pattern-dependent jitter in the serializer: run lengths and transition density vary from frame to frame, and the reported <3 ps precision may not be uniform across all 32-bit patterns; measuring every possible frame's width would test this.","The architecture is essentially a pulse-density modulation at 10 Gbps, so low-pass filtering the output could extend the DTC into an arbitrary waveform generator, a direction the authors do not explore.","The claimed 'calibration-free' property rests on the transceiver's clock stability; if a lower-cost FPGA with a noisier PLL is used, the same encoding would likely show worse INL, meaning the method transfers the calibration burden from delay taps to the clock source.","The uniform-random certification is only statistical; a longer capture and a chi-square or spectral test would be needed to verify the m-sequence combination's randomness, especially because the period of the combined sequence is the product of 12 maximal-length sequences, which may still produce detectable periodicities."],"forward_implications":["The same encoding scheme should scale to faster transceivers: a 25 Gbps link would give 40 ps resolution with the same architecture and no calibration.","Because the time base is the serial clock rather than a delay chain, temperature and voltage drift affect only the clock frequency, which can be disciplined, instead of each tap's delay.","The 32-bit frame plus 10 Gbps bit rate bounds the maximum single-frame interval at 3.2 ns; the encoding's carry mechanism is what extends the range to 40 µs, so wider frames or faster clocks would extend the range further.","The random-interval output, based on multiple m sequences read in parallel, gives a uniform distribution that is directly useful for dithering in power converters and motor drives.","The resource cost is small (about 5,000 flip-flops plus one transceiver), so the DTC can be embedded in a larger FPGA design without a separate timing chip."],"supporting_citations":[{"why":"Supplies the nearest FPGA-based prior art, a DSP-block delay-line DTC, used as the comparison baseline for resolution, linearity, and dynamic range.","marker":"[29]"},{"why":"Provides the time-folding arbitrary-timing baseline that this method is compared with on high-resolution FPGA timing.","marker":"[30]"},{"why":"Represents the delay-line pulse-train DTC baseline whose calibration and dynamic-range trade-offs motivate the proposed design.","marker":"[28]"},{"why":"Gives a simple FPGA delay-generator baseline from the direct-counting/delay-line family that typically needs calibration.","marker":"[24]"},{"why":"Shows a Vernier carry-chain delay generator, illustrating the narrow dynamic range the transceiver method avoids.","marker":"[27]"}],"fun_headline_variants":["No-calibration FPGA transceiver yields 100 ps timing","FPGA serializer generates 100 ps pulses without calibration","Calibration-free timing: 100 ps resolution from FPGA transceiver","Reconfigurable DTC: FPGA transceiver hits 100 ps, no calibration","Serializer-based timing: 100 ps, no calibration, reconfigurable"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The entire accuracy depends on the assumption that the serializer reproduces the encoded run of 1s with negligible pattern-dependent jitter and that the reference clock's jitter is low enough that the pulse width is exactly the number of 1s times 100 ps; the paper asserts this via clock stability but does not decompose jitter sources.","fun_headline_variants_meta":{"raw":{"variants":["No-calibration FPGA transceiver yields 100 ps timing","FPGA serializer generates 100 ps pulses without calibration","Calibration-free timing: 100 ps resolution from FPGA transceiver","Reconfigurable DTC: FPGA transceiver hits 100 ps, no calibration","Serializer-based timing: 100 ps, no calibration, reconfigurable"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000635,"raw_usage":{"total_tokens":2938,"prompt_tokens":963,"completion_tokens":1975,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":579,"completion_tokens_details":{"reasoning_tokens":1885}},"tokens_in":579,"tokens_out":1975,"duration_ms":14460,"temperature":1.0,"reasoning_tokens":1885,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T19:46:00.616390+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the output pulse width for every 32-bit frame (or a dense subset covering run lengths from 1 to 32 and all transition positions) with a reference time base whose jitter is below 1 ps, and check whether any width deviates from the integer-multiple prediction by more than the claimed sub-3 ps precision; a single pattern-dependent deviation above that bound would falsify the calibration-free claim.","supporting_citations":[{"cited_title":"A Pico-Second Resolution Arbitrary Timing Generator Based on Tim e Folding and Time Interpolating","cited_arxiv_id":null,"evidence_quote":"Provides the time-folding arbitrary-timing baseline that this method is compared with on high-resolution FPGA timing."},{"cited_title":"Digital-to-Time Converter with P ulse Train Generation Capabil- ity","cited_arxiv_id":null,"evidence_quote":"Represents the delay-line pulse-train DTC baseline whose calibration and dynamic-range trade-offs motivate the proposed design."},{"cited_title":"A Simple Field Programmable Gate Array (FPGA) Based High Precision Low- Jitter Delay Generator","cited_arxiv_id":null,"evidence_quote":"Gives a simple FPGA delay-generator baseline from the direct-counting/delay-line family that typically needs calibration."},{"cited_title":"A High-Resolution Programmable Vernier Delay Generator Based o n Carry Chains in FPGA","cited_arxiv_id":null,"evidence_quote":"Shows a Vernier carry-chain delay generator, illustrating the narrow dynamic range the transceiver method avoids."}],"review_version":1}