{"id":"586de52b-75e3-488c-93f7-07c4a52b9d63","arxiv_id":"2412.09010","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":7.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A differentiable spike-time discretization makes ODE-based physical neural networks of IMC circuits trainable at scale, and including reversal-potential nonidealities cuts model-to-SPICE timing error by over 20 times.","lead":"This paper trains neural networks on an ODE model of analog in-memory computing circuits whose currents depend on voltage, instead of pretending the hardware is ideal. It introduces a discretization trick that makes training fast enough for CIFAR-10, and shows in a small post-layout SkyWater chip that the physical model tracks SPICE spike timing about 20 times better than a standard ANN mapping.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The order-of-magnitude hardware claim rests on a single global lambda per polarity, while SI G.1 reports about 5% per-device CLM variation; the 1.97 ns RMSE does not bound the resulting per-synapse E_rev spread.","rationale":"Reading in good faith, the paper's main contributions are DSTD and the ODE-based physical neural network, and the hardware experiment is a supporting demonstration. The DSTD convergence proof is plausible, and the method is genuinely useful for training ODE-based spiking models. The weakest part of the central claim is not the CIFAR-10 accuracy, which is modest but consistent, but the assertion of a robust order-of-magnitude reduction in model-to-hardware discrepancy. The reader identified the linear constant-coefficient MOSFET model as the weak assumption; I agree, but I would sharpen it: the more concrete issue is the paper's own measured 5% variation in lambda across weight currents, which makes a single global E_rev per polarity inexact. This is a calibration-sensitivity issue, not an indictment of the approach. It can be settled by re-running the mapping with per-synapse lambda values or a Monte-Carlo spread. If the 20x margin survives, the paper should be accepted; if not, the claim should be qualified. Since the reader already set CONDITIONAL and my concern is one reason for that condition rather than a reason to move to ACCEPT or REJECT, the verdict remains UNCHANGED.","tokens_in":46093,"tokens_out":12224,"duration_ms":136511,"concrete_test":"Re-run the PNN-to-IMC forward model with per-synapse reversal potentials: for each weight current I_ij, extract lambda_N(V_g) and lambda_P(V_g) from the I-V sweeps underlying Figs. 15a-d and set beta_ij = V_th * lambda(w_ij) instead of the global values in Table 2. Apply this model to the same 50 Iris test samples and compare the resulting output spike times to the existing post-layout SPICE waveforms. Also run a Monte-Carlo sweep of +/-5% in lambda for both the PNN and ANN mapping schemes. If the per-synapse lambda model keeps the PNN RMSE below about 5 ns and the order-of-magnitude margin survives the lambda spread, the concern is resolved; if RMSE rises toward the 20-40 ns range, the headline hardware claim is not robust to the measured device variation.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that PNN-to-IMC mapping reduces spike-timing discrepancy by at least an order of magnitude is load-bearing on the circuit-to-ODE equivalence in SI A.2, Eqs. (70)-(77). There, the current-source nonideality is reduced to an RC-Spike model with one constant lambda_N and one constant lambda_P, and Eq. (8) in Methods uses global E_rev values for all synapses of a given polarity. The paper's own device data in SI G.1 (Figs. 15c-d) show that the CLM coefficient varies by about 5% with the programmed synaptic current, i.e., with the gate bias of each weight transistor. Table 2 instead fixes lambda_N = 0.41 and lambda_P = 0.75. Thus the model ignores a measured per-synapse spread in the effective reversal potential, not just a small extrapolation outside the fitted voltage range. The reported PNN-to-IMC RMSE of 1.97 ns was obtained with this simplified global-lambda model, and no sensitivity analysis quantifies how a 5% lambda spread propagates to output firing times. Because the ANN-to-IMC baseline error is 39.04 ns, a per-synapse correction of only a few nanoseconds could preserve the claim, but a spread of tens of nanoseconds would erase it. The paper itself notes in SI G.1 that a current-dependent E_rev would be more accurate, but it does not quantify the error caused by omitting it.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a bottom-up, physics-aware training framework for charge-domain analog in-memory computing (IMC). It models IMC circuit nonidealities, specifically the membrane-potential dependence of synaptic currents, as reversal potentials in an ODE-based physical neural network (PNN) called RC-Spike. To make training tractable at scale, the paper introduces differentiable spike-time discretization (DSTD), which approximates continuous spike times by differentiable discrete-time spike variables and is claimed to reduce computational cost from quadratic to linear in the number of input spikes. The authors prove approximation-error bounds for DSTD, demonstrate its use on Fashion-MNIST and CIFAR-10 with both RC-Spike and time-to-first-spike (TTFS) networks, and design a sky130 post-layout IMC circuit. They report that mapping a trained PNN to the circuit reduces output-layer spike-timing RMSE from 39.04 ns (ANN-to-IMC mapping) to 1.97 ns (PNN-to-IMC mapping), an order-of-magnitude improvement, and that finite reversal potentials can improve rather than degrade learning performance.","tokens_in":46382,"tokens_out":6302,"duration_ms":69333,"significance":"If the claims are fully supported, the paper makes a significant contribution. It provides an explicit circuit-to-ODE equivalence for charge-domain IMC with nonideal current sources, an analytical solution for the resulting neuron model, and a scalable training method (DSTD) with convergence guarantees. The CIFAR-10 results show that reversal-potential nonidealities can be harnessed rather than merely compensated, which is a non-obvious and potentially useful finding. The use of a post-layout SPICE simulation in an open-source sky130 process is a concrete and reproducible form of hardware validation, and the paper is careful to state the assumptions of the linearized MOSFET model. However, the central order-of-magnitude hardware claim is currently supported only by a within-sample fit: the nonideality parameters are extracted from the same circuit simulation used for evaluation, and the measured per-synapse spread in channel-length modulation is not propagated to the reported timing error. These issues do not invalidate the approach but they do require additional analysis before the headline claim is fully established.","major_comments":[{"comment":"The order-of-magnitude discrepancy claim rests on representing each MOSFET polarity by a single constant channel-length-modulation coefficient (lambda_N=0.41, lambda_P=0.75), but Figs. 15c-d show that the CLM coefficient varies by roughly 5% with the programmed synaptic current, and the text acknowledges that a current-dependent reversal potential E_rev(.) would be more accurate. No sensitivity analysis bounds how this measured per-synapse spread propagates to the output-layer firing-time RMSE. Because the reported PNN-to-IMC RMSE of 1.97 ns is much smaller than the ANN-to-IMC value of 39.04 ns, the claim may survive a 5% variation, but the paper must quantify this, for example by drawing per-synapse lambda values from the measured spread and re-running the model-to-SPICE comparison, or by deriving an analytic bound. Without this, the central 'at least an order of magnitude' conclusion is not established for the actual circuit with nonuniform devices.","section":"Section 2.3 and SI G.1, Eqs. (70)-(71), Table 2"},{"comment":"The PNN-to-IMC validation is a within-sample fit: lambda_N, lambda_P, lambda_dis, the resulting E_rev values, and the current scaling are all extracted from post-layout SPICE simulations of the exact same circuit instance used for the discrepancy evaluation. The 1-dimensional scaling for PNN-to-IMC mapping and the 2-dimensional scaling for ANN-to-IMC mapping are also tuned on the same SPICE results. The manuscript should either present an out-of-sample test (e.g., a different process corner, a Monte Carlo process-variation run, or a hold-out circuit instance) or explicitly qualify the claim as reproduction of the fitted circuit rather than prediction for a new circuit. As written, the 'reduces discrepancy' wording overstates what is demonstrated.","section":"Section 2.3, Algorithms 5-6, SI F"},{"comment":"The main text states the DSTD error as O(Delta_tau^2 |E_rev|^{-1}), but the proof in SI B.1 establishes O(Delta_tau^2) for fixed reversal potential and SI B.2 establishes O(|E_rev|^{-1}) for fixed step size. The combined dependence is not proven; the error expression in B.2 contains terms that depend on both Delta_tau and beta, and the proof does not show a uniform bound of the form C * Delta_tau^2 * beta. Please either supply the combined bound or restate Theorem 1 as two separate convergence statements. This matters because the main text uses the combined order to motivate the efficiency-accuracy trade-off of DSTD.","section":"Section 4.4, Eq. (49), and SI B.2"}],"minor_comments":[{"comment":"In Eq. (48), the conditions for the spike variable s^{(l-1)}_{jm} reference t^{(l)}_i, but the variable being defined is the discretized input spike from neuron j, so the condition should refer to t^{(l-1)}_j throughout.","section":"Section 4.4, Eq. (48)"},{"comment":"The text and figure caption use 'SNN-to-IMC mapping' where the intended term is 'PNN-to-IMC mapping'; this is inconsistent with the rest of the paper and should be corrected.","section":"Section 2.3 and Fig. 5h"},{"comment":"There are numerous typos and formatting inconsistencies, including 'CIF AR-10' instead of 'CIFAR-10', 'refered' instead of 'referred', 'recieved' instead of 'received', 'membrene' instead of 'membrane', and 'Oder' instead of 'Order'. A careful proofread is needed.","section":"Throughout"},{"comment":"Table 2 lists the membrane capacitance Cm as 140 fF, while SI G.2 states that the MIMCAP in the layout has a capacitance of 103.3 fF. Please clarify whether the model uses the MIMCAP value plus parasitic capacitance or some other convention.","section":"Table 2 and SI G.2"}],"recommendation":"major_revision","confidential_remarks":"The paper is a strong systems-oriented contribution, and the core idea of training directly on the circuit's ODE dynamics is timely and relevant. The main risk is that the headline hardware claim is presented as a validation but is currently a within-sample fit without sensitivity analysis. I would encourage the editor to request that the authors either provide the sensitivity analysis described in the report or soften the claim to 'reproduces the fitted circuit dynamics.' The paper would also benefit from releasing the SPICE netlists or simulation scripts, since reproducibility is a stated value of the open-source sky130 workflow."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick take: this is the first paper I've seen that trains ODE-based physical neural networks with reversal potentials at CIFAR-10 scale, and DSTD is the reason. The differentiable spike-time discretization is simple, the O(Delta^2 |E_rev|^-1) bound is proved in the SI, and the speed/memory figures come from a complexity argument plus GPU measurements. That alone is a citable contribution for the spiking/temporal-coding crowd.\n\nThe circuit half is more mixed but still earnest. The equivalence between the RC-Spike ODE and the linearized MOSFET current-source model is derived cleanly in SI A.2. Using post-layout sky130 SPICE rather than an idealized macro-model is the right way to test the idea. But the evidence stops short of the abstract's \"by at least an order of magnitude\" in an important way: lambda_N, lambda_P, lambda_dis, and the current scaling are all fitted to the same small 5-5-5 circuit, and SI G.1 admits the CLM coefficient varies by about 5% with programmed current. The model uses one global E_rev per polarity, so it ignores a measured per-synapse spread. The reported 39 ns vs 1.97 ns RMSE gap is large enough that a plausible few-percent lambda spread probably does not erase the qualitative conclusion, but the paper does not show that. A sensitivity analysis over the observed lambda distribution would settle it. Also, CIFAR-10 gains are modest and the summary table gives no error bars, so the \"exploiting nonidealities\" claim should be read as \"doesn't hurt much,\" not as a clear accuracy win.\n\nOther soft spots: no code or data release, and the hardware demo is a single tiny Iris task. Those are fixable in revision. The citation pattern looks fair; RC-Spike is properly credited to their earlier ISCAS paper, and the comparison with surrogate-gradient and timing-based SNN training is accurate.\n\nWho this is for: people working on analog IMC, physical neural networks, or temporal coding in SNNs. It deserves a serious referee — the DSTD theorem and the post-layout validation are real evidence, and a good referee will ask for the sensitivity analysis and code. I would cite it for DSTD even though I do not buy the strongest hardware claim yet.","headline":"DSTD is a real, useful training trick with a proof, and the post-layout IMC validation is honest hardware work; just don't take the 20x discrepancy reduction as a general law until the per-synapse nonideality spread is quantified.","tokens_in":46963,"tokens_out":2359,"would_cite":true,"duration_ms":25914,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Training physical ODE models of analog in-memory circuits cuts model-to-hardware spike-timing error by an order of magnitude and turns a circuit nonideality into a learnable feature.","keywords":["analog in-memory computing","physical neural networks","reversal potential","spiking neural networks","differentiable spike-time discretization","RC-Spike model","hardware nonidealities","ODE-based training"],"falsifier":"Measure the drain current of the memory MOSFETs over a wider membrane-potential range (e.g., 0.1 V to 1.7 V) and fit the residual against the linear model; if the second derivative of $I_D$ versus $V_{DS}$ exceeds the reported roughly 5% channel-length-modulation variation, retrain the PNN and check whether the 1.97 ns RMSE degrades toward the ANN baseline.","tokens_in":45873,"feed_emoji":"⚡","tokens_out":3633,"duration_ms":35317,"temperature":0.7,"pith_summary":"The paper claims that the nonideal voltage dependence of synaptic currents in charge-domain in-memory computing circuits can be modeled exactly as reversal potentials in an ODE-based spiking neuron model, and that training the resulting physical neural network eliminates most of the model-to-hardware gap. On a post-layout sky130 circuit, the output-layer spike-timing error drops from 39.04 ns for conventional ANN mapping to 1.97 ns for the physics-based mapping. To make such training tractable at scale, the paper introduces differentiable spike-time discretization (DSTD), which reduces computational cost from quadratic to linear in spike count and enables convolutional networks on CIFAR-10. The authors further show that reversal potentials, usually considered a defect, can improve learning performance when the model accounts for them.","feed_headline":"Physics-trained model beats ANN mapping 20x on spike timing","feed_subtitle":"Training on the circuit's own differential equations cuts model-to-hardware error from 39 ns to under 2 ns.","key_machinery":"The central object is the RC-Spike model, a spiking neuron whose membrane potential evolves as $dv/dt = -f(t) v + g(t)$ with reversal potentials $E^\\pm_{\\mathrm{rev}}$ bounding the membrane potential; it reduces to ideal charge-domain computing as $|E^\\pm_{\\mathrm{rev}}|\\to\\infty$. The load-bearing identity is the linearized MOSFET current model $I_D \\approx I(1+\\lambda V_{DS})$ (channel-length modulation), which converts the circuit equations into the same ODE form as the neuron model. DSTD then discretizes spike arrival times onto a regular grid with triangular real-valued spike variables, making the whole computation differentiable and cheap while retaining an $O(\\Delta\\tau^2)$ error bound.","core_discovery":"On the paper's own terms, the central discovery is that the RC-Spike neuron model, which adds reversal potentials $E^\\pm_{\\mathrm{rev}}$ to a non-leaky integrate-and-fire dynamics, is mathematically equivalent to a charge-domain IMC circuit whose synaptic currents depend linearly on membrane potential. Because of that equivalence, training the PNN with the measured reversal potentials yields spike timing predictions that match post-layout SPICE simulations with an order-of-magnitude smaller error than mapping a trained ANN. The paper also proves that DSTD approximates the exact ODE solution with error $O(\\Delta\\tau^2 |E^\\pm_{\\mathrm{rev}}|^{-1})$, and demonstrates that convolutional networks trained this way reach peak accuracy at finite, non-ideal reversal potentials rather than in the ideal limit.","pith_inferences":["If the linear $\\lambda$ model holds beyond the fitted 0.46-1.36 V range, the same bottom-up strategy could be applied to other nonidealities such as IR drop or sneak currents by adding them as state-dependent terms.","The DSTD error bound suggests that random offset acts as a gradient denoiser, so one could test whether fewer steps suffice for other ODE-based physical neural networks.","The claim that nonidealities can be 'harnessed' implies hardware designers might deliberately bias circuits toward regimes with strong, predictable nonlinearity instead of linearizing them.","A testable extension is to train the RC-Spike PNN on measured $\\lambda_N$, $\\lambda_P$, and $\\lambda_{\\mathrm{dis}}$ from a fabricated chip and compare closed-loop accuracy against post-layout simulation."],"forward_implications":["The PNN-to-IMC mapping reduces output-layer spike-timing RMSE from 39.04 ns to 1.97 ns on the post-layout sky130 circuit.","DSTD gives up to 20x speedup and 100x memory reduction for RC-Spike models, and larger gains for TTFS-SNN models.","Convolutional RC-Spike networks can be trained on CIFAR-10 with DSTD, with accuracy peaking at finite reversal potentials around $|E^\\pm_{\\mathrm{rev}}|\\approx 3$.","ANN-to-IMC mapping with optimal positive/negative weight scaling still degrades markedly when $|E^\\pm_{\\mathrm{rev}}|<4$, while the physics-trained model does not.","The circuit-model equivalence extends to both resistor-based 1T1R synapses and MOSFET current sources with measured $\\lambda$ coefficients."],"supporting_citations":[{"why":"Defines the RC-Spike model with reversal potentials that the paper uses as the physical neural network.","marker":"[44]"},{"why":"Provides the ideal charge-domain IMC operation that the RC-Spike model recovers in the infinite-reversal-potential limit.","marker":"[20]"},{"why":"Supplies a charge-domain SRAM IMC implementation whose phase-based operation the designed circuit follows.","marker":"[36]"},{"why":"Documents analog circuit nonidealities as the source of model-to-hardware inference errors that the paper targets.","marker":"[25]"},{"why":"Identifies the sky130 open-source PDK used for the post-layout circuit design and simulation.","marker":"[34]"},{"why":"Represents the adjoint-method ODE training baseline that DSTD avoids because of computational cost.","marker":"[75]"},{"why":"Frames the physics-aware training paradigm that the paper extends to IMC circuits through ODE-based PNNs.","marker":"[31]"}],"fun_headline_variants":["Train on analog ODEs to exploit nonidealities, cut error 10x","ODE-trained PNN beats ANN mapping: 20x speedup, 10x accuracy","Embrace nonideal analog: physical training wins over mapping","Physics-coded IMC: 100x memory savings, 10x error drop"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"Everything rests on the claim that the synaptic current depends linearly on membrane potential with constant coefficients $\\lambda_N$, $\\lambda_P$, and $\\lambda_{\\mathrm{dis}}$; if that linear fit breaks outside the tested voltage range or under device variation, the circuit-to-model equivalence and the order-of-magnitude error reduction no longer follow.","fun_headline_variants_meta":{"raw":{"variants":["Train on analog ODEs to exploit nonidealities, cut error 10x","ODE-trained PNN beats ANN mapping: 20x speedup, 10x accuracy","Embrace nonideal analog: physical training wins over mapping","Physics-coded IMC: 100x memory savings, 10x error drop"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000778,"raw_usage":{"total_tokens":3442,"prompt_tokens":954,"completion_tokens":2488,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":570,"completion_tokens_details":{"reasoning_tokens":2402}},"tokens_in":570,"tokens_out":2488,"duration_ms":18616,"temperature":1.0,"reasoning_tokens":2402,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T17:21:20.471080+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the drain current of the memory MOSFETs over a wider membrane-potential range (e.g., 0.1 V to 1.7 V) and fit the residual against the linear model; if the second derivative of $I_D$ versus $V_{DS}$ exceeds the reported roughly 5% channel-length-modulation variation, retrain the PNN and check whether the 1.97 ns RMSE degrades toward the ANN baseline.","supporting_citations":[{"cited_title":"Sakemi, K","cited_arxiv_id":null,"evidence_quote":"Defines the RC-Spike model with reversal potentials that the paper uses as the physical neural network."},{"cited_title":"Bavandpour, M","cited_arxiv_id":null,"evidence_quote":"Provides the ideal charge-domain IMC operation that the RC-Spike model recovers in the infinite-reversal-potential limit."},{"cited_title":"Yamaguchi, G","cited_arxiv_id":null,"evidence_quote":"Supplies a charge-domain SRAM IMC implementation whose phase-based operation the designed circuit follows."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Documents analog circuit nonidealities as the source of model-to-hardware inference errors that the paper targets."},{"cited_title":"readthedocs.io/en/main/","cited_arxiv_id":null,"evidence_quote":"Identifies the sky130 open-source PDK used for the post-layout circuit design and simulation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Represents the adjoint-method ODE training baseline that DSTD avoids because of computational cost."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Frames the physics-aware training paradigm that the paper extends to IMC circuits through ODE-based PNNs."}],"review_version":1}