{"id":"9ab170c8-fb79-496c-bed3-2a05be8e71af","arxiv_id":"2412.09291","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":6,"one_line_summary":"A two-step vapor deposition process grows tellurium nanowire and molybdenum disulfide heterojunctions and separate FETs on one wafer, enabling a diode, a CMOS inverter, and basic logic gates on the same platform.","lead":"This paper reports a two-step vapor growth method that places tellurium nanowires and molybdenum disulfide flakes on the same chip, forming 1D/2D junctions. The authors use these junctions as diodes and pair the individual materials as transistors to build inverters and logic gates, aiming at unified analog and digital circuits from one substrate.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"KPFM work-function/surface-potential sign inconsistency leaves the built-in potential and charge-transfer direction ambiguous.","rationale":"The paper's strongest contribution is the two-step growth plus the device-level demonstration of a diode, p/n FETs, a CMOS inverter, and logic gates on one substrate. Those measurements are largely self-contained and would still be informative even if the KPFM band-alignment story were corrected. However, the abstract and conclusions explicitly claim that the atomically thin depletion region and type-I band alignment are revealed and confirmed by KPFM/DFT; the internal sign/surface-potential contradiction makes those specific claims unverified. The reader's CONDITIONAL verdict already captures this. I do not see grounds to reject: the rectification, gate modulation, and logic outputs are reported with sufficient detail to be checked independently, and a corrected KPFM analysis would either strengthen the p-n picture or require only a revised interpretation of the band offsets. I therefore recommend keeping the verdict unchanged, with the condition that the authors clarify the KPFM sign convention, the Vbi value, and the electron-transfer direction.","tokens_in":16834,"tokens_out":10413,"duration_ms":98971,"concrete_test":"Re-analyze the raw KPFM line scans in Fig. 1(g) using the standard convention V_CPD = (Φ_tip − Φ_sample)/e, with the tip calibrated against a known reference such as Au or HOPG. Determine whether the measured CPD ordering gives W_Te < W_MoS2 or W_MoS2 < W_Te, and compare the resulting work-function difference with the reported knee voltage of ~0.14 V. Independently, perform UPS or XPS valence-band measurements on the as-grown Te and MoS2 regions to obtain absolute work functions. If W_Te < W_MoS2, the paper's claimed MoS2→Te transfer and the 0.19 eV Vbi are incorrect, and Vbi should be ~0.14 eV; if W_MoS2 < W_Te, the paper's conversion equation or substrate work-function assignment has a sign error.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claim—an atomically thin p-n depletion region of ~6.85 nm with Vbi = 0.19 V—rests on the KPFM work-function analysis in Section II, and that analysis is internally inconsistent. The paper defines ΔVCPD = (W_substrate − W_sample)/e and, with W_substrate = 5.05 eV, obtains W_Te = 4.96 eV and W_MoS2 = 5.15 eV. But the same paragraph states that MoS2 has a higher surface potential than Te by ΔVCPD = 0.14 V; under the stated convention, higher surface potential means lower work function, so this would imply W_MoS2 < W_Te, opposite to the assigned values. The quoted ΔVCPD(MoS2–Te) = 0.14 V also matches the reported knee voltage of ~0.14 V, whereas the assigned work-function difference is 0.19 eV—so Vbi is ambiguous. The claimed electron transfer direction (MoS2→Te) is likewise opposite to what W_Te < W_MoS2 would produce and opposite to the DFT Bader result (Te→MoS2). Since Vbi and the charge-transfer direction enter the depletion-width, electric-field, and type-I band-offset numbers, the paper's mechanistic interpretation is not established unless the KPFM sign convention is corrected.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This manuscript reports a sequential two-step vapor deposition route (CVD for MoS2, then PVD for Te nanowires) that produces mixed-dimensional van der Waals heterostructures on a single SiO2/Si substrate. The authors characterize the Te NW/MoS2 junctions as gate-tunable p-n diodes, extract a total depletion width of about 6.85 nm, and propose a type-I band alignment with a built-in potential of 0.19 V supported by KPFM, Raman spectroscopy, electrical transport, CAFM, and DFT-NEGF calculations. In the same platform, the isolated Te NWs and MoS2 flakes are used as p- and n-FETs, and ionic-liquid gating is used to demonstrate a CMOS inverter and AND/OR/NOT logic gates. The central claim is that this approach unifies analog diode devices and digital CMOS logic on one chip.","tokens_in":17124,"tokens_out":7035,"duration_ms":74970,"significance":"If the results hold, the paper would demonstrate a scalable, lithography-compatible route to mixed-dimensional 1D/2D vdW electronics, avoiding manual exfoliation and stacking. The breadth is a clear strength: growth, structural and optical characterization, transport measurements, first-principles transport calculations, and circuit-level demonstrations are all present. However, the quantitative diode picture—built-in potential, depletion width, band offsets, and charge-transfer direction—rests on a KPFM analysis whose sign convention is internally inconsistent. Because this inconsistency affects the central mechanistic claim, the paper cannot be accepted in its current form. The issue is potentially fixable, so I do not recommend rejection, but the experimental interpretation must be re-derived and clearly stated.","major_comments":[{"comment":"The KPFM analysis is internally inconsistent. The paper defines ΔVCPD = (W_substrate − W_sample)/e and then quotes W_Te = 4.96 eV and W_MoS2 = 5.15 eV with W_substrate = 5.05 eV. The same paragraph states that MoS2 has a higher surface potential than Te by ΔVCPD = 0.14 V and a higher surface potential than SiO2 by ΔVCPD = −0.10 V. Under the stated convention, a higher surface potential corresponds to a lower work function, so the reported contrast implies W_MoS2 < W_Te, opposite to the assigned values. The sentence about Te also appears garbled ('Te has lower (ΔVCPD = 0.09) work function than SiO2'). This contradiction matters because W_MoS2 − W_Te = 0.19 eV is used to define the built-in potential, the electron transfer direction from MoS2 to Te, and the type-I band offsets. The DFT Bader analysis in the same paper says electrons transfer from Te to MoS2, which is consistent with W_Te < W_MoS2 and not with the text's claimed MoS2→Te direction. The authors must re-derive the work functions from the raw KPFM data, state the sign convention unambiguously, and either reconcile the charge-transfer direction or revise the band-alignment and depletion-width conclusions (Vbi, ΔEC, ΔEV, WTe, WMoS2).","section":"Section II, KPFM paragraph"},{"comment":"The Raman evidence for charge transfer is presented with contradictory directions. The text says the MoS2 modes in the overlapped region show a finite red shift and interprets this as electron transfer from MoS2 to the Te NW. The caption of Fig. 1(e), however, says the inset shows an up shift of both MoS2 characteristic peaks in the overlapped region relative to pristine MoS2. Red shift and up shift are opposite observations. Since Raman is one of the two experimental probes used to establish the charge-transfer direction, the authors must report the actual measured peak positions (pristine MoS2 vs overlapped region) and state whether the shift is to lower or higher wavenumber; the present inconsistency leaves the Raman-based charge-transfer claim unsupported.","section":"Section II, Raman characterization and Fig. 1(e) caption"},{"comment":"The paper reports two different values for the maximum rectification ratio without reconciling them. In the CAFM paragraph, the heterojunction is said to yield a current rectification ratio of around 400 at ±10 V tip voltage. Two paragraphs later, the text states that the diode's highest rectification ratio is 180 at V_DS = 4, and the Conclusions repeat the value ~180. If these are different devices, different bias conditions, or different measurement techniques, that must be stated explicitly. As written, the reader cannot determine the actual maximum rectification ratio of the diode, which is a central quantitative device characteristic.","section":"Section II, CAFM and gate-tunable rectification paragraphs"},{"comment":"The doping density used in the DFT-NEGF simulation is not matched to the experimental values and is described with an apparent typo. The text says the simulation uses experimentally relevant doping densities of 10^14 cm^-3, while the Fig. 3 caption reads a carrier density of 10^-14 cm^-3, which is unphysical as a doping density. Even taking the intended value as 10^14 cm^-3, this is orders of magnitude smaller than the measured NA = 1.05 × 10^19 cm^-3 and ND = 2.36 × 10^18 cm^-3 reported earlier in the same paper. The claim that the DFT calculation 'confirms' the experimental band bending and built-in potential is therefore not quantitatively grounded. The authors should specify the compensation-charge model, give the actual charge densities used, and either match the experimental doping regime or clearly state that the DFT result is only qualitative.","section":"Section II, Theoretical results, and Fig. 3 caption"}],"minor_comments":[{"comment":"The sentence defining the rectification ratio says 'which compares forward current (If) and reverse currents (If)'—the second symbol should be Ir; please correct the notation.","section":"Section II, rectification ratio sentence"},{"comment":"The phrase 'defect-free interfaces' is used as a claim, but the paper provides no atomic-scale evidence (e.g., TEM or STM) for the absence of defects. I suggest tempering the wording to 'clean interfaces' or adding supporting evidence.","section":"Abstract and Section I"},{"comment":"The Te NW FET on-off ratio is reported as ~6.4, which is very low for a field-effect transistor; please specify whether this is the ratio of maximum to minimum current within the measured back-gate window and whether the device is fully depleted at negative gate voltages.","section":"Section II, FET mobility paragraph"},{"comment":"The sentence 'while Te has lower (ΔVCPD = 0.09) work function than SiO2' is grammatically ambiguous; it is unclear whether ΔVCPD = 0.09 refers to a surface-potential difference or a work-function difference.","section":"Section II, KPFM sentence"},{"comment":"References [36] and [37] already report Te/MoS2 1D/2D diodes and depletion-width estimates obtained by other growth methods; the Introduction and Conclusions should state more explicitly what new capability the present sequential CVD/PVD approach adds relative to those works.","section":"References and comparison to prior work"}],"recommendation":"major_revision","confidential_remarks":"The paper has a potentially interesting integration story, but the central diode interpretation depends on a KPFM sign convention that is currently self-contradictory. If the raw KPFM data actually imply W_MoS2 < W_Te, the band-alignment model and the depletion-width estimate will need to be substantially revised, and the DFT Bader result (Te→MoS2) would then be consistent with the corrected experimental picture. I would ask the authors to address this point with raw data before considering the paper for publication. The overlap with refs [36,37] should also be clarified in the revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The interesting part of this paper is the growth, not the physics. The authors grow MoS2 by CVD and then Te nanowires by PVD on the same SiO2 wafer, making 1D/2D heterojunctions in place rather than by exfoliation and stacking. That is a real synthesis advance, and they back it with a plausible demonstration: gate-tunable diode behavior, individual p- and n-FETs, and an IL-gated CMOS inverter with basic logic gates all on one substrate. If you work on mixed-dimensional vdW integration, this is worth a look.\n\nThe soft spots are in the interpretation. I checked the KPFM paragraph, and the stress-test concern holds up. The text says MoS2 has higher surface potential than Te, which under their own convention ΔVCPD = (W_substrate − W_sample)/e means W_MoS2 should be lower than W_Te. But they assign W_Te = 4.96 eV and W_MoS2 = 5.15 eV, the opposite ordering. That flips the claimed electron transfer direction and the built-in potential. The Raman evidence goes the same way: the main text says the MoS2 modes red-shift and attributes that to electron transfer from MoS2 to Te, while the Figure 1 caption says the peaks up-shift. You cannot have both. Since the depletion width (6.85 nm) and the band offsets all rest on Vbi from KPFM, those numbers are not established.\n\nThe DFT transport section also has a glaring numbers problem: it uses a doping density of 10^14 cm^-3 and calls it experimentally relevant, while the measured carrier densities in the FET sections are 10^18–10^19 cm^-3. That is five orders of magnitude off. The calculated built-in potential is 0.4 V, a factor of two above the experimental 0.19 V; they call it close.\n\nThe device results themselves look reasonable. The diode I-V curves and gate modulation are consistent with expectations for a Te/MoS2 junction. The CMOS gain of 1.2 is low for practical logic, but the inverter and logic demonstrations are honest proof-of-concept. The rectification ratio appears as 400 in the CAFM section and 180 in the two-terminal transport section; that is likely just a difference in bias range, but the paper should say so explicitly.\n\nRecommendation: this deserves serious peer review. The growth route is novel enough to justify referee time, and the device suite is broad. But the characterization and theory sections need real correction. The authors should fix the KPFM sign convention, reconcile the Raman shift statement with the caption, and justify or revise the DFT doping density. As it stands, I would not cite the band-alignment numbers, but I would cite the growth method once it is cleaned up.","headline":"A promising two-step vapor-growth route to mixed-dimensional Te/MoS2 circuits on one wafer, but the KPFM and Raman interpretations are internally inconsistent and need thorough correction before the band-alignment and charge-transfer claims can be trusted.","tokens_in":17719,"tokens_out":4937,"would_cite":true,"duration_ms":44304,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A two-step vapor recipe makes p-n diodes and CMOS logic on one chip.","keywords":["Te NW","MoS2","vapor deposition","vdW p-n junction","ionic liquid gating","CMOS inverter","logic gates","1D/2D heterostructure"],"falsifier":"Measure the contact-potential difference of the same Te NW/MoS2 junction against a reference metal with a calibrated Kelvin probe or ultraviolet photoemission spectroscopy; if the extracted work functions do not satisfy $W_{\\mathrm{Te}} < W_{\\mathrm{MoS_2}}$, then the type-I alignment, the 0.19 V built-in potential, and the 6.85 nm depletion width do not follow.","tokens_in":16654,"feed_emoji":"⚡","tokens_out":9179,"duration_ms":81729,"temperature":0.7,"pith_summary":"This paper claims that a two-step vapor deposition sequence—CVD for MoS2 flakes, then PVD for Te nanowires—can grow mixed-dimensional van der Waals heterostructures directly on a single SiO2 wafer, with the junction and the isolated materials available as devices on the same substrate. If true, the method would remove the exfoliate-and-restack step that usually limits vdW heterostructure fabrication, and would put diodes, p-type and n-type transistors, and CMOS logic within one platform. The paper supports the claim by showing gate-tunable rectification at the Te NW/MoS2 junction, an estimated atomically thin depletion region of about 6.85 nm, and working ionic-liquid-gated FETs that form an inverter and AND, OR, and NOT gates.","feed_headline":"Two-step growth puts p-n diodes and CMOS logic on one wafer","feed_subtitle":"Te nanowire/MoS2 junctions form atomically thin diodes while neighboring FETs run low-power gates.","key_machinery":"The central object is the 1D/2D van der Waals heterojunction formed where a tellurium nanowire crosses an MoS2 flake, created in place by a two-step vapor deposition process: atmospheric-pressure CVD grows MoS2 on SiO2/Si, and subsequent PVD grows Te nanowires over and around it. That junction carries a gate-tunable p-n diode with an atomically thin depletion region; Kelvin probe force microscopy-derived work functions set the band alignment, and an ionic liquid electric double layer supplies the high gate capacitance used to run the CMOS inverter and logic gates from the same substrate.","core_discovery":"The central discovery is that Te nanowires and MoS2 flakes grown sequentially by vapor deposition on one SiO2/Si substrate form a working mixed-dimensional electronics platform. At the overlapping Te NW/MoS2 junction, the paper reports a type-I band alignment with a built-in potential of about 0.19 V, a total depletion width of 6.85 nm, and a gate-tunable diode whose rectification ratio reaches around 180; first-principles transport calculations are presented as supporting the band bending and charge redistribution. Away from the junctions, the same growth gives p-type Te nanowire FETs and n-type MoS2 FETs whose performance is enhanced by ionic liquid gating, and these are combined into a CMOS inverter with a gain of 1.2 and static power near 10 nW, plus pass-transistor AND, OR, and NOT gates.","pith_inferences":["If the growth route is as general as the proof of concept suggests, other p-type 1D materials and n-type 2D channels could be substituted into the same two-step recipe, extending it from Te/MoS2 to a family of mixed-dimensional circuits.","The paper leaves junction capacitance and high-frequency rectifier operation as future work; measuring those quantities would directly test whether the 6.85 nm depletion region behaves as atomically thin in dynamic operation.","Since Te nanowires have an antenna effect and MoS2 photoluminescence is quenched at the junction, the same platform is a plausible basis for integrated photodetection and optoelectronic logic beyond the electrical gates demonstrated.","A direct measurement of the interface dipole, for example via surface potential under illumination or a band-bending-sensitive photoemission shift, would settle the relation between the KPFM-based electron transfer from MoS2 to Te and the paper's Bader charge analysis."],"forward_implications":["The same wafer can provide p-type Te FETs, n-type MoS2 FETs, and Te/MoS2 diodes, so mixed-signal circuits no longer require transfer, stacking, or separate substrates.","A depletion width near 6.85 nm with an internal field around $3\\times10^7$ V/m means the junction is atomically abrupt by the paper's estimate.","Ionic liquid gating raises both FET types to comparable on-off ratios around $\\sim5\\times10^4$, which the paper identifies as the key to building a working CMOS inverter on this platform.","AND, OR, and NOT gates built from the same IL-gated FETs follow their truth tables, so basic digital logic can be made entirely from 1D/2D heterostructures.","The observed density of 15-20 heterojunctions and 50-60 MoS2 flakes per 130 µm by 130 µm area suggests the growth route can be scaled to centimeter-scale templates."],"supporting_citations":[{"why":"Supplies the atmospheric-pressure CVD recipe that grows MoS2 flakes on the SiO2/Si substrate.","marker":"[38]"},{"why":"Supplies the PVD route that grows Te nanowires on the same substrate after the MoS2 step.","marker":"[39]"},{"why":"Provides the SiO2 work function (5.05 eV) used to convert KPFM contact-potential differences into the sample work functions.","marker":"[44]"},{"why":"Supports the work function value assigned to MoS2 in the band-alignment analysis.","marker":"[45]"},{"why":"Supports the work function value assigned to tellurium in the band-alignment analysis.","marker":"[46]"},{"why":"Provides the donor/acceptor concentration and depletion-width formulas used to obtain the 6.85 nm total depletion width.","marker":"[36]"},{"why":"Gives the comparison rectification ratio for similar 1D/2D diodes against which the measured value of about 180 is placed.","marker":"[37]"},{"why":"Supports the claim that Te forms nearly barrier-free contacts, which the paper uses to explain the IL-induced current change.","marker":"[62]"},{"why":"Supplies the back-gate/ionic-liquid capacitance comparison used to extract the electric double layer capacitance and the IL-gated mobility.","marker":"[63]"},{"why":"Provides the pass-transistor circuit design used to implement the AND, OR, and NOT gates.","marker":"[64]"}],"fun_headline_variants":["Two-step growth co-integrates p-n diodes and CMOS logic on one wafer","One wafer, two functions: diodes and logic gates from Te and MoS2","Mixed-dimensional vdW platform for analog and digital circuits","Sequential vapor deposition yields diode and CMOS on same chip","1D/2D vdW structures enable unified analog-digital electronics"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the Kelvin probe surface-potential measurement correctly orders the work functions, with Te at 4.96 eV and MoS2 at 5.15 eV; if that ordering is wrong, the built-in potential, band offsets, and 6.85 nm depletion width are not established.","fun_headline_variants_meta":{"raw":{"variants":["Two-step growth co-integrates p-n diodes and CMOS logic on one wafer","One wafer, two functions: diodes and logic gates from Te and MoS2","Mixed-dimensional vdW platform for analog and digital circuits","Sequential vapor deposition yields diode and CMOS on same chip","1D/2D vdW structures enable unified analog-digital electronics"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001414,"raw_usage":{"total_tokens":5730,"prompt_tokens":984,"completion_tokens":4746,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":600,"completion_tokens_details":{"reasoning_tokens":4650}},"tokens_in":600,"tokens_out":4746,"duration_ms":31105,"temperature":1.0,"reasoning_tokens":4650,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T17:06:05.356466+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the contact-potential difference of the same Te NW/MoS2 junction against a reference metal with a calibrated Kelvin probe or ultraviolet photoemission spectroscopy; if the extracted work functions do not satisfy $W_{\\mathrm{Te}} < W_{\\mathrm{MoS_2}}$, then the type-I alignment, the 0.19 V built-in potential, and the 6.85 nm depletion width do not follow.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the atmospheric-pressure CVD recipe that grows MoS2 flakes on the SiO2/Si substrate."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the PVD route that grows Te nanowires on the same substrate after the MoS2 step."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the SiO2 work function (5.05 eV) used to convert KPFM contact-potential differences into the sample work functions."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supports the work function value assigned to MoS2 in the band-alignment analysis."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supports the work function value assigned to tellurium in the band-alignment analysis."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the donor/acceptor concentration and depletion-width formulas used to obtain the 6.85 nm total depletion width."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Gives the comparison rectification ratio for similar 1D/2D diodes against which the measured value of about 180 is placed."},{"cited_title":"Dasika, D","cited_arxiv_id":null,"evidence_quote":"Supports the claim that Te forms nearly barrier-free contacts, which the paper uses to explain the IL-induced current change."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the back-gate/ionic-liquid capacitance comparison used to extract the electric double layer capacitance and the IL-gated mobility."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the pass-transistor circuit design used to implement the AND, OR, and NOT gates."}],"review_version":1}