{"id":"51aee0e4-0bf0-48f2-a0cc-34a68c211e9f","arxiv_id":"2412.10757","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A vertical MoS2/In2Se3 device demonstrates two coupled synaptic channels, homosynaptic and heterosynaptic plasticity, Boolean logic, and simulated ANN/SNN learning up to about 90 percent MNIST accuracy.","lead":"A stacked two-layer transistor made of MoS2 and In2Se3 behaves as two coupled synapses that can strengthen or weaken together, mimic a sea slug's reflex learning, and reconfigure into logic gates. The device is compact, but the headline neural-network accuracies are from simulations, not from a fabricated chip.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The reported high-accuracy on-chip learning is an idealized crossbar simulation, not a measurement; the headline claim depends on the untested assumption that many VSFETs behave identically to the single measured device.","rationale":"The reader correctly identifies the extrapolation from a single device to an idealized crossbar as the weakest assumption. My independent reading concurs: the device-level data (hysteresis, C-MoS2 control, PFM, P/D, STDP, simultaneous heterosynaptic measurements, and logic gates) are internally consistent and support the claim that the VSFET is a functioning dual-synapse/logic building block. However, the 'high accuracy on-chip learning' numbers in the abstract and title are simulation outputs based on a single-device model with no array non-idealities. This is a real overclaim that should be explicitly qualified. The concern is load-bearing because these numbers are the primary quantitative evidence for the 'in-memory neuromorphic computing' capability. A computational sensitivity test can determine whether the simulated accuracies survive realistic non-idealities. I agree with the reader's CONDITIONAL verdict; no change is needed beyond enforcing the stated conditions.","tokens_in":18487,"tokens_out":7571,"duration_ms":68348,"concrete_test":"Re-run the FCNN and SNN simulations using the same measured P/D curves with the following non-idealities added: Gaussian device-to-device variation (σ = 10% in Gmax/Gmin and σ = 20% in αp, αd), 2% stuck-at-faults, and series line resistance of 10 Ω per cell. If MNIST accuracy drops below 80% or Iris accuracy below 85%, the 'high accuracy' claim is not robust and should be downgraded to 'simulated for an idealized array'.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The strongest quantitative claims (90.06% MNIST accuracy, 96.2% Iris accuracy) are not obtained from a fabricated array. Section 'Homosynaptic Plasticity and Neuromorphic In-Memory Computing' states that 'the P/D parameters extracted from Figure 4b were used to model the hardware implementation of a NN circuit utilizing MoS2/In2Se3 vdW VSFET arrays in crossbar architecture.' No array was fabricated; no multi-device statistics are reported. Therefore, the abstract's assertion of 'high accuracy supervised and unsupervised on-chip learning' is an extrapolation, not a demonstration. To support the central claim, one would need at least a small crossbar (or a statistical ensemble of devices) showing that the P/D behavior is reproducible and that the simulated accuracy holds with device-to-device variation, interconnect resistance, and write noise. As it stands, the learning-accuracy numbers are conditional on the single-device data being representative of an entire array.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports a vertically stacked MoS2/In2Se3 field-effect transistor (VSFET) in which a top MoS2 channel and a bottom ferroelectric-semiconductor In2Se3 channel share a common gate and are electrostatically coupled. The authors demonstrate hysteretic transfer and output characteristics, attribute the hysteresis to coupled out-of-plane and in-plane ferroelectric polarization of In2Se3, and use the gate-controlled MoS2 channel to emulate homosynaptic plasticity (potentiation/depression and STDP). From measured P/D and STDP curves they simulate supervised MNIST and unsupervised iris classification accuracies of 90.06% and 96.2%, respectively. Simultaneous measurements of both channels are used to demonstrate heterosynaptic cooperation and competition, which are mapped onto a conceptual Aplysia gill-withdrawal model. Finally, the device is reconfigured to implement NOT and NOR logic gates.","tokens_in":18635,"tokens_out":7109,"duration_ms":62142,"significance":"If the claims are properly scoped, the VSFET is a useful building block for in-memory neuromorphic computing: it is area-efficient, combines two coupled synapses in a vertical stack, shows both homosynaptic and heterosynaptic plasticity, and can be reconfigured as logic gates. The strength of the work lies in the direct device-level measurements, the inclusion of C-MoS2 and C-In2Se3 control devices that support the ferroelectric-coupling attribution, the demonstration of simultaneous access to two coupled channels, and the use of measured P/D and STDP data as inputs to network simulations rather than purely abstract model parameters. The main weakness is that the headline 'on-chip learning' accuracies are not hardware results but single-device-to-simulation extrapolations, so the significance depends on whether array-level variability is small or the claims are appropriately qualified.","major_comments":[{"comment":"The abstract and main text claim 'high accuracy supervised and unsupervised on-chip learning' (90.06% MNIST, 96.2% iris), but these numbers are not obtained from a fabricated crossbar array; they are simulations that use the measured P/D and STDP curves from a single device. The manuscript itself states that 'the P/D parameters extracted from Figure 4b were used to model the hardware implementation of a NN circuit utilizing MoS2/In2Se3 vdW VSFET arrays in crossbar architecture,' and no array-level measurements or multi-device statistics are reported. The learning-accuracy claims therefore rest on the untested assumption that the single measured device is representative of an entire array with no device-to-device variation, interconnect resistance, or write noise. To support the central claim, the authors should either present array or statistical-ensemble measurements, or explicitly re-label these results as simulations and qualify the 'on-chip' language in the abstract.","section":"Homosynaptic Plasticity and Neuromorphic In-Memory Computing, Figure 4"},{"comment":"The relationship between the reported test accuracies is inconsistent and unexplained. Figure 4d reports 90.06% for 'on-chip learning' using the incremental-amplitude pulse scheme, while Table 2 lists 97.21% for the same scheme under 'on-chip inference.' If the Table 2 numbers refer to inference after offline training with ideal weights mapped to the device, that should be stated; if they refer to on-chip training, the discrepancy with Figure 4d is substantial and needs a reason. Without clarification, the central accuracy numbers cannot be interpreted.","section":"Homosynaptic Plasticity and Neuromorphic In-Memory Computing, Table 2 and Figure 4d"},{"comment":"The 96.2% unsupervised SNN accuracy on Fisher's iris is presented without the network architecture, neuron model, input encoding, or spike-timing simulation details; the reader is only referred to prior work [44]. Given that the measured STDP time constants are approximately 113 ms and 337 ms, the SNN simulation must also specify the mapping between physical time and simulation time. Without these details, the unsupervised learning result is not reproducible.","section":"Homosynaptic Plasticity and Neuromorphic In-Memory Computing, Figure 4f"}],"minor_comments":[{"comment":"The abstract describes the device as showing 'low nonlinearity' but the reported potentiation nonlinearity factor is alpha_p = 1.74; please state the numerical values or clarify the comparison baseline.","section":"Abstract"},{"comment":"The caption refers to 'on-chip learning accuracy numbers' but these numbers come from simulations. Please use 'simulated' or 'modeled' in the caption and throughout the text.","section":"Figure 4d caption"},{"comment":"The mapping from the fitted parameters A_P and A_D to the nonlinearity factors alpha_p and alpha_d is not shown explicitly; please provide the full formula or a reference to the exact NeuroSim documentation page.","section":"Supporting Information 7"},{"comment":"The equation E_perspike = I_PSC * V_D * t_spike uses the drain-side voltage, but the presynaptic spike is applied at the gate; please justify why gate leakage current is negligible and clarify why the drain-side energy is the relevant metric.","section":"Energy per spike, Homosynaptic Plasticity section"},{"comment":"The text says 'the HT-MoS2 and HB-MoS2 synapses' but the bottom channel is In2Se3, not MoS2; this should read 'HT-MoS2 and HB-In2Se3.'","section":"Biomimetic Heterosynaptic Interactions in Sea Mollusk"},{"comment":"In the comparison table, 'Fisher's Irish' should be 'Fisher's Iris.'","section":"Table 1, Conclusion"},{"comment":"References [45-47] are URLs of Wikimedia Commons images; these are not standard citations for a scientific journal and should be replaced with proper data or literature citations.","section":"References [45-47]"}],"recommendation":"major_revision","confidential_remarks":"The paper relies heavily on the authors' own prior simulation frameworks [39,40,44], which is acceptable but means the network-level results depend on unvalidated assumptions about array behaviour. The 'on-chip learning' phrasing in the abstract and conclusion is likely to attract scrutiny from reviewers and should be softened unless array measurements are added. The device physics and the simultaneous dual-channel measurements are the strongest contributions."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The vertically stacked MoS2/In2Se3 VSFET is a genuinely new device architecture. Putting a ferroelectric semiconductor under a non-ferroelectric channel and reading both channels simultaneously gives you two coupled synapses in a compact footprint, and the C-MoS2 control convincingly attributes the hysteresis to the In2Se3. The device-level data—hysteresis scaling with sweep range, P/D curves, STDP, heterosynaptic cooperation and competition, and the NOT/NOR logic—are all shown and look internally consistent. The power numbers are also reported. That is a solid experimental contribution.\n\nThe soft spot is the \"on-chip learning\" claim. The 90.06% MNIST and 96.2% iris accuracies are model outputs, not measurements. The P/D and STDP curves from a single device are fed into a simulated crossbar that assumes ideal wiring and no device-to-device variation. That is ordinary device-to-system modeling, not circular reasoning, but it means the abstract's \"high accuracy supervised and unsupervised on-chip learning\" is an extrapolation. The stress-test note lands. The paper would be much stronger if it fabricated a small array or at least simulated with measured variability and interconnect parasitics. As it stands, the learning sections are a simulation study anchored to one device.\n\nOther soft spots are minor. Most electrical measurements lack error bars or device-to-device statistics, though the MW/SR repeats on two extra devices are a start. The Aplysia mimicry is qualitative—a nice narrative, not a quantitative model. The logic gates are simple NOT/NOR demonstrations, fine for proof-of-concept. The nonlinearity asymmetry (αp−αd = 1.81) is not great for analog weight updates, but they use 1-bit updates, so it is consistent.\n\nWho gets value from this? People working on 2D ferroelectric devices, neuromorphic hardware, and in-memory computing. The architecture is worth a serious look. I would send it to peer review with a request for major revision: rephrase the abstract to separate measured device behavior from simulated system accuracy, add statistics where possible, and include a variability analysis for the crossbar claims. The device data are substantive enough to warrant referee time.","headline":"The device work is real and the vertical dual-memtransistor architecture is new, but the headline learning accuracies come from idealized crossbar simulations, not from a fabricated array.","tokens_in":19262,"tokens_out":1728,"would_cite":true,"duration_ms":16528,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A single vertically stacked MoS2/In2Se3 transistor can act as two coupled synapses and a Boolean logic gate, the paper argues.","keywords":["2D materials","van der Waals heterostructure","ferroelectric semiconductor","MoS2/In2Se3 heterostructure","memtransistor","heterosynaptic plasticity","in-memory neuromorphic computing","reconfigurable Boolean logic"],"falsifier":"Fabricate a small crossbar array of MoS2/In2Se3 VSFETs, measure the conductance update of every cell across repeated potentiation/depression cycles, and run the same MNIST and iris simulations using the measured array-level nonlinearity and variation; if the 90.06% and 96.2% accuracies collapse or fail to reproduce, the single-device claims stand but the array-level neuromorphic claim falls.","tokens_in":18254,"feed_emoji":"🧠","tokens_out":8012,"duration_ms":66949,"temperature":0.7,"pith_summary":"This paper claims that a single vertically stacked transistor, the VSFET, built from a MoS2 channel on top of a ferroelectric-semiconductor In2Se3 channel on hBN, can serve as two coupled synapse devices accessed by one gate. The authors report that gate-controlled ferroelectric polarization of In2Se3 gives the MoS2 channel memtransistor behavior suitable for homosynaptic plasticity, with measured potentiation and depression nonlinearities of $\\alpha_p = 1.74$ and $\\alpha_d = -0.07$, and that this behavior yields 90.06% test accuracy in a simulated MNIST classifier after five epochs and 96.2% accuracy in a spiking network on Fisher's iris after two epochs. They further report that simultaneously measuring both channels realizes heterosynaptic cooperation and competition, which they use to mimic the gill-withdrawal reflex sensitization and habituation of Aplysia, and that the same device can be reconfigured as NOT and NOR Boolean gates. If correct, a single area-efficient device could serve as memory, two coupled synapses, and logic, a building block for in-memory neuromorphic computing.","feed_headline":"One stacked transistor becomes two synapses and a logic gate","feed_subtitle":"MoS2 on ferroelectric In2Se3 runs 90% MNIST and 96% iris learning, then reconfigures to Boolean logic.","key_machinery":"The load-bearing object is the vertically stratified field-effect transistor (VSFET): a bottom Au gate, an hBN dielectric, a thick n-type In2Se3 ferroelectric semiconductor channel, and a thin n-type MoS2 channel stacked on top, with source/drain contacts on both layers so each layer can be read as an independent transistor while sharing one gate. The out-of-plane ferroelectric polarization of In2Se3 is what stores memory: sweeping the gate beyond the coercive field flips the polarization, and the bound charge at the In2Se3/MoS2 interface modulates the MoS2 channel conductance, producing clockwise hysteresis whose memory window grows with sweep range. The in-plane polarization of the same In2Se3 layer modulates the MoS2 output conductance through Schottky-barrier changes at the contacts, producing pinched resistive hysteresis loops at zero gate bias. Because both channels share the gate, one gate pulse updates two coupled conductances at once; that shared-gate coupling is the mechanism behind the heterosynaptic cooperation and competition, and the same stack is reconfigured as a NOT or NOR gate by choosing which terminals serve as inputs and reading the net source current as the output.","core_discovery":"The central claim is that stacking a non-ferroelectric 2D semiconductor (MoS2) on a ferroelectric 2D semiconductor (In2Se3) creates two electrostatically coupled memtransistors within one vertical footprint, and that this coupling can be harnessed for both synaptic and logic functions. The out-of-plane ferroelectric polarization of In2Se3 modulates the MoS2 channel conductance, producing the gate-controlled hysteresis that underlies homosynaptic plasticity, while the in-plane polarization of the same In2Se3 layer produces pinched resistive output hysteresis at zero gate bias. Because both channel layers share a single gate, the two synapses can be measured simultaneously and show cooperative or competitive plasticity depending on the drain biases, and the same device can be reconfigured as a NOT or NOR gate by choosing which terminals are inputs.","pith_inferences":["Beyond the paper, if the single-device behavior survives in an array, the vertical stacking could push synapse density beyond planar designs because two memtransistors occupy one footprint; a fabricated crossbar would be the natural test.","The shared-gate coupling means one input pulse updates two weights simultaneously, which could enable training schemes where correlated synapses are updated together rather than independently.","The zero-gate-bias resistive switching from in-plane polarization suggests the VSFET could also be read as a two-terminal memory cell when the gate is idle, expanding its role beyond synaptic emulation.","Because the measured learning accuracies are simulation-based, a near-term testable extension is to build a small VSFET crossbar and measure classification accuracy under real device-to-device variation."],"forward_implications":["A single VSFET cell could replace two separate synapse devices in a crossbar array, roughly halving the area per synapse while keeping both conductances coupled.","The measured potentiation and depression nonlinearity, with $\\alpha_p - \\alpha_d = 1.81$, is low enough that a five-epoch, one-bit-update multilayer perceptron reaches 90.06% on MNIST, so the device offers a route to simple peripheral circuits.","The simultaneously read two channels support cooperative and competitive plasticity in one device, which could help balance and refine synaptic weights during learning.","The same device can switch between synaptic memory and NOT/NOR logic, enabling a logic-in-memory architecture without extra area."],"supporting_citations":[{"why":"Establishes the intrinsic out-of-plane ferroelectricity of In2Se3 caused by its asymmetric five-layer structure.","marker":"[19]"},{"why":"Establishes the intercorrelated in-plane and out-of-plane ferroelectricity in In2Se3 that the VSFET exploits.","marker":"[20]"},{"why":"Provides the ferroelectric-channel transistor behavior used to explain the memory-window growth in the MoS2 transfer curves.","marker":"[22]"},{"why":"Provides the ferroelectric switching and pulse-response behavior used for the MoS2 synapse's postsynaptic current and paired-pulse facilitation.","marker":"[31]"},{"why":"Supplies the in-plane ferroelectric resistance-switching behavior that explains the pinched output hysteresis and serves as a comparison device.","marker":"[33]"},{"why":"Supplies the ionic-coupling mechanism in MoS2 devices that the paper adapts for heterosynaptic cooperation.","marker":"[52]"},{"why":"Provides the multi-terminal memtransistor demonstration of competition and cooperation that this work compares against.","marker":"[63]"},{"why":"Supplies the back-propagation crossbar training method used to compute the MNIST on-chip learning accuracy.","marker":"[39]"},{"why":"Supplies the spiking-neural-network STDP learning rule used for the iris dataset accuracy.","marker":"[44]"},{"why":"Provides the Aplysia gill-withdrawal reflex learning model that the biomimetic sensitization and habituation demonstration maps onto.","marker":"[55]"}],"fun_headline_variants":["Two synapses and a logic gate from one stacked transistor","Stacked 2D transistors team up as synapses and logic","A single stacked FET does learning and logic","One vertical stack: two memtransistors, one logic gate","Ferroelectric stack runs neural nets and Boolean gates"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The simulated neural-network accuracies assume that a crossbar array of VSFETs will behave exactly like the single measured device, with no device-to-device variation and ideal interconnects, and no array was fabricated to test this.","fun_headline_variants_meta":{"raw":{"variants":["Two synapses and a logic gate from one stacked transistor","Stacked 2D transistors team up as synapses and logic","A single stacked FET does learning and logic","One vertical stack: two memtransistors, one logic gate","Ferroelectric stack runs neural nets and Boolean gates"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001001,"raw_usage":{"total_tokens":4245,"prompt_tokens":966,"completion_tokens":3279,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":582,"completion_tokens_details":{"reasoning_tokens":3201}},"tokens_in":582,"tokens_out":3279,"duration_ms":21352,"temperature":1.0,"reasoning_tokens":3201,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T15:37:54.202296+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Fabricate a small crossbar array of MoS2/In2Se3 VSFETs, measure the conductance update of every cell across repeated potentiation/depression cycles, and run the same MNIST and iris simulations using the measured array-level nonlinearity and variation; if the 90.06% and 96.2% accuracies collapse or fail to reproduce, the single-device claims stand but the array-level neuromorphic claim falls.","supporting_citations":[{"cited_title":"A.; Martin, L","cited_arxiv_id":null,"evidence_quote":"Establishes the intrinsic out-of-plane ferroelectricity of In2Se3 caused by its asymmetric five-layer structure."},{"cited_title":"Nano letters 2018, 18, 1253--1258","cited_arxiv_id":null,"evidence_quote":"Establishes the intercorrelated in-plane and out-of-plane ferroelectricity in In2Se3 that the VSFET exploits."},{"cited_title":"W.; Zhou, P","cited_arxiv_id":null,"evidence_quote":"Provides the ferroelectric-channel transistor behavior used to explain the memory-window growth in the MoS2 transfer curves."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the ferroelectric switching and pulse-response behavior used for the MoS2 synapse's postsynaptic current and paired-pulse facilitation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the in-plane ferroelectric resistance-switching behavior that explains the pinched output hysteresis and serves as a comparison device."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the ionic-coupling mechanism in MoS2 devices that the paper adapts for heterosynaptic cooperation."},{"cited_title":"-lZibkga j(| WAa[ AKC =vȖ^c᭏ ޺o_y7<]|cƌ+zz<j1","cited_arxiv_id":null,"evidence_quote":"Provides the multi-terminal memtransistor demonstration of competition and cooperation that this work compares against."},{"cited_title":"Synapse cell optimization and back-propagation algorithm implementation in a domain wall synapse based crossbar neural network for scalable on-chip learning","cited_arxiv_id":null,"evidence_quote":"Supplies the back-propagation crossbar training method used to compute the MNIST on-chip learning accuracy."},{"cited_title":"Spike time dependent plasticity (STDP) enabled learning in spiking neural networks using domain wall based synapses and neurons","cited_arxiv_id":null,"evidence_quote":"Supplies the spiking-neural-network STDP learning rule used for the iris dataset accuracy."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the Aplysia gill-withdrawal reflex learning model that the biomimetic sensitization and habituation demonstration maps onto."}],"review_version":1}