{"id":"8315b31a-346a-452e-9a9f-811d7b8ee8be","arxiv_id":"2412.18948","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"This is the first reported FPGA implementation of the L-Mul approximate multiplier for FP8, using about 22 lookup tables per multiplier and showing lower power in CNN/GCN inference.","lead":"This paper builds an energy-saving circuit on an FPGA that performs the approximate 8-bit floating-point multiplication used in neural networks, using lookup tables and carry chains instead of full multiplier blocks. It reports lower logic usage and power than earlier 8-bit approximate multipliers, and demonstrates the design in image and graph network inference.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Abstract's 'highest accuracy among 8-bit designs' is contradicted by Table VII, where L-Mul loses -0.96% (CNN) and -3.01% (GCN) vs INT8's -0.10% and -2.77%.","rationale":"I read the paper in good faith. The hardware design is novel and the LUT/carry-chain implementation is described in enough detail to be plausible. However, the strongest claim includes 'highest accuracy' among 8-bit designs, and this is directly contradicted by Table VII: L-Mul accuracy loss (-0.96% CNN, -3.01% GCN) is larger than INT8 (-0.10%, -2.77%). The reader's weakest assumption (subnormal/NaN/Inf handling) is a valid correctness gap, but the accuracy-claim contradiction is more immediately load-bearing because it is visible in the paper's own data. I would keep the conditional verdict and add a condition that the accuracy claim be corrected and, ideally, backed by measured end-to-end accuracy on the FPGA accelerators. The subnormal issue and WNS/power-language issues remain secondary conditions for acceptance.","tokens_in":10374,"tokens_out":13097,"duration_ms":114172,"concrete_test":"Run the deployed CNN and GCN accelerators on the ZCU104 at 250 MHz with identical quantization and report end-to-end inference accuracy for L-Mul (FP8 E4M3) and exact INT8. If L-Mul accuracy is lower than INT8, revise or remove the 'highest accuracy' claim; if it is higher, report the measured values to resolve the contradiction with Table VII.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that the design achieves 'the highest accuracy, energy efficiency, and the lowest latency' among 8-bit designs is undercut by the paper's own Table VII. That table reports L-Mul (E4M3) average inference accuracy losses of -0.96% on CNN and -3.01% on GCN, compared to exact INT8 losses of -0.10% and -2.77%. Since INT8 is an 8-bit design, L-Mul has the lowest accuracy of the 8-bit formats evaluated, not the highest. Section IV-D even states 'Although L-Mul exhibits the highest accuracy loss...' This is an internal inconsistency in the main claim. The energy-efficiency and latency comparisons are made against an INT8 baseline, so any claim of superior accuracy must be backed by either a narrower comparator set (e.g., only approximate multipliers) or by measured hardware accuracy for the actual accelerators. As written, the contribution summary overstates the accuracy result and the evidence does not support it.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript presents a primitive-level FPGA implementation of the L-Mul approximate FP8 multiplier for AMD UltraScale/UltraScale+ devices, mapping the computation onto LUTs, carry chains, and CLB-level placement constraints. It reports resource, frequency, and power results for six FP8 formats, compares the E4M3 deployment with prior 8-bit approximate multipliers and an exact IP core, and evaluates DNN inference accuracy loss and accelerator-level power. The stated contributions are that this is the first FPGA-based FP8 approximate multiplier, that it reduces resource consumption by about 10% relative to previous 8-bit designs, and that it achieves the highest accuracy, energy efficiency, and lowest latency among 8-bit designs.","tokens_in":10538,"tokens_out":9910,"duration_ms":83938,"significance":"The underlying hardware idea is relevant and plausible: reducing FP8 multiplication to add/shift operations via L-Mul and implementing it with LUT/carry primitives yields a compact DSP-free operator (about 22 LUTs), and the error evaluation against exact FP8 is an independent, non-circular benchmark. The paper gives enough architectural detail to be reproducible, and the synthesis-based resource counts across formats are a useful data point. However, the headline comparison claims are internally inconsistent with the reported tables, and several specification gaps (subnormal handling, consistency of Eq. (5), and normalization of power comparisons) must be resolved before the significance of the hardware claims can be assessed.","major_comments":[{"comment":"The claim that \"among 8-bit designs, ours achieves the highest accuracy\" is contradicted by Table VII: L-Mul E4M3 has average accuracy losses of -0.96% (CNN) and -3.01% (GCN), while exact INT8 has -0.10% and -2.77%, and exact FP8 E4M3 has -0.04% and -1.96%. Section IV-D itself states, \"Although L-Mul exhibits the highest accuracy loss...\" Please restrict the accuracy claim to approximate multipliers or remove it from the abstract and contribution list.","section":"Section I, second contribution bullet; Section IV-D, Table VII"},{"comment":"The latency and energy-efficiency claims are not supported by the reported data. The proposed design has a delay of 4.85 ns, whereas the AMD-Xilinx exact design reports 3.54 ns and Van Toan reports 4.65 ns. The power comparison is also not normalized: 1.34 mW at 617 MHz cannot be directly compared with 0.432 mW at 100 MHz, and the designs are on different device families (7-series versus UltraScale+). Please report energy per operation (e.g., power/frequency) under matched conditions, and include an exact FP8 multiplier baseline on the same device and at the same frequency to substantiate the FP8-specific efficiency claim.","section":"Section IV-C, Table VI"},{"comment":"The zero detection only checks whether fp8_x[6:0] == 7'b0 or fp8_y[6:0] == 7'b0. Subnormal FP8 numbers (exponent field 0000 with nonzero mantissa) and reserved exponent patterns (infinity/NaN) are therefore not detected; they are treated as normal numbers and produce incorrect outputs. Since the paper claims an FP8 implementation under IEEE-754 conventions, please either implement IEEE-754 special-case handling or explicitly state and justify a flush-to-zero/no-special-values assumption, and verify that the DNN workloads used in Section IV-D satisfy that assumption.","section":"Section III-B, zero-flag logic"},{"comment":"Eq. (5) does not follow from Eq. (4). The L-Mul correction term 2^{-l(m)} should appear as 2^{m-l(m)}/2^m in a numerator of the form (2^m + x + y + 2^{m-l(m)})/2^m, whereas the printed numerator \"1 + x + y + 2^{l(m)}\" gives a correction of 2^{l(m)-m}. The two coincide only when m = 3, so the bit-level representation as written is wrong for the other FP8 formats implemented in Table V. Please correct Eq. (5) and re-verify the synthesized arithmetic for m != 3.","section":"Section II-A, Eq. (5)"},{"comment":"The claimed \"average 10%\" resource reduction is not reproducible from Table VI. Averaging the listed LUT counts for the previous 8-bit designs gives approximately 48-52 LUTs, compared with 22 for the proposed design, which is a reduction of roughly 55%, not 10%. Please specify the exact comparator set and the calculation used for the 10% figure.","section":"Section I, first contribution bullet; Table VI"}],"minor_comments":[{"comment":"The bit-width descriptions of the Exponent-Adder and Mantissa-Adder appear swapped: for a format with e exponent bits and m mantissa bits, the exponent adder should be e/e+1 bits and the mantissa adder should be m/m+1 bits, not the reverse as written.","section":"Section III-B, adder description"},{"comment":"The piecewise definition of l(m) is contradictory at m = 4: it says both \"3 if m = 4\" and \"4 if m >= 4\". The last case should presumably be \"m > 4\".","section":"Section II-A, Eq. (4)"},{"comment":"The definition of NED as an average of ED_i/max(ED) is not the standard normalized error distance; please clarify the definition or rename the metric to avoid confusion.","section":"Section IV-A, Eq. (12)"},{"comment":"The accelerator comparison would be stronger if it reported measured inference accuracy and throughput for the deployed accelerators, not only resource and power, since Table VII reports software-evaluated accuracy rather than end-to-end hardware accuracy.","section":"Section IV-D, Table VIII"},{"comment":"Minor language issues include \"a real numbers is encoded\" and \"implicit\" in place of \"implicit\"; please copyedit the manuscript.","section":"Section II-A"}],"recommendation":"major_revision","confidential_remarks":"The paper is likely within scope for a reconfigurable-computing or approximate-computing venue, and the primitive-level implementation and synthesis results are a potentially useful contribution. However, the main contribution bullet overstates the accuracy and latency results relative to the paper's own tables, and the subnormal-handling and Eq. (5) issues are substantive specification gaps. These are fixable, so I recommend major revision rather than rejection."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short take: this is a real hardware implementation paper, and the resource story looks credible. The genuinely new things are the fine-grained mapping of L-Mul onto UltraScale/UltraScale+ LUTs and carry chains, the bias* constant tables, and the post-processing logic; no prior reference implements L-Mul in hardware or builds an FPGA-based FP8 approximate multiplier. The paper reports synthesis data consistently: about 22 LUTs, 25 FFs, 4 CARRY8s, no DSP, 617 MHz on ZCU104, and it integrates the multiplier into CNN and GCN accelerators with power savings. That is enough substance to justify a serious referee.\n\nThe weak point is the abstract. The claim of \"highest accuracy among 8-bit designs\" is contradicted by Table VII in the same paper: L-Mul loses -0.96% (CNN) and -3.01% (GCN), versus INT8's -0.10% and -2.77%. The body admits this in Section IV-D. The claim should be narrowed to resource, latency, and power, or carefully restricted to approximate FP8 designs. Since the full text already concedes the accuracy loss, this is fixable.\n\nOther soft spots: the comparisons against INT8 designs run on different devices, frequencies, and power measurement conditions. Reference [24] reports power at 100 MHz while other designs run nearer their maximum frequencies. The paper notes some of this, but without an exact FP8 multiplier baseline on the same device, the \"energy efficiency\" conclusions are weaker than the abstract suggests. The zero flag only catches the all-zero 7-bit payload; subnormal values and Inf/NaN patterns are flushed or miscomputed. That is not fatal for typical NN inference, but the paper should state the precondition explicitly.\n\nThe L-Mul approximation itself is prior work by Luo and Sun, and the paper does not claim otherwise. The error evaluation uses exact FP8 as an independent benchmark, and no free parameters are fitted. The citation pattern is appropriate.\n\nI would send this to peer review. The referee should insist on fixing the accuracy wording, adding an exact FP8 baseline on the same device, and stating subnormal and NaN handling. If those are addressed, this is a useful contribution for approximate computing and FPGA-based NN inference.","headline":"A credible first hardware mapping of L-Mul onto FPGA LUT/carry primitives with solid resource reporting; the headline accuracy claim overstates what Table VII actually shows.","tokens_in":11065,"tokens_out":1781,"would_cite":true,"duration_ms":17811,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper builds the first FPGA implementation of L-Mul, an approximate FP8 multiplier that replaces multiplication with additions and shifts, fitting in roughly 22 lookup tables with no DSP blocks.","keywords":["approximate computing","L-Mul","FP8","FPGA","lookup table","carry chain","neural network inference","energy-efficient hardware"],"falsifier":"A decisive check: simulate the paper's bit-level equations for all 65,536 E4M3 input pairs and compare with exact IEEE-754 FP8 multiplication. Any mismatch on inputs with exponent bits 0000 and nonzero mantissa, or exponent bits 1111, exposes the special-value handling gap; a same-target synthesis of the Verilog would independently confirm the roughly 22-LUT, no-DSP resource count.","tokens_in":10168,"feed_emoji":"⚡","tokens_out":11285,"duration_ms":95105,"temperature":0.7,"pith_summary":"This paper claims to present the first FPGA-based approximate multiplier for the FP8 floating-point format, implementing the L-Mul algorithm. L-Mul replaces the mantissa product in FP8 multiplication with a shift-and-add approximation, and the authors show that this arithmetic maps onto FPGA lookup tables and carry chains using about 22 LUTs and no DSP blocks. In E4M3 format, the standalone multiplier runs at 617 MHz, consumes 1.34 mW, and keeps inference accuracy loss to 0.96% on CNNs and 3.01% on GCNs while cutting accelerator power. The paper argues this makes L-Mul practical for energy-constrained neural-network inference on FPGAs.","feed_headline":"22 LUTs, zero DSPs: first FPGA FP8 approximate multiplier","feed_subtitle":"L-Mul turns FP8 multiplication into additions, fitting in 22 LUTs with no DSPs and under 1% CNN accuracy loss.","key_machinery":"The load-bearing object is the L-Mul identity, which replaces the mantissa product $m_x m_y$ in FP8 multiplication with the small power $2^{-\\ell(m)}$, turning $(1+m_x)(1+m_y)$ into the sum $1+m_x+m_y+2^{-\\ell(m)}$ while the exponents are added separately. The hardware realizes this with five LUT configurations and CARRY8 chains split into an exponent adder, a mantissa adder, and a post-processing unit; per-format constants fold the FP8 bias and mantissa-carry handling into a single $bias^*$ value, and CLB-level placement constraints keep LUT-to-carry-chain paths short.","core_discovery":"On its own terms, the paper establishes that L-Mul's approximate FP8 multiplication can be built entirely from standard FPGA logic primitives rather than DSP blocks. Five LUT configurations and CARRY8 chains form an exponent adder, a mantissa adder, and a post-processing unit that together compute the L-Mul result for a chosen FP8 exponent/mantissa split. For the widely used E4M3 format the result is a multiplier with about 22 LUTs, 25 flip-flops, four carry-chain units, a 4.85 ns critical path, and 1.34 mW of power. The paper further claims this is the first FPGA-based FP8 approximate multiplier, that it uses on average 10% fewer resources than previous 8-bit approximate FPGA multipliers, and that in CNN and GCN inference it removes all DSP blocks while keeping accuracy loss below 1% and around 3%, respectively.","pith_inferences":["Editorial inference: the reported accuracy numbers implicitly assume flush-to-zero-like behavior, because the hardware's zero flag only detects an all-zero payload; feeding FP8 subnormals, infinities, or NaNs would produce silently wrong products.","Editorial inference: the 10% resource saving is measured against INT8 approximate multipliers of the same bit width, so a future subnormal-aware or exactly-specified FP8 baseline could change the comparison.","Editorial inference: since the FPGA circuit computes the same L-Mul arithmetic already validated on GPUs for large language models, LLM accuracy should carry over, but the subnormal blind spot may matter more for low-precision transformer activations."],"forward_implications":["With the E4M3 format, the multiplier consumes 22 LUTs, 25 flip-flops, and four carry-chain units per product, with no DSP block and a 4.85 ns critical path at 617 MHz.","Across the six FP8 formats, resource use stays between 21 and 23 LUTs, so the same architecture covers E1M6, E2M5, E3M4, E4M3, E5M2, and E6M1 with near-identical cost.","In CNN inference, replacing exact INT8 multipliers with the FP8 L-Mul design removes 1,156 DSPs and cuts power from 9.46 W to 8.08 W at 250 MHz, with 0.96% accuracy loss.","In GCN inference, the design removes 512 DSPs and lowers power from 8.61 W to 8.23 W, with 3.01% accuracy loss.","Against prior 8-bit approximate FPGA multipliers, the design uses on average 10% fewer LUTs and sits on the area-latency Pareto frontier, with the second-lowest power-delay product."],"supporting_citations":[{"why":"Supplies the L-Mul algorithm that the paper implements in hardware.","marker":"[2]"},{"why":"Provides the LUT6-2 and carry-chain structure of the target FPGA that the primitive-level design exploits.","marker":"[10]"},{"why":"Defines the FP8 formats and their exponent/mantissa layouts that the design targets.","marker":"[11]"},{"why":"Supports the claim that FP8 achieves good neural-network inference accuracy, motivating the FP8 multiplier.","marker":"[12]"},{"why":"Serves as the closest prior FPGA 8-bit approximate multiplier comparison, including the FP8-to-INT8 DyRecMul design.","marker":"[21]"},{"why":"Provides an area-optimized low-latency FPGA approximate multiplier baseline for resource and delay comparison.","marker":"[23]"},{"why":"Supplies a fast FPGA INT8 approximate multiplier baseline whose power is measured at a lower frequency.","marker":"[24]"},{"why":"Provides the LW-GCN accelerator baseline into which the FP8 multiplier is integrated for GCN inference evaluation.","marker":"[25]"}],"fun_headline_variants":["First FPGA FP8 multiplier: 22 LUTs, zero DSPs, 1.34 mW","L-Mul on FPGA: FP8 multiply in 22 LUTs, no DSP blocks","FP8 approximate multiply: 22 LUTs replace DSPs, <1% CNN loss","Power-efficient FPGA FP8 multiplier: 22 LUTs, no DSPs","Approximate FP8 multiply on FPGA: 22 LUTs, 1.34 mW"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"For the reported accuracy numbers to hold, every weight and activation entering the multiplier must be a normal finite FP8 value or exactly zero, because the hardware does not detect subnormals, infinities, or NaNs and would multiply them as if they were ordinary numbers.","fun_headline_variants_meta":{"raw":{"variants":["First FPGA FP8 multiplier: 22 LUTs, zero DSPs, 1.34 mW","L-Mul on FPGA: FP8 multiply in 22 LUTs, no DSP blocks","FP8 approximate multiply: 22 LUTs replace DSPs, <1% CNN loss","Power-efficient FPGA FP8 multiplier: 22 LUTs, no DSPs","Approximate FP8 multiply on FPGA: 22 LUTs, 1.34 mW"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000347,"raw_usage":{"total_tokens":1890,"prompt_tokens":928,"completion_tokens":962,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":544,"completion_tokens_details":{"reasoning_tokens":840}},"tokens_in":544,"tokens_out":962,"duration_ms":7716,"temperature":1.0,"reasoning_tokens":840,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T04:18:25.338346+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"A decisive check: simulate the paper's bit-level equations for all 65,536 E4M3 input pairs and compare with exact IEEE-754 FP8 multiplication. Any mismatch on inputs with exponent bits 0000 and nonzero mantissa, or exponent bits 1111, exposes the special-value handling gap; a same-target synthesis of the Verilog would independently confirm the roughly 22-LUT, no-DSP resource count.","supporting_citations":[{"cited_title":"Ultrascale architecture configurable logic block user guide","cited_arxiv_id":null,"evidence_quote":"Provides the LUT6-2 and carry-chain structure of the target FPGA that the primitive-level design exploits."},{"cited_title":"Dyrecmul: Fast and low-cost approximate multiplier for fpgas using dynamic reconfigura- tion,","cited_arxiv_id":null,"evidence_quote":"Serves as the closest prior FPGA 8-bit approximate multiplier comparison, including the FP8-to-INT8 DyRecMul design."},{"cited_title":"Area-optimized low-latency approximate multipliers for fpga-based hardware accelerators,","cited_arxiv_id":null,"evidence_quote":"Provides an area-optimized low-latency FPGA approximate multiplier baseline for resource and delay comparison."},{"cited_title":"Fpga-based multi-level approximate mul- tipliers for high-performance error-resilient applications,","cited_arxiv_id":null,"evidence_quote":"Supplies a fast FPGA INT8 approximate multiplier baseline whose power is measured at a lower frequency."},{"cited_title":"Lw-gcn: A lightweight fpga-based graph convolutional network accelerator,","cited_arxiv_id":null,"evidence_quote":"Provides the LW-GCN accelerator baseline into which the FP8 multiplier is integrated for GCN inference evaluation."}],"review_version":1}