{"id":"0ec813b7-0ac6-4439-97de-13cf6add24d6","arxiv_id":"2501.00482","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A 12-bit delta-sigma ADC in a 0.18 µm SOI CMOS process qualified to 175 °C was measured to maintain 12 effective bits and a 140 dB Schreier FoM at 250 °C.","lead":"Researchers built a 12-bit delta-sigma analog-to-digital converter on a standard 180-nanometer silicon-on-insulator CMOS process and showed it keeps working at 250 °C, far above the 175 °C the process is qualified for. The design uses dummy transistors and boosted clocks to cancel leakage, producing a small, low-power converter for oil, gas, and aerospace sensing.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"250°C rating rests on snapshot measurements with no soak or time-resolved data; the reported 'up to 250°C' and 'reliable operation' require a steady-state check.","rationale":"The core claim is an empirical temperature rating, not a theoretical derivation. Measurements from five samples at discrete temperatures are credible evidence for instantaneous operation, and the paper's transparency about the collapse above 250°C and about PDK limitations counts in its favor. The load-bearing gap is that a temperature rating ('up to 250°C') and the reliability language in the abstract require sustained, equilibrium operation. The reported data are aggregates over unknown dwell times; no time axis is shown. If the measurements were taken before thermal equilibrium, the die was cooler than 250°C and the headline number is not that claimed. If they were taken at equilibrium but the chip drifts over minutes or hours, the phrase 'reliable operation' is not supported. This is not an internal inconsistency in the circuit description; it is a missing measurement that directly gates the central claim. A one-hour soak with continuous SINAD logging, plus a thermal cycle, would distinguish these cases and is inexpensive. Secondary issues: the abstract and conclusion say 44 mW while Table I says 0.044 mW (μW); if the true power were 44 mW, the Schreier FoM would be about 110 dB, not 140 dB, materially weakening the record-low-power claim. This should be fixed by checking the supply-current plot and correcting the manuscript, but it is less load-bearing than the soak question because the table and the reported bias current strongly suggest μW. The absence of raw data and of a control chip without mitigation circuits is relevant but also secondary. The reader's CONDITIONAL verdict is appropriate; no change is needed.","tokens_in":13386,"tokens_out":13111,"duration_ms":135337,"concrete_test":"Re-measure the five samples with a defined dwell protocol: ramp to 250°C, hold for at least 60 minutes while continuously acquiring the bitstream and computing SINAD in one-minute windows, then cycle to room temperature and re-measure at 250°C. Also attach a thermocouple to the package lid or use a temperature-sensor die to verify the die is within a few degrees Celsius of 250°C during the acquired windows. Pass criterion: after the first 10 minutes, SINAD remains within ±3 dB of the reported 74.5 dB mean for the remaining dwell and repeats after the thermal cycle.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section IV reports mean SNR/SINAD over temperature (Fig. 6(a)-(b)) but gives no dwell time at each setpoint, no time-resolved data at 250°C, and no thermal-cycling data. The simulation-based justification for the leakage-compensation circuits (Fig. 3(c)-(d)) is explicitly only 'strictly reliable up to the qualification temperature (175°C)' (Section II.B), so the 250°C result rests entirely on the measurements. The title's 'up to 250°C' and the abstract's 'reliable operation' claims therefore depend on an unverified steady-state assumption. A ceramic DIL48 package plus a metal socket and ceramic PCB have substantial thermal mass; if data were taken when the oven setpoint first reached 250°C, the die could still be below 250°C, making the reported ENOB a low-temperature artifact. Conversely, at true 250°C, junction leakage and electromigration can cause drift or failure over minutes to hours, and none of the five samples was observed beyond a single snapshot. The paper itself notes that at high temperature the measured bias current 'cannot be trusted' because pad-protection diodes leak (Section IV), which makes the output bitstream the only reliable indicator and underscores the need for time-resolved validation. Without a soak/cycling test, the headline 'operates up to 250°C' is a functional data point, not a temperature rating.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a second-order discrete-time delta-sigma ADC fabricated in XFAB XT018 0.18 µm SOI CMOS, with the stated goal of operating at temperatures up to 250 °C, well above the 175 °C qualification limit of the process. The authors describe design techniques for high-temperature operation, including dummy-transistor junction-leakage compensation, clock-boosting for pass-gate subthreshold leakage, and electromigration-aware metal sizing. Measurements on five samples report SNR above 93 dB, SINAD of 74.5 dB (ENOB of 12 bits), a Schreier FoM of 140 dB at 250 °C, a die area of 0.065 mm², and a power consumption that appears in the abstract and conclusions as 44 mW but in Table I as 0.044 mW. The paper claims a record-low area and power for a high-temperature data converter and positions the design for applications such as oil/gas extraction and aeronautics.","tokens_in":13584,"tokens_out":5521,"duration_ms":53677,"significance":"If the measured performance is reproducible, this is a valuable engineering contribution: a 12-bit ADC operating at 250 °C in a standard automotive-grade SOI process, with very low area and power, would be of clear practical interest for high-temperature sensing and instrumentation. The paper is commendable for reporting measurements on five samples, presenting mean and ±3σ curves, and including a comparison with prior high-temperature ADCs. The claimed FoM and area overhead are also noteworthy. However, the strength of the claims is limited by the power inconsistency, the absence of steady-state/lifetime validation at 250 °C, and the lack of a baseline chip without the mitigation circuits.","major_comments":[{"comment":"There is a factor-of-1000 inconsistency in the reported power consumption. The abstract and the Conclusions state 44 mW, while Table I lists 0.044 mW. The stated Schreier FoM of 140 dB is consistent only with 0.044 mW (44 µW) for the reported bandwidth of 0.146 kHz and SINAD of 74.5 dB. Because power is a headline result and enters the FoM calculation, all instances must be harmonized and the value verified; the authors should also specify exactly which supply domains are included (e.g., 1.8 V analog core only, or also 3.3 V I/O and reference).","section":"Abstract, Conclusions, Table I"},{"comment":"The claim that the ADC \"operates up to 250 °C\" and offers \"reliable operation\" is stronger than the evidence presented. The measurements in Fig. 6 appear to be snapshot temperature steps: no dwell time at each setpoint, no time-resolved data at 250 °C, and no thermal-cycling or soak data are reported. Since the process and PDK are qualified only to 175 °C, the 250 °C result rests entirely on these snapshots. The authors should either add steady-state/cycling validation or explicitly limit the claims to \"functional operation at 250 °C during the described measurements\" and remove \"reliable operation\" from the abstract and conclusions.","section":"Section IV, Fig. 6, Abstract"},{"comment":"The effectiveness of the leakage-compensation and clock-boosting techniques is demonstrated only by simulations that the paper itself says are \"strictly reliable only up to the qualification temperature (175 °C)\" (Section II.B). No measured comparison is provided with a baseline ADC fabricated without these mitigation circuits, so the experimental evidence that these techniques are what enables operation at 250 °C is indirect. The authors should state this limitation explicitly and, if possible, provide a measured comparison or per-block measurements.","section":"Section II.B, Fig. 3"},{"comment":"Reporting only mean and ±3σ curves for five samples, without raw data or per-sample tables, limits verification of the central measurement result. With n=5, the ±3σ spread is itself a statistical estimate, and the paper does not state the number of repeated measurements per temperature point or the measurement uncertainty. Numerical data points or a table of per-sample SNR, SINAD, INL, and supply current at each temperature should be provided.","section":"Section IV, Fig. 6"}],"minor_comments":[{"comment":"The units of the supply-current axis are not stated; please specify whether the current is per sample or averaged, and give the unit (e.g., µA).","section":"Fig. 6(d) caption"},{"comment":"The text uses \"integrative non-linearity\" and \"adsorbed\"; these should be \"integral non-linearity\" and \"drawn\" or \"consumed.\"","section":"Section IV"},{"comment":"There is a typo, \"Schereier\", which should be \"Schreier.\"","section":"Section IV"},{"comment":"The statement that INL is \"below 1 mV\" from -40 °C to 250 °C needs context: for a 1.8 V reference, 1 mV corresponds to about 2.3 LSB at 12 bits. Please explain how this coexists with a 12-bit ENOB (e.g., INL after calibration, different full-scale definition, or DC INL not directly limiting AC SINAD).","section":"Section IV, INL statement"},{"comment":"Reference [30] has a typo in the URL: \"hhttps://\" should be \"https://\".","section":"Reference list"},{"comment":"The Schreier FoM formula is given as SINAD + 10×log(BW/P); please explicitly state that P is in watts and BW in hertz, and note the unit convention used in Table I.","section":"Section II, FoM definition"}],"recommendation":"major_revision","confidential_remarks":"This is a solid and practically relevant engineering result, but the power inconsistency and the unsupported \"reliable operation\" claim are load-bearing and must be fixed before publication. The absence of a baseline chip and the lack of soak/cycling data are the main scientific gaps; a revised version that tempers the claims and, if possible, adds a small amount of time-resolved data at 250 °C would be suitable for the journal."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The core result here is real: a second-order delta-sigma ADC in XFAB XT018 that keeps 12-bit ENOB at 250°C across five samples, with mean and ±3σ curves. That is a useful, measured data point for the high-temperature electronics community. The design is not built on new device physics; the leakage compensation and clock boosting are known tricks, and the paper says so. The novelty is the combination in a standard automotive SOI process at an area (0.065 mm²) and power (see below) that beat prior high-temperature converters. The authors are also honest that PDK models are not trustworthy above 175°C and that performance collapses above 250°C.\n\nThe soft spots are mostly about what the paper claims versus what it shows. First, the power figure is inconsistent: the abstract and conclusions say 44 mW, but Table I lists 0.044 mW. The FoM of 140 dB only works with 44 µW, so the mW in the text is a typo, but it needs to be corrected before publication. Second, there is no control chip without the mitigation circuits, so the attribution of the 250°C operation to the dummy-transistor and clock-boosting techniques is plausible but not directly demonstrated. Third, and most important, the “reliable operation” language in the abstract and conclusions runs ahead of the evidence. The measurements are snapshots at each temperature point; there is no dwell time, no thermal cycling, no soak data. The paper itself notes that the measured bias current cannot be trusted at high temperature because of pad-diode leakage, which means the bitstream is the only reliable indicator. That makes the missing time-resolved or soak data a real gap. The stress-test worry about thermal mass and oven setpoint is a plausible scenario, but the bigger issue is simply that a “250°C rating” needs a steady-state check, and this paper does not provide one.\n\nThese are missing pieces, not contradictions. The central measurement claim seems solid. The paper deserves a serious referee, and a good review would request raw data, a leakage validation or control measurement, and at least one soak experiment at 250°C. For someone building high-temperature data converters, this is worth citing as a demonstration of what standard SOI can do with careful design.","headline":"A credible 12-bit delta-sigma ADC demo at 250°C in a 175°C-qualified 0.18µm SOI process, but the reliability claim needs soak data and the power unit typo needs fixing.","tokens_in":14243,"tokens_out":2474,"would_cite":true,"duration_ms":24129,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A 12-bit delta-sigma ADC delivers full accuracy at 250 °C.","keywords":["high-temperature electronics","delta-sigma ADC","SOI CMOS","leakage compensation","clock boosting","electromigration","harsh-environment sensing","Schreier figure of merit"],"falsifier":"Power five packaged samples at 250 °C in an oven with clocks and inputs running, then measure SNR, SINAD, INL, and supply current every few hours for 1000 hours and thermal-cycle between −40 °C and 250 °C; if ENOB drops below 12 bits, INL exceeds 1 mV, or an interconnect resistance shift or open appears during the soak, the claim of reliable operation up to 250 °C is falsified.","tokens_in":13117,"feed_emoji":"🌡️","tokens_out":11936,"duration_ms":100924,"temperature":0.7,"pith_summary":"This paper claims that a second-order discrete-time delta-sigma ADC fabricated in a 0.18 µm SOI CMOS process qualified only to 175 °C can deliver 12-bit accuracy at 250 °C. In measurements on five samples, SNR stays above 93 dB and SINAD is 74.5 dB at 250 °C, with an effective number of bits of 12. The converter draws 44 µW according to Table I and occupies 0.065 mm², with only 13.7% of the die area devoted to high-temperature hardening. If the claim holds, harsh-environment systems in oil and gas extraction, aeronautics, and industrial ovens could use inexpensive automotive-grade CMOS instead of specialized wide-bandgap or bulky high-temperature SOI parts, at the cost of a lower conversion bandwidth.","feed_headline":"12-bit ADC delivers full accuracy at 250 °C","feed_subtitle":"Built on a 175 °C-rated 0.18 µm SOI CMOS process, it keeps 93 dB SNR at 250 °C for oil, gas, and aeronautics sensing.","key_machinery":"The central object is a second-order, single-bit, cascade-of-integrators feedback delta-sigma modulator implemented as a fully differential switched-capacitor circuit with a StrongARM latch comparator and an on-chip digital low-pass filter. The argument is carried by three temperature-hardening mechanisms: dummy-transistor leakage compensation, which injects equal-and-opposite junction currents into source/drain-body junctions and uses a current mirror with ratio four to cancel leakage at the differential input pair; clock boosting, which shifts the pass-gate clock high level to $V_{DD}+V_{ref}$ and the low level to $-V_{ref}$, cutting subthreshold channel leakage by more than a factor of twenty at a 200 mV boost; and metal-line sizing that keeps current density a factor of ten below an electromigration threshold extrapolated to 300 °C. These mechanisms protect the switched-capacitor charge, which is what the delta-sigma conversion accuracy ultimately depends on.","core_discovery":"On the paper's own terms, the discovery is that a standard automotive SOI CMOS process can be pushed 75 °C above its qualification limit without losing data-converter performance, provided the design counters junction leakage, subthreshold leakage, and electromigration. Across five packaged samples characterized from −40 °C to 260 °C, SNR exceeds 93 dB up to 250 °C while SINAD degrades softly from about 85 dB at room temperature to 74.5 dB at 250 °C; the worst-case INL stays below 1 mV and supply current remains nearly flat. Above 250 °C the performance collapses, which the authors attribute to leakage through pad-protection diodes and unintended turn-on of nominally off blocks. Because the PDK is calibrated only to 175 °C, these measurements, not simulations, are what support the 12-bit ENOB at 250 °C.","pith_inferences":["The abstract states a power of 44 mW, while Table I reports 0.044 mW; the 140 dB Schreier FoM only closes if the power is 44 µW, so the milliwatt figure is almost certainly a typographical error that should be corrected before the power claim is relied upon.","Functional measurements at temperature steps demonstrate performance at 250 °C but not lifetime at 250 °C; 'reliable operation' is a projection from extrapolated electromigration rules until soak, thermal-cycling, or long-duration data are reported.","A natural next experiment is a 1000-hour powered soak at 250 °C with periodic SNR, SINAD, INL, and supply-current checks; if those hold, the same hardening recipe could plausibly be extended toward 300 °C, as the authors suggest, possibly with more temperature-resistant interconnect.","The leakage-compensation current mirror at the input pair injects nonideal mirrored currents that could become a nonlinearity source at resolutions beyond 12 bits, so calibration or chopping may be needed for higher-performance variants."],"forward_implications":["A 12-bit delta-sigma ADC can be embedded in a high-temperature sensor node built on a standard automotive CMOS process, removing the need for SiC or GaN conversion electronics in many oil-and-gas and aeronautics signal chains.","The hardening techniques transfer to other switched-capacitor and mixed-signal blocks, so op-amps, references, and SAR front-ends on the same process can adopt the same leakage compensation and clock boosting.","With 44 µW and 0.065 mm², the converter is small and efficient enough for battery- or energy-harvesting-powered loggers that sit inside ovens or wells.","Because the area cost of the high-temperature circuitry is only 13.7%, temperature hardening does not force a larger, more expensive die.","Raising the CMFB clock frequency above the signal band should remove the pair of distortion spurs seen in the spectra, giving headroom for further SINAD improvement."],"supporting_citations":[{"why":"Supplies the high-temperature design criteria and the extrapolated electromigration thresholds that the ADC's hardening is based on.","marker":"[9]"},{"why":"Process datasheet identifying XT018 as a 0.18 µm SOI CMOS process qualified to 175 °C, the baseline the paper pushes beyond.","marker":"[26]"},{"why":"Earlier 0.18 µm SOI delta-sigma ADC demonstrated to 175 °C; the comparison point the paper must beat at higher temperature.","marker":"[27]"},{"why":"Prior 250 °C SOI-CMOS delta-sigma converter; comparison baseline showing the area and power savings of this design.","marker":"[28]"},{"why":"Commercial high-temperature SAR ADC used as state-of-the-art comparison for Figure of Merit and maximum temperature.","marker":"[29]"},{"why":"SOI SAR ADC operating to 300 °C; comparison showing performance degradation at very high temperature and prior work's larger area and power.","marker":"[31]"},{"why":"Reference for second-order delta-sigma architecture principles and for the Schreier FoM definition used to evaluate the converter.","marker":"[32]"},{"why":"StrongARM latch topology adopted for the comparator, chosen for low static power and no hysteresis.","marker":"[36]"},{"why":"Source of the dummy-transistor leakage-compensation technique used on junctions and pass-gates.","marker":"[37]"},{"why":"Review of leakage mechanisms that motivates the subthreshold-leakage reduction via clock boosting.","marker":"[38]"}],"fun_headline_variants":["12-bit ADC keeps 93 dB SNR at 250 °C","SOI ADC delivers 12-bit at 250 °C despite 175 °C spec","250 °C-capable ADC: 93 dB SNR, 12-bit, in 0.18 µm SOI","High-temp ADC: 12-bit ENOB at 250 °C, 44 mW only","ADC outlasts 175 °C spec: 12-bit at 250 °C in SOI"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the converter's measured 250 °C performance persists over application-relevant lifetimes, which the paper supports only with short temperature-step measurements and extrapolated electromigration rules, not with soak or thermal-cycling data.","fun_headline_variants_meta":{"raw":{"variants":["12-bit ADC keeps 93 dB SNR at 250 °C","SOI ADC delivers 12-bit at 250 °C despite 175 °C spec","250 °C-capable ADC: 93 dB SNR, 12-bit, in 0.18 µm SOI","High-temp ADC: 12-bit ENOB at 250 °C, 44 mW only","ADC outlasts 175 °C spec: 12-bit at 250 °C in SOI"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000828,"raw_usage":{"total_tokens":3660,"prompt_tokens":1030,"completion_tokens":2630,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":646,"completion_tokens_details":{"reasoning_tokens":2506}},"tokens_in":646,"tokens_out":2630,"duration_ms":18724,"temperature":1.0,"reasoning_tokens":2506,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T22:50:07.655084+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Power five packaged samples at 250 °C in an oven with clocks and inputs running, then measure SNR, SINAD, INL, and supply current every few hours for 1000 hours and thermal-cycle between −40 °C and 250 °C; if ENOB drops below 12 bits, INL exceeds 1 mV, or an interconnect resistance shift or open appears during the soak, the claim of reliable operation up to 250 °C is falsified.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Process datasheet identifying XT018 as a 0.18 µm SOI CMOS process qualified to 175 °C, the baseline the paper pushes beyond."},{"cited_title":"Sigma- Delta ADC on SOI Technology for Working at High Temperatures,","cited_arxiv_id":null,"evidence_quote":"Earlier 0.18 µm SOI delta-sigma ADC demonstrated to 175 °C; the comparison point the paper must beat at higher temperature."},{"cited_title":"A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300°C,","cited_arxiv_id":null,"evidence_quote":"Prior 250 °C SOI-CMOS delta-sigma converter; comparison baseline showing the area and power savings of this design."},{"cited_title":"A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications,","cited_arxiv_id":null,"evidence_quote":"Commercial high-temperature SAR ADC used as state-of-the-art comparison for Figure of Merit and maximum temperature."},{"cited_title":"A 9-bit successive approximation adc in soi cmos operating up to 300°c,","cited_arxiv_id":null,"evidence_quote":"SOI SAR ADC operating to 300 °C; comparison showing performance degradation at very high temperature and prior work's larger area and power."},{"cited_title":"Schreier and G","cited_arxiv_id":null,"evidence_quote":"Reference for second-order delta-sigma architecture principles and for the Schreier FoM definition used to evaluate the converter."},{"cited_title":"The strongarm latch [a circuit for all seasons],","cited_arxiv_id":null,"evidence_quote":"StrongARM latch topology adopted for the comparator, chosen for low static power and no hysteresis."},{"cited_title":"On low-leakage cmos switches,","cited_arxiv_id":null,"evidence_quote":"Source of the dummy-transistor leakage-compensation technique used on junctions and pass-gates."},{"cited_title":"Leak- age current mechanisms and leakage reduction techniques in deep- submicrometer cmos circuits,","cited_arxiv_id":null,"evidence_quote":"Review of leakage mechanisms that motivates the subthreshold-leakage reduction via clock boosting."}],"review_version":1}