{"id":"bd1f72c0-7e1d-4f4f-b949-064bdaeb009d","arxiv_id":"2501.00921","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"SynAlign aligns post-synthesis netlists to source code lines using preserved names and structural graph matching, reporting average 75% accuracy without source locators.","lead":"This paper presents SynAlign, a tool that maps synthesized chip netlists back to the original HDL source lines without relying on source-locator metadata. It works by anchoring on preserved net names and ports and using graph alignment heuristics, reporting 50-93% accuracy across test designs.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Evaluation only tests dont_touch-preserved nets and renamed netlists, so the claim that SynAlign maps arbitrary post-optimized cells to source code is not supported.","rationale":"The most load-bearing claim is the unqualified one in the abstract: SynAlign maps post-optimized netlists back to source code so a designer can trace critical-path cells. The two evaluation layers do not support that claim at the advertised strength. NL2NL changes only net names; it leaves the graph structure untouched, so the 61% 'design net changes' figure is really '61% name changes,' which is not the hard part of synthesis. Manual evaluation marks every test variable as dontTouch/keep before synthesis, so the variable survives optimization with its identity intact; the subsequent renaming only removes exact-name matching, not the structural preservation. A real critical-path trace targets optimized combinational logic that has no dont_touch attribute, and the paper gives no accuracy data for that regime. The limitation is acknowledged in Section 4 but the abstract and introduction do not carry the caveat. I do not regard this as a sign of dishonesty: the work is a reasonable first step and the algorithm could generalize. But the evidence as presented is conditional, not a demonstration of the headline capability. The proposed test would determine whether the concern actually lands.","tokens_in":15819,"tokens_out":5646,"duration_ms":52085,"concrete_test":"Re-run the Manual Accuracy Evaluation on RocketTile (Yosys and DC) without dont_touch/keep on the annotated nets: annotate 50-100 randomly selected combinational cells on the reported critical path, obtain a golden mapping via a hierarchical synthesis trace or LEC-assisted manual inspection, and compute accuracy. If accuracy falls substantially below the 50-93% range, the central claim must be narrowed to preserved nets; if it remains high, the concern is resolved.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The central claim—that SynAlign lets designers trace critical-path cells in a post-optimized netlist back to RTL lines—is not actually measured by either evaluation. The abstract's 61% tolerance figure comes from the NL2NL evaluation (Section 3.1, Listing 4), which generates V_synth by appending '_changed' to a random subset of net names in V_ref. That is renaming noise, not synthesis-induced structural change: no flattening, retiming, resource sharing, or logic restructuring occurs, so the graph topology remains identical and the results only measure robustness to name loss. The Manual Accuracy Evaluation (Section 3.2) is stronger but still constrained: for each test net the authors 'preserve only the variable to be aligned' by marking it dontTouch/keep (and punching in DC), and then manually rename the annotated net so it cannot be anchor-matched. Thus the reported 50-93% accuracy is specifically for nets that the synthesis flow was forced to preserve. Real critical-path cells—optimized combinational logic, muxes, adders, clock gates—are not dont_touch nets; Section 4 itself concedes that the method 'relies on the availability of Anchor links.' Without an experiment on non-preserved, optimization-heavy nets, the headline claim that a designer can annotate an arbitrary netlist cell and get its source LoC is unsupported.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents SynAlign, a tool that aims to automatically map annotated post-synthesis netlists back to the original HDL source code without relying on source locators. The method builds a reference graph (Gre_f) from HDL with line-of-code information and a synthesized graph (Gsynth) from the netlist, then aligns them using anchor points (preserved names and top-level I/O), full+half matching, partial matching, and surrounding matching. The evaluation uses two approaches: an automated netlist-to-netlist (NL2NL) test where a fraction of net names are randomly renamed, and a manual accuracy evaluation where selected variables are preserved with dontTouch/keep directives before synthesis. The paper reports 50-93% manual accuracy across designs and claims tolerance to up to 61% design net changes.","tokens_in":16059,"tokens_out":3789,"duration_ms":34956,"significance":"If the claimed results hold, SynAlign would give chip designers a practical way to trace critical-path cells to RTL lines across multiple synthesis tools, which is a real pain point in iterative design. The manuscript provides a clearly specified algorithm at pseudocode level and a reproducible NL2NL evaluation methodology, which are strengths. However, the evaluation does not currently exercise the central use case: aligning arbitrary post-optimized cells that were not explicitly preserved through synthesis. The reported accuracy figures apply to specially protected nets, and the noise-tolerance claim is based on renaming, not structural transformations. The core idea is promising and the algorithmic description is a useful starting point, but the evidence presented is not yet sufficient to support the paper's headline claims.","major_comments":[{"comment":"The claim that SynAlign 'can tolerate up to 61% design net changes without impacting alignment accuracy' is not supported by the NL2NL evaluation. Listing 4 shows that Vsynth is generated by appending '_changed' to a randomly selected subset of net names in Vref; no synthesis transformations such as flattening, retiming, resource sharing, or logic restructuring are applied. The graph topology therefore remains identical, and the experiment measures robustness to name loss, not structural change. The abstract should clearly state that this is name-noise tolerance, or the experiment must be redesigned to include actual synthesis-induced modifications.","section":"Abstract; Section 3.1, Listing 4, Figure 5"},{"comment":"The Manual Accuracy Evaluation only tests nets that were explicitly preserved through synthesis. Step 1 marks the left-hand side of selected assignment lines as 'dontTouch', Step 3 requires 'keep' or 'set_dont_touch' plus punching through the design in DC, and then the annotated net name is manually changed. The resulting 50-93% accuracy is therefore an accuracy for deliberately preserved nets, not for arbitrary post-optimized netlist cells. Designers tracing critical-path cells would typically annotate ordinary combinational gates or muxes that are not protected. Section 4 concedes that 'This work relies on the availability of Anchor links,' but the experiments never measure behavior when anchors are scarce or when the target net is not preserved. An evaluation on non-preserved, optimization-heavy nets, or a clearly scoped claim that the method only applies to preserved nets, is needed.","section":"Section 3.2, steps 1-3; Section 4"},{"comment":"The calc_wt() weighting function in Listing 3 is introduced as being 'based on experiments with benchmarks PipelinedCPU and SingleCycleCPU', and those same two benchmarks appear in the evaluation results in Table 2. Since Figure 8 shows that Partial Matching contributes a substantial fraction of alignments (about 50% for RocketTile_DC), tuning this weighting on the same designs used for reporting accuracy risks self-fitting. The authors should either hold out the tuning designs, report cross-validated accuracy, or perform a sensitivity analysis over the 5x multiplier to show that the reported results are not dependent on this choice.","section":"Section 2.3; Table 2; Figure 8"},{"comment":"The claim that SynAlign's overall time complexity is 'less than quadratic' is not established. The per-stage complexity O((md-a)*m'd) is quadratic in the worst case unless additional structural properties are proved, and the statement that combinational cells are separated by sequential cells is an informal observation rather than a bound. If the complexity claim is a contribution, the paper should either prove a sub-quadratic bound for the targeted design class or explicitly present the complexity as empirical. As written, Table 1 does not substantiate the 'less than quadratic' statement.","section":"Section 2; Table 1"}],"minor_comments":[{"comment":"The calc_wt() function divides by mismatches, but if the synthesized set and reference set are identical, mismatches is zero and the division is undefined. The paper should specify how this edge case is handled (e.g., returning a large constant).","section":"Section 2.3, Listing 3"},{"comment":"The heading 'Performace evaluation' contains a typo; it should read 'Performance evaluation'.","section":"Section 3.3"},{"comment":"The text says 'Figure 5 shows manual marking accuracies,' but Figure 5 is the NL2NL accuracy plot for RocketTile. The manual accuracy results appear to be in Figure 8. This cross-reference should be corrected.","section":"Section 3.2, paragraph after step 5"},{"comment":"'Inn digital systems like RocketTile' should read 'In digital systems like RocketTile'.","section":"Section 2, paragraph before Section 2.1"},{"comment":"The description of the crossed part of the bars as 'marked with X' is difficult to interpret without a visible legend in the text; a textual description or a proper legend would improve clarity.","section":"Figure 8 description"}],"recommendation":"major_revision","confidential_remarks":"The core idea of using network alignment on hardware netlists is timely and the pseudocode-level algorithm is a useful contribution. The main gap is experimental: both evaluation methodologies avoid the hardest part of the problem. The NL2NL test is a renaming test, and the manual test protects the nets to be aligned. The authors should be encouraged to add an experiment that applies full synthesis (without dont_touch) and annotates nets that were not preserved, and to report accuracy on those. This is feasible in the same tool flow (e.g., by picking random combinational cells and manually checking their source correspondence), so a major revision is an appropriate outcome rather than a rejection."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Read this one if you care about EDA debug flows: it is the first paper I know to use network alignment to map a post-synthesis netlist back to RTL source lines without source locators, and that is a real and useful idea. But do not trust the headline numbers as stated. The 61% tolerance figure comes from NL2NL experiments that only append \"_changed\" to random net names; the netlist topology is untouched. That is name-loss robustness, not tolerance to flattening, retiming, or logic restructuring. The manual accuracy numbers (50-93%, avg 75%) are also measured on nets the authors explicitly forced the synthesizer to preserve with dont_touch/keep, and then manually renamed so they cannot match by name alone. That is a stronger test than NL2NL, but it still does not demonstrate the claimed scenario of pointing at an arbitrary critical-path cell in an optimized netlist and getting the source line. Real critical-path cells are usually not dont_touch nets, and Section 4 concedes the method \"relies on the availability of Anchor links.\" The stress-test note is fair: the central use case is not actually measured.\n\nWhat the paper does well: the algorithm is clearly specified in pseudocode, the multi-stage matching is sensible (anchors, sequential-first, then combinational, with full/half/partial/surrounding passes), and the complexity argument is plausible. Evaluating with both Yosys and Design Compiler, and including Chisel and Verilog designs, is a good-faith effort. The worked walkthroughs of both accurate and inaccurate alignments are genuinely informative, and the limitations section is honest about the anchor dependence. The paper also correctly identifies that propagating source locators through every compiler transformation is expensive and that existing equivalence-checking tools do not give line-level mappings.\n\nThe soft spots are real but not fatal to the core idea. The calc_wt() constant was tuned on PipelinedCPU and SingleCycleCPU, which also appear in the results; that is a mild self-fitting loop, though the main accuracy results are not simply read out of that constant. No code or artifacts are shipped, so the evaluation is not independently reproducible. There are no error bars on the manual accuracy, and no baseline comparison (e.g., simple name matching or a compiler that propagates locators) to calibrate how much value the structural matching adds.\n\nBottom line: this is a promising approach, clearly presented, and worth a serious referee. I would send it to review with a request for major revision: release the tool, add an evaluation on nets that were not preserved by dont_touch/keep, measure accuracy as a function of anchor density, and revise the abstract so the 61% claim is described as renaming noise rather than structural net change.","headline":"First credible graph-alignment approach for netlist-to-source mapping, but the headline accuracy numbers are measured on renamed netlists and dont_touch-preserved nets, so the strong claims outrun the evaluation.","tokens_in":16607,"tokens_out":2578,"would_cite":true,"duration_ms":26512,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"SynAlign automatically maps annotated post-optimized netlists to original source code without source locators.","keywords":["netlist-to-source alignment","synthesis back-annotation","graph alignment","RTL debugging","critical path traceability","network alignment","Chisel","Verilog"],"falsifier":"Take a moderately sized design, synthesize it with aggressive retiming and with every internal net renamed to a fresh temporary name (keeping only top-level ports), then run SynAlign on a random sample of annotated cells; if accuracy does not fall well below the reported 50–93% range, the anchor-dependence premise is contradicted, and if it does drop, the noise-tolerance claim is bounded by anchor survival.","tokens_in":15581,"feed_emoji":"🔗","tokens_out":5112,"duration_ms":47297,"temperature":0.7,"pith_summary":"SynAlign is an automated method for tracing cells in a synthesized, optimized gate-level netlist back to the lines of the original HDL source code, without requiring compilers or synthesis tools to carry source-locator metadata. The paper claims that by treating preserved net names and top-level inputs/outputs as anchors, and then propagating matches through the surrounding connection topology, it can recover the correct source location for annotated netlist cells 50–93% of the time across Verilog and Chisel designs. The practical value is that designers could trace critical-path timing failures to specific source lines in seconds rather than in days of manual correlation, and they could use aggressive optimizations such as flattening and retiming without losing the link back to RTL. The paper also reports resilience to net-rename noise, with alignment accuracy holding until roughly 60% of net names are changed.","feed_headline":"Tracing a chip netlist back to RTL in seconds, without source locators","feed_subtitle":"Maps post-synthesis gates to HDL lines with 50–93% accuracy, surviving up to ~60% net renames.","key_machinery":"The load-bearing mechanism is the directed net graph with Resolved Points (RPs): nets in both the reference graph (G_ref) and the synthesized graph (G_synth) that have been confidently aligned. Start Resolved Points (SRPs) and End Resolved Points (ERPs) are computed for each net through topological traversal from anchor points; a net in G_synth whose SRPs and ERPs are identical to a net in G_ref is a full match, while half matching accepts a match on only one side, and partial matching scores candidates by shared resolved neighbors. Surrounding matching uses the observation that if all directly connected nodes share one source line, the unresolved node is likely at that line too. The algorithm deliberately aligns the sequential subgraph first (typically about 14% of the netlist), then the combinational logic, keeping the overall complexity below quadratic.","core_discovery":"The paper's central claim is that alignment between a post-synthesis netlist and source code is possible from structure alone: if the synthesis tool preserves a small fraction of net names (typically 5–20%) plus the top-level I/O, those anchors supply start and end points, and iterative full, half, partial, and surrounding matching over the directed net graphs walks the remaining nets back to source-code lines. Across all examined benchmarks, SynAlign correctly identifies the source code location 50–93% of the time, with full and surrounding matches reported as perfectly accurate and half/partial matches carrying the error. The NL2NL experiments show tolerance to approximately 60% random net renames without accuracy loss, and even 100% combinational-name noise when sequential names are preserved. The authors present this as the first automated correlation between netlists and source code separated by multiple tools, including for fully flattened and optimized designs.","pith_inferences":["Because the paper ties accuracy to the survival of anchor links, a natural extension is to predict per-design confidence from the measured fraction of preserved net names, turning the 50–93% range into a flow-specific estimate.","The anchor-plus-topology recipe might transfer to tracing other transformed representations, such as optimized compiler IR back to source, though the paper only demonstrates the synthesis setting and synthesis noise is unusually high.","A product extension the paper leaves implicit is a GUI that lets a user click a critical-path cell and jump directly to the corresponding RTL line, with full and surrounding matches flagged as high-confidence and half/partial matches flagged as uncertain.","Since full and surrounding matches are reported as always accurate while half and partial matches carry the error, a practical deployment could surface only high-confidence matches by default and hide lower-confidence ones."],"forward_implications":["Frontend designers can receive early timing and power feedback tied to specific source lines before the backend handoff.","Design teams can enable flattening and retiming without giving up the ability to trace critical-path cells back to RTL.","Backend-to-frontend timing reviews can shift from manual, multi-day netlist tracing to a lookup that returns a source line in seconds.","The same structural approach works across synthesis tools and HDLs, provided the HDL can emit Verilog with line-of-code information.","SynAlign can produce useful mappings even when a large fraction of net names are changed during synthesis, as long as enough sequential anchors survive."],"supporting_citations":[{"why":"Supplies the RocketTile design used as the largest benchmark for accuracy, scalability, and timing measurements.","marker":"[16]"},{"why":"Describes Chisel, the Scala HDL whose emitted Verilog provides the reference graph and line-of-code information for Chisel benchmarks.","marker":"[17]"},{"why":"Design Compiler is one of the two synthesis tools used to produce optimized, flattened, and retimed netlists for evaluation.","marker":"[46]"},{"why":"Yosys is the other synthesis tool, used with the Skywater130 technology library to generate netlists for alignment.","marker":"[51]"},{"why":"The open-source development flow that implements the annotation and alignment pipeline used in the evaluation.","marker":"[49]"},{"why":"The two small CPU designs whose experiments were used to calibrate the calc_wt scoring function for partial matching.","marker":"[27, 28]"}],"fun_headline_variants":["SynAlign maps gates to code lines in seconds, even with 60% net renames","No source locators? SynAlign pulls netlist-to-RTL mapping from structure alone","Up to 93% accuracy: SynAlign traces netlist gates back to their HDL lines","Structural matching: SynAlign aligns flattened netlists to source code without compilers","SynAlign survives 60% net renames, still maps netlist to source code accurately"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The method assumes that synthesis leaves enough stable reference points—top-level inputs/outputs plus the few preserved net names—and enough of the surrounding connection structure intact for matches to propagate; if a flow renames or optimizes away almost every anchor and breaks the local topology, the alignment has no reliable starting point and accuracy degrades.","fun_headline_variants_meta":{"raw":{"variants":["SynAlign maps gates to code lines in seconds, even with 60% net renames","No source locators? SynAlign pulls netlist-to-RTL mapping from structure alone","Up to 93% accuracy: SynAlign traces netlist gates back to their HDL lines","Structural matching: SynAlign aligns flattened netlists to source code without compilers","SynAlign survives 60% net renames, still maps netlist to source code accurately"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000446,"raw_usage":{"total_tokens":2242,"prompt_tokens":919,"completion_tokens":1323,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":535,"completion_tokens_details":{"reasoning_tokens":1211}},"tokens_in":535,"tokens_out":1323,"duration_ms":7846,"temperature":1.0,"reasoning_tokens":1211,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T22:39:09.504106+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a moderately sized design, synthesize it with aggressive retiming and with every internal net renamed to a fresh temporary name (keeping only top-level ports), then run SynAlign on a random sample of annotated cells; if accuracy does not fall well below the reported 50–93% range, the anchor-dependence premise is contradicted, and if it does drop, the noise-tolerance claim is bounded by anchor survival.","supporting_citations":[{"cited_title":"Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Water- man","cited_arxiv_id":null,"evidence_quote":"Supplies the RocketTile design used as the largest benchmark for accuracy, scalability, and timing measurements."},{"cited_title":"Chisel: constructing hardware in a scala embedded language","cited_arxiv_id":null,"evidence_quote":"Describes Chisel, the Scala HDL whose emitted Verilog provides the reference graph and line-of-code information for Chisel benchmarks."},{"cited_title":"Design Compiler User Guide","cited_arxiv_id":null,"evidence_quote":"Design Compiler is one of the two synthesis tools used to produce optimized, flattened, and retimed netlists for evaluation."},{"cited_title":"Yosys Open SYnthesis Suite","cited_arxiv_id":null,"evidence_quote":"Yosys is the other synthesis tool, used with the Skywater130 technology library to generate netlists for alignment."},{"cited_title":"LiveHD: A Productive Live Hardware Development Flow","cited_arxiv_id":null,"evidence_quote":"The open-source development flow that implements the annotation and alignment pipeline used in the evaluation."}],"review_version":1}