{"id":"86cdd91a-6e26-4af1-a53e-af81ce440609","arxiv_id":"2501.07825","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"An FPGA accelerator encodes spike positions to skip zero activations in a spike-driven Transformer, reporting 307.2 GSOP/s peak throughput and 25.6 GSOP/W energy efficiency.","lead":"This paper describes an FPGA accelerator for spike-driven Transformers that encodes where spikes occur and skips zero values in linear, maxpooling, and self-attention calculations. The authors report up to 13.24x throughput and 1.33x energy-efficiency gains over prior spiking-network accelerators, although the comparisons mix different networks and platforms.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Table I's 13.24x/1.33x comparison is not apples-to-apples: SOP definitions, workloads, and FPGA platforms differ across baselines, so the headline speedup and energy ratios are unverified.","rationale":"The reader's weakest_assumption identifies the same load-bearing premise: Table I must be a valid, apples-to-apples comparison for the central speedup and energy claims to hold. This concern is concrete and visible in the manuscript: different networks (FC, CNN, Transformer), datasets (MNIST, MLND, CIFAR-10), and FPGA platforms are listed together, and the SOP definition given in Section IV-B is not shown to match the baselines. The paper's own peak throughput is internally consistent but does not validate the comparison. A concrete recalculation or matched-workload evaluation would settle the issue. Because the reader already assigned CONDITIONAL, this stress-test does not change the verdict; it reinforces the condition: the comparative results need to be re-derived under a unified SOP definition and matched workloads.","tokens_in":6877,"tokens_out":7953,"duration_ms":86683,"concrete_test":"Obtain the three baseline papers and recalculate their reported GSOP/s and GSOP/W using this paper's SOP definition: one operation per nonzero spike-synapse pair, excluding control operations such as SMAM address matches and maxpool ORs. Then either map all four designs to the same network and dataset on the same FPGA family at the same clock frequency, or at minimum recompute Table I with corrected SOP counts and verify whether each baseline's throughput changes by more than 10%. If the corrected numbers shift materially, or if the Transformer workload cannot be mapped to the CNN/FC baselines, the claimed 13.24x and 1.33x improvements are unsupported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claim is the comparative speedup and energy efficiency in Table I. The paper defines SOP as 'a spike traversing a unique synapse', but it never shows that the ISCAS [14], TCAD [15], and AICAS [16] baselines count SOPs the same way. The baselines run FC/CNN workloads on MNIST/MLND on different FPGAs, while the proposed design runs a Transformer on CIFAR-10 on a much larger Virtex UltraScale (453k LUTs vs 42k-46k LUTs for TCAD/AICAS). SOP counts depend on layer type, spike sparsity, fan-out, and how zero-spike operations are skipped; a Transformer workload with high sparsity can report a high peak SOP rate while performing structurally different operations, such as address comparisons and mask-adds, than the multiply-accumulate synaptic operations in CNN baselines. The arithmetic consistency of 307.2 GSOP/s = 1536 PEs x 200 MHz does not validate the 13.24x and 1.33x ratios unless the baseline numbers use the identical SOP accounting and comparable workloads. Without a unified SOP definition or a matched workload evaluation, the headline improvements are not established.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a sparse hardware accelerator for the Spike-driven Transformer. The key idea is to encode the position information of active spikes and skip non-spike values, so that linear, maxpooling, and spike-driven self-attention computations are performed using address comparison and sparse addition rather than dense multiply-accumulate. The accelerator is implemented on a Xilinx Virtex UltraScale FPGA and evaluated on the Spike-driven Transformer with CIFAR-10, reporting a peak throughput of 307.2 GSOP/s, an energy efficiency of 25.6 GSOP/W, and up to 13.24x and 1.33x improvements over prior SNN accelerators.","tokens_in":7093,"tokens_out":3531,"duration_ms":37599,"significance":"The work addresses a real gap: most prior SNN accelerators target convolutional or fully connected spiking networks, while the Spike-driven Transformer requires handling dual spike inputs in self-attention. The proposed position-encoding scheme and the associated SMU, SLU, and SMAM modules are a plausible way to exploit sparsity in transformer-style SNNs. The paper also provides an RTL implementation with resource utilization and frequency details, which is a concrete strength. If the comparative performance claims were rigorously established, this would be a useful contribution to SNN hardware design. However, as presented, the headline speedup and energy-efficiency ratios rest on a comparison across different networks, datasets, and FPGA platforms, without a unified definition of the reported synaptic-operation counts.","major_comments":[{"comment":"The headline improvements of 13.24x and 1.33x are computed from Table I, which compares designs running different networks (FC, CNN, Transformer), different datasets (MNIST, MLND, CIFAR-10), and different FPGA families (Kintex UltraScale, Zynq-7000, Zynq UltraScale, Virtex UltraScale). The paper defines a synaptic operation as 'a spike traversing a unique synapse', but it does not show that the ISCAS [14], TCAD [15], and AICAS [16] baselines use the same SOP accounting, nor that their peak throughput values are measured under comparable sparsity assumptions. Because the proposed design replaces multiply-accumulate operations with address comparisons and mask-adds, equal SOP counts may not represent equal computational work. The 13.24x and 1.33x ratios are therefore not established by the data as presented; a controlled comparison with a unified SOP definition or a matched workload is required.","section":"IV-B, Table I"},{"comment":"The energy-efficiency comparison is load-bearing but relies on inconsistent power methodology. Section IV-A states that hardware utilization and power are estimated using Vivado 2023.2, while the baseline values in Table I come from other published designs, where it is not stated whether power is measured on-chip or estimated, and on different FPGA platforms. The claimed 1.33x energy improvement over the AICAS [16] baseline depends on comparing an estimated power number with an independently reported number. The authors should either measure power on the same board using a consistent methodology or provide a sensitivity analysis showing that the 1.33x ratio is robust to plausible differences in power accounting.","section":"IV-A, IV-B"},{"comment":"The derivation of the peak throughput value 307.2 GSOP/s is not explained in the paper. The number is consistent with 1,536 parallel neurons operating at 200 MHz, but that equivalence assumes each neuron contributes one synaptic operation per cycle in the peak case. Since the architecture is designed to skip non-spike values, the relationship between this peak rate and actual workload sparsity needs to be stated explicitly. Without this, the reader cannot determine whether the comparison in Table I is peak-to-peak, peak-to-average, or something else, and the central throughput claim remains ambiguous.","section":"IV-B"}],"minor_comments":[{"comment":"There is a typo in 'Xilinx Virtex UltarScale' in Section I and in the Experimental Setup; it should read 'UltraScale'. Also, 'Cifar-10' is used inconsistently and should be 'CIFAR-10' throughout.","section":"I, IV-A"},{"comment":"Figure 4 contains garbled glyphs in the PDF text and the comparator data path is difficult to follow. The text says the comparator 'temporarily stores the larger address' during the scan of encoded spikes, but the exact ordering and termination conditions of the comparison loop are not fully specified. Please regenerate the figure and clarify the algorithm, ideally with a small pseudocode listing.","section":"III-C, Fig. 4"},{"comment":"The footnote for the ISCAS [14] baseline says the reported values are an 'average performance under different conditions'. Please specify which conditions are averaged and why an average is the appropriate point of comparison for a peak-throughput and peak-efficiency table.","section":"Table I"},{"comment":"The paper reports 94.87% accuracy after 10-bit weight/activation and 8-bit encoded-spike quantization, but it does not give the accuracy of the unquantized Spike-driven Transformer on CIFAR-10. Adding this baseline would help the reader assess the quantization cost and the practical feasibility of the accelerator.","section":"IV-A"},{"comment":"Reference [6] contains a typo: 'ASPLOPS' should be 'ASPLOS'. Please check all reference titles for similar errors.","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The core architectural idea is sound and the paper is within the scope of the journal. My main concern is purely methodological: the comparative claims in Table I are not yet supported by controlled measurements or a unified operation-count definition. I believe this can be fixed with additional experiments or a careful re-framing of the claims, so I recommend major revision rather than rejection."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Here's my take: the architecture is real and worth a look, but the headline numbers are not yet supported. The position-encoding method is a reasonable adaptation of address-event representation to spike-driven transformer layers. The genuinely new pieces are handling dual spike inputs in self-attention (SMAM) and applying encoded spikes to maxpooling. The modules are described concretely, the 1536-PE / 200 MHz arithmetic is internally consistent, and the implementation is fully on an FPGA, which is more than many accelerator papers do.\n\nThe soft spot is the evaluation. Table I mixes networks (FC, CNN, Transformer), datasets (MNIST, MLND, CIFAR-10), and FPGA platforms (Zynq-7000, Kintex, Virtex). The Virtex UltraScale is roughly 10x the LUT budget of the TCAD and AICAS baselines. The paper defines SOP as 'a spike traversing a unique synapse' but never shows the baselines count SOPs the same way. A Transformer workload with high sparsity can produce high SOP/s while doing qualitatively different operations (address comparisons, mask-adds) than the MAC-dominated CNN baselines. So the 13.24x speedup and 1.33x energy numbers are not established. They are plausible upper bounds, not measured improvements.\n\nTwo smaller issues: power comes from Vivado estimation, not measurement, and the baseline energy numbers may come from different estimation flows. And the 94.87% CIFAR-10 accuracy is reported after quantization but there is no comparison to the original Spike-driven Transformer accuracy, so the quantization cost is unknown. No code or bitstream is provided, which makes independent verification harder.\n\nOverall, the central architectural idea is solid and the paper is clearly written. The comparison problem is fixable in principle: run a matched workload or clearly state that the comparison is across different operating points. I would send this to peer review, not desk reject it, but the reviewers should push for a fair comparison or a revision that drops the 'up to' ratios.\n\nYou could cite it if you work on SNN accelerator design; otherwise it is not going to change your work. I would bring it to a reading group focused on efficient transformer hardware.","headline":"A solid FPGA accelerator for the Spike-driven Transformer with a genuinely new dual-spike attention module, but the headline speedup and energy numbers rest on an apples-to-oranges comparison that peer review should force the authors to fix.","tokens_in":7619,"tokens_out":2797,"would_cite":false,"duration_ms":28360,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper claims that encoding where spikes fire turns linear, maxpooling, and self-attention into address comparison, giving 307.2 GSOP/s at 25.6 GSOP/W.","keywords":["spiking neural networks","spike-driven transformer","hardware accelerator","FPGA implementation","sparse computation","position encoding","self-attention","low-power inference"],"falsifier":"Run the same Spike-driven Transformer and CIFAR-10 benchmark on the same FPGA while fixing one SOP definition across all compared accelerators and measuring power at the board; if the 13.24x throughput or 1.33x energy ratios do not survive that setup, the central quantitative comparison collapses.","tokens_in":6680,"feed_emoji":"⚡","tokens_out":5345,"duration_ms":48633,"temperature":0.7,"pith_summary":"Spike-driven Transformers run on binary spike events, yet prior SNN accelerators still read zero entries and mostly target convolutional or fully connected networks. The paper tries to show that encoding each fired spike's position in memory lets a hardware accelerator skip all non-spike values and execute linear layers, maxpooling, and spike-driven self-attention through address comparison and sparse addition. On a Xilinx Virtex UltraScale FPGA running the Spike-driven Transformer on CIFAR-10, the design reports a peak throughput of 307.2 GSOP/s and an energy efficiency of 25.6 GSOP/W, up to 13.24x and 1.33x better than three prior SNN accelerators. If true, this is a concrete path toward running transformer-scale spiking networks on low-power hardware.","feed_headline":"Spike-position encoding pushes SNN accelerator to 307.2 GSOP/s","feed_subtitle":"Position-coded spikes turn attention into address comparison, reaching 25.6 GSOP/W on CIFAR-10.","key_machinery":"The Spike Encoding Array (SEA) converts each fired spike into its token position and stores the encoded spikes in an Encoded Spike SRAM, so downstream units treat every stored entry as valid and never test for zeros. The Spike Mask-Add Module (SMAM) compares address pairs from spiking Q and K, accumulates matches along tokens, thresholds to build the attention mask, and applies it to encoded V spikes. The Spike Linear Unit (SLU) uses each spike position to index a weight buffer and sums selected weights without multiplication. The shared mechanism is that all computation becomes address comparison and addition.","core_discovery":"The central claim is that a spike can be represented by its position so that zero-valued activations never enter computation. Linear layers reduce to selecting and accumulating weights at encoded spike addresses; maxpooling reduces to checking whether any fired spike's position falls inside a pooling window, with overlap reused across windows; self-attention reduces to comparing two sets of spike addresses, accumulating matches along the token dimension, and thresholding the result to form a mask that gates the value spikes. The report states that this yields 307.2 GSOP/s peak throughput and 25.6 GSOP/W energy efficiency on the Spike-driven Transformer with CIFAR-10, and that the design is unique among the compared accelerators in handling dual spike inputs for self-attention.","pith_inferences":["The position-encoding trick should transfer to other attention mechanisms where keys and queries are sparse or event-driven, such as token pruning in vision transformers, though the paper does not test that.","The reported energy advantage may not survive when off-chip weight and activation movement dominates, because the design spends extra BRAMs and logic on encoding and temporal storage; a board-level power measurement would be the more demanding test.","A natural next experiment is to apply the same encoder to ImageNet-scale spiking transformers or language tasks and check whether 10-bit quantized accuracy of 94.87% on CIFAR-10 degrades."],"forward_implications":["Inference energy and latency scale with the number of fired spikes rather than the tensor dimensions, because non-spike positions never enter the datapath.","The same encoding unit serves maxpooling, linear layers, and self-attention, so a single accelerator core can map a full Spike-driven Transformer, not just convolutional or fully connected SNNs.","Self-attention with two spike inputs costs only address comparison and token-wise accumulation, making attention masks much cheaper than matrix multiplication.","On the reported FPGA implementation, peak throughput of 307.2 GSOP/s and 25.6 GSOP/W indicate that spiking transformers can run under edge-style hardware constraints."],"supporting_citations":[{"why":"Supplies the Spike-driven Transformer model whose sparsity and dual-spike self-attention the accelerator is built around and evaluated on.","marker":"[11]"},{"why":"Supplies the LIF neuron model whose firing behavior the spike encoding units implement.","marker":"[12]"},{"why":"Provides the Tile Engine reused for the convolution portion of Spiking Patch Splitting.","marker":"[13]"},{"why":"Serves as one of the three comparison baselines for throughput and energy efficiency.","marker":"[14]"},{"why":"Serves as one of the three comparison baselines for throughput and energy efficiency.","marker":"[15]"},{"why":"Serves as one of the three comparison baselines for throughput and energy efficiency.","marker":"[16]"}],"fun_headline_variants":["Spike-position encoding skips zeros for 307.2 GSOP/s","Position-coded spikes turn attention into address compares","Dual-spike attention accelerator hits 25.6 GSOP/W","Sparse spike encoding yields 13.24x throughput gain"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The entire quantitative comparison depends on counting synaptic operations the same way in the new accelerator and in the three earlier designs, even though they run different networks on different datasets and FPGAs.","fun_headline_variants_meta":{"raw":{"variants":["Spike-position encoding skips zeros for 307.2 GSOP/s","Position-coded spikes turn attention into address compares","Dual-spike attention accelerator hits 25.6 GSOP/W","Sparse spike encoding yields 13.24x throughput gain"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000466,"raw_usage":{"total_tokens":2308,"prompt_tokens":912,"completion_tokens":1396,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":528,"completion_tokens_details":{"reasoning_tokens":1323}},"tokens_in":528,"tokens_out":1396,"duration_ms":10147,"temperature":1.0,"reasoning_tokens":1323,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T20:35:03.095834+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same Spike-driven Transformer and CIFAR-10 benchmark on the same FPGA while fixing one SOP definition across all compared accelerators and measuring power at the board; if the 13.24x throughput or 1.33x energy ratios do not survive that setup, the central quantitative comparison collapses.","supporting_citations":[{"cited_title":"Spike-driven transformer,","cited_arxiv_id":null,"evidence_quote":"Supplies the Spike-driven Transformer model whose sparsity and dual-spike self-attention the accelerator is built around and evaluated on."},{"cited_title":"Theoretical neuroscience: Computational and mathematical modeling of neural systems,","cited_arxiv_id":null,"evidence_quote":"Supplies the LIF neuron model whose firing behavior the spike encoding units implement."},{"cited_title":"A Unified Acceleration Solution Based on Deformable Network for Image Pixel Processing,","cited_arxiv_id":null,"evidence_quote":"Provides the Tile Engine reused for the convolution portion of Spiking Patch Splitting."},{"cited_title":"An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight,","cited_arxiv_id":null,"evidence_quote":"Serves as one of the three comparison baselines for throughput and energy efficiency."},{"cited_title":"Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance,","cited_arxiv_id":null,"evidence_quote":"Serves as one of the three comparison baselines for throughput and energy efficiency."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Serves as one of the three comparison baselines for throughput and energy efficiency."}],"review_version":1}