{"id":"3320611d-f645-4704-b5ca-38c579f1b0f3","arxiv_id":"2501.09449","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":7,"one_line_summary":"The paper presents circuit designs and simulation results for asynchronously resettable RSFQ gates (AND, OR, XOR, inverter) and memory cells (DFF, TFF, multi-flux DRO) built around the bidirectional alpha cell.","lead":"This paper designs superconducting logic and memory cells that can be reset asynchronously, using a bidirectional connector called the alpha cell. The goal is to let RSFQ circuits avoid complex clock distribution while supporting compact state machines, counters, and high fan-in logic.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The clean-reset assumption is internally contradicted: §III.C shows an α input with no prior data stores negative flux, yet the AND gate claims the reverse path has no inductive elements, so a reset pulse on an idle gate may corrupt the ¬RES ∧ f(A,B) behavior.","rationale":"The reader's weakest assumption correctly identifies that the reset path is assumed non-stateful in the reverse direction and that the MDRO behavior contradicts this. My stress-test sharpens the concern: the contradiction is not merely about partially decrementing stored flux but about the reset pulse creating a negative-flux state from an already idle state, which would invalidate the functional form ¬RES ∧ f(A,B) even in nominal timing. This is load-bearing because every claimed benefit of AR-SFQ (local asynchronous reset, no global clock, compact state machines) rests on the gate returning to the true idle state after reset. The manuscript provides direct internal evidence against this assumption (§III.C), so the central claim is not established by the reported simulations. However, the issue is testable and may be resolved if the reset path in the AND/OR/XOR/DFF/TFF cells is structurally different from the MDRO's α-input path. Therefore a conditional acceptance is appropriate: require the idle-state reset simulation for all cells, plus a statement of the structural difference if the reset paths are not inductive. I do not call for rejection because the simulations may indeed show clean reset for the logic cells; the concern is about missing evidence and an internal contradiction, not about a proven failure independent of simulation. No fabrication or process-corner data would be needed to settle this specific point, making the requested check inexpensive and decisive.","tokens_in":8699,"tokens_out":2501,"duration_ms":29522,"concrete_test":"Run analog simulations (e.g., JSIM) for each AR-SFQ cell with the published parameters: (1) initialize the cell to the idle state with no inputs; (2) apply exactly one reset pulse at the reset/output port; (3) apply CLK with all data inputs at logic 0 and observe the output; (4) repeat with two reset pulses while idle. If any output pulse appears in step 3 or 4, or if a subsequent normal data evaluation produces a wrong output after the reset, the reverse path is stateful and the clean-reset claim fails. The decisive configuration is the AND gate and the DFF, since those cells explicitly rely on 'no inductive elements in the reverse direction'.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The central claim is that integrating the α-cell gives each cell an asynchronous reset that returns it to the idle state, captured as ¬RES ∧ f(A,B), with no state retention in the reverse direction. That claim depends on a specific physical assumption stated for the AND gate: 'the absence of inductive elements in the reverse direction, preventing it from retaining state information in the reverse direction' (§II.B.1). However, the manuscript itself demonstrates the opposite behavior for the multi-flux DRO: 'applying an α input when no prior data is present results in the storage of this input as a negative flux in the loop' (§III.C, Negative pulse storage). The α input there is the same reset mechanism: it decrements stored flux and, critically, can write negative flux into an idle loop. If the same physics applies to the reset ports of the AND, OR, XOR, DFF, and TFF cells, then a reset pulse arriving while the cell is already idle will leave it in a negative-flux state, not the (0,0) idle state. A subsequent f(A,B) evaluation would then be corrupted, and the stated function ¬RES ∧ f(A,B) would fail even under the advertised timing windows. The paper provides no simulation evidence that the reset path of each cell is non-stateful when the cell is idle; the admitted XOR timing error (Fig. 6, star) is consistent with reset-path statefulness. This is not a process-variation or margin issue: it is a potential correctness failure of the central construction, and it is supported by the manuscript's own simulation of negative-flux storage.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes an asynchronous reset RSFQ (AR-SFQ) cell library built around the α-cell, a bidirectional interconnect element previously introduced by the same group. The library includes AND, OR, XOR, inverter, DFF, TFF, and multi-flux DRO cells, each with an asynchronous reset signal applied through the α-cell. The central claim is that a reset pulse returns every cell to its idle state, so each gate executes the reset-modified function ¬RES ∧ f(A,B), and this is achieved without increasing area or bias overhead. Validation is performed with analog simulations, and component values and some critical margins are reported.","tokens_in":9081,"tokens_out":3433,"duration_ms":34159,"significance":"If correct, the library would be a practical contribution to RSFQ design, enabling localized asynchronous reset without a global clock and potentially simplifying state machines, branch prediction, and neuromorphic topologies. The manuscript has notable strengths: complete component lists for every cell, simulation waveforms for all cells, explicit critical margins and timing windows for the logic gates, and a clear statement of the intended logic function. These details make the design reproducible in principle. However, the central physical assumption that the reset path is non-stateful is in tension with the authors' own demonstration of negative-flux storage in the multi-flux DRO, and the reliability claims are not backed by process-variation or yield analysis. The work is therefore promising but needs substantial revision to establish correctness and robustness.","major_comments":[{"comment":"The non-statefulness assumption for the reset path is contradicted by the manuscript's own results. Section II.B.1 states for the AND gate that 'the absence of inductive elements in the reverse direction, preventing it from retaining state information in the reverse direction,' but Section III.C, 'Negative pulse storage,' demonstrates that applying an α input with no prior data stores that input as negative flux in the multi-flux DRO loop. Since the reset port in every AR-SFQ cell is the same α-cell mechanism, a reset pulse arriving while a cell is already idle could write negative flux into the storage loop, corrupting the subsequent ¬RES ∧ f(A,B) behavior. No simulation evidence is provided that the reset path of the AND, OR, XOR, DFF, or TFF is non-stateful under idle conditions; the admitted XOR timing violation (Fig. 6, star) is consistent with exactly this failure mode. This is a load-bearing correctness issue, not a margin or timing concern.","section":"§III.C"},{"comment":"The manuscript claims reliability and correct functionality via analog simulations, but no margin values are given for the memory cells. Figure 10's caption states 'The circuit parameters and margin values are provided,' yet the figure lists only inductances and critical currents, with no margin or timing data for the DFF. Similarly, the TFF (Fig. 13) and multi-flux DRO (Fig. 16) lack margin values. No Monte Carlo or process-variation analysis appears anywhere in the paper. Since the reset mechanism's timing windows are given only for AND and XOR, the robustness of the reset path for OR, inverter, and all memory cells is unquantified, which is a significant gap for a cell-library paper.","section":"Conclusion"},{"comment":"The conclusion states that the library is developed 'without increasing the overall area and bias overhead of individual cells,' but the manuscript provides no area, JJ-count, or bias-current comparison between the AR-SFQ cells and conventional RSFQ cells with reset functionality. The schematics show the α-cell added to each logic gate, which presumably adds junctions and wiring, so the claim is unsupported. A quantitative comparison of junction counts and bias current requirements is needed to substantiate this assertion.","section":"Conclusion"}],"minor_comments":[{"comment":"The caption says margin values are provided, but the figure only gives component parameters; the margin values for the DFF are missing.","section":"Fig. 10"},{"comment":"References [11] and [16] appear to be the same paper (same title, same authors, same venue and year); [16] lacks volume/page details. This should be resolved.","section":"References"},{"comment":"The OR gate description is unclear about the effect of a reset signal that arrives before input data: it says the reset 'can suppress the first input signal' but also that if two pulses arrive after a premature reset the output is still logic-1. The exact intended behavior and timing constraints should be stated more precisely.","section":"§II.B.2"},{"comment":"The description of the α-DFF-based XOR (Fig. 19) would benefit from a timing diagram or explicit truth-table demonstration, since the claimed generation of A ∧ ¬B, B ∧ ¬A, and A ⊕ B from two DFFs and two α-cells is not obvious from the text alone.","section":"§IV"},{"comment":"The acronym is inconsistently given as AR-SFQ in the title/abstract and AR-RSFQ in the conclusion; please standardize.","section":"Abstract"},{"comment":"There are several typographical and grammatical issues, e.g., 'the clock causes a large skew' in the abstract, 'whether' for 'whether' in §II.B.1, and 'α input' where 'an α input' is meant. A careful proofread is recommended.","section":null}],"recommendation":"major_revision","confidential_remarks":"The paper leans heavily on the authors' own α-cell [9] and qCS optimizer [17] without independent validation, which is appropriate for a research paper but worth noting for the editor. The apparent duplication of Refs. [11] and [16] should be checked. The central contradiction between the non-statefulness assumption and the negative-flux storage demonstration needs to be resolved before the paper can be considered for publication."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The paper is a genuine, if incremental, extension of the group's own α-cell work: it systematically adds asynchronous reset to standard AND, OR, XOR, inverter, DFF, TFF, and multi-flux DRO cells, and it documents state machines, timing windows, and component values. That is a real contribution to the SFQ design library space, and the core idea—local reset without a global clock—is sensible and potentially useful for state machines and higher-fanin circuits.\n\nWhat the paper does well: it gives concrete schematics with component values, reports critical margins for the logic gates, and shows analog simulation waveforms for the main cells. The state-machine descriptions for the DFF, TFF, and multi-flux DRO are clear. The architectural discussion about targeted resets in shift registers and branch prediction is plausible, even if speculative.\n\nWhere it is soft: the evidence outruns the claims. There is no Monte Carlo or process-variation analysis, no fabricated chip, no released netlists, and no margin values for the memory cells. The admitted XOR timing error (Fig. 6, star) is a red flag that should be explained. The paper also leans heavily on the group's own α-cell (ref [9]) and their qCS optimizer (ref [17]); that is not a problem per se, but it means independent verification is lacking.\n\nOn the stress-test concern: the negative-flux storage shown in §III.C is for a deliberately parameter-modified multi-flux DRO, not for the standard reset paths of the AND/OR gates, so I would not call it an outright internal contradiction. But the concern is fair as an unexamined risk. The authors claim the reverse path lacks inductive elements and therefore cannot retain state, yet they never show a simulation of a reset pulse arriving while a gate is already idle and then demonstrate that a subsequent operation is correct. Given that the reset mechanism does involve flux injection, that scenario should be explicitly tested. The paper currently asserts the behavior without providing the evidence.\n\nThe bottom line: this is a reasonable design-study paper for the superconducting electronics community. It is not ready for publication as-is, but it deserves peer review. A serious referee should ask for the missing margin analysis, explicit reset-on-idle simulations, netlists and process parameters, and a baseline comparison against conventional clocked reset. If those are added, the paper could be a useful library reference. If not, the claims should be scaled back to what is actually demonstrated.","headline":"A useful and plausibly working asynchronous reset extension of the group's own α-cell work, but the evidence base is thinner than the claims.","tokens_in":9613,"tokens_out":2150,"would_cite":false,"duration_ms":24075,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Integrating a bidirectional α-cell gives RSFQ logic and memory cells an asynchronous reset, enabling each cell to execute ¬RES ∧ f(A,B) without extra area or bias overhead.","keywords":["RSFQ","single flux quantum","alpha-cell","bidirectional signal propagation","asynchronous reset","superconductor logic","cell library","flux storage"],"falsifier":"Apply a reset pulse to an empty AND, OR, or XOR cell and then measure the loop current at the storage inductance; if any residual flux is stored (as the paper's multi-flux DRO does with negative-flux bias), the reverse path is stateful and the clean-reset claim fails. Alternatively, run a Monte Carlo yield simulation over the stated reset timing windows (e.g., AND reset between 6.84 ps before first input and 4.5 ps before clock, XOR between 15.14 ps and 10 ps) and count functional errors; any error at nominal bias would falsify the claimed reliability.","tokens_in":8534,"feed_emoji":"🔁","tokens_out":5459,"duration_ms":51909,"temperature":0.7,"pith_summary":"The paper claims that a bidirectional interconnect cell called the α-cell can be grafted onto ordinary RSFQ logic gates and memory cells to give each one an asynchronous reset: a pulse arriving through the output port reverses the stored data flow and returns the cell to its idle state. If true, this removes the need for a global clock or a separate reset network to clear pipeline stages, shift-register memory, and state machines, and it lets a single cell compute a reset-modified function such as $\\neg\\text{RES}\\wedge f(A,B)$ without adding area or bias overhead. The authors support the claim with analog simulations of AND, OR, XOR, inverter, DFF, TFF, and multi-flux DRO cells, reporting parameter margins and reset timing windows for each.","feed_headline":"Local async reset for SFQ gates, no extra area","feed_subtitle":"A bidirectional alpha-cell lets RSFQ logic and memory reset in place, skipping the global clock.","key_machinery":"The α-cell is an interconnect cell with three inputs, two outputs, and asymmetric Josephson-junction loops that allow SFQ pulses to travel in both directions: forward it behaves as a Josephson transmission line, reverse it behaves as a confluence buffer performing parallel-to-serial conversion. It carries the argument by providing a reverse port through which a reset pulse can enter a logic or memory cell, decrement or clear the stored flux in the destructive-readout loop, and restore the cell to its idle state. The relevant physical mechanism is flux quantization in superconducting loops: stored flux is an integer multiple of $\\Phi_0$, so a counter-propagating pulse can subtract one flux quantum, and the reset-modified function $\\neg\\text{RES}\\wedge f(A,B)$ follows from the absence of inductive state in the reverse path.","core_discovery":"The central discovery is that the α-cell's reverse signal path can be reused as a local reset mechanism. In each AR-SFQ cell, a reset pulse applied at the output pin travels backwards through the α-cell and discharges the flux stored in the cell's destructive-readout loop, reactivating the primary escape junctions and restoring the default state. Because the reverse path is designed without inductive elements, the reset is claimed to be memoryless: it does not store state in the reverse direction and does not generate a reverse pulse at the input port when the loop is empty. Functionally, every gate in the library executes $\\neg\\text{RES}\\wedge f(A,B)$, and the same structure adds reset to DFF and TFF memory cells, gives the inverter a compact implementation using a multi-flux DRO with positive and negative flux cancellation, and turns the multi-flux DRO into a decrementable storage element that can hold up to four flux quanta and even store negative flux as a bias.","pith_inferences":["If the memoryless reverse path holds, the α-reset pattern may extend to any DRO-style RSFQ cell, but the paper's own XOR timing violation (starred peak in Fig. 6) suggests that each cell's reset window, not the clock, becomes the new timing constraint that synthesis tools must satisfy.","The multi-flux DRO's demonstrated negative-flux storage implies that a reset pulse is physically a decrement by one flux quantum rather than an absolute clear; in cells whose loops can hold multiple quanta, an incomplete reset might leave residual bias, so the claimed clean idle state should be verified under multi-pulse reset sequences and process variation.","Combining α-reset DFFs to form AND-invert and XOR functions suggests a synthesis mapping where reset ports serve as logic inputs, not just control; this could reduce cell count for arithmetic datapaths, but it will require design tools that understand pulse-direction encoding."],"forward_implications":["Local reset of individual DFFs in a shift-register memory can clear a target address without shifting all bits through the chain, reducing clock cycles for memory rewrite.","Branch misprediction recovery can reset only the affected computational stages, preventing erroneous signals from propagating without a global reset.","Two α-DFF pairs with crossed reset outputs produce $A\\wedge\\neg B$ and $B\\wedge\\neg A$ and, merged through one CBU, yield $A\\oplus B$, giving three functions from the same components.","The multi-flux DRO with α reset can act as an up-down counter, store up to four bits plus negative-flux bias, and support bidirectional counting.","The inverter is implemented more compactly by using the reset path as a negative-flux input to an MDRO, with higher error margin than a standard RSFQ inverter."],"supporting_citations":[{"why":"Supplies the validated bidirectional α-cell design that the reset scheme is built on.","marker":"[9]"},{"why":"Provides the cell-optimization method used to set all component values and margins.","marker":"[17]"},{"why":"Establishes the RSFQ logic and memory family and the pulse encoding that the reset-modified function builds on.","marker":"[1]"},{"why":"Offers an RSFQ/ERSFQ cell library baseline for comparing the complexity of adding reset to individual cells.","marker":"[14]"}],"fun_headline_variants":["Bidirectional alpha-cell resets SFQ gates in place","SFQ async reset via reverse signal path","Local reset in RSFQ skips global clock","Alpha-cell makes SFQ reset memoryless and local"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that a reset pulse travelling backward through the α-cell clears a gate's stored flux completely and leaves no state behind, so the cell always returns to its idle (0,0) or set state; if the reverse path can instead partially decrement stored flux or leave residual bias, the reset-modified functions $\\neg\\text{RES}\\wedge f(A,B)$ would not hold for all input histories.","fun_headline_variants_meta":{"raw":{"variants":["Bidirectional alpha-cell resets SFQ gates in place","SFQ async reset via reverse signal path","Local reset in RSFQ skips global clock","Alpha-cell makes SFQ reset memoryless and local"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000172,"raw_usage":{"total_tokens":1245,"prompt_tokens":882,"completion_tokens":363,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":498,"completion_tokens_details":{"reasoning_tokens":313}},"tokens_in":498,"tokens_out":363,"duration_ms":4445,"temperature":1.0,"reasoning_tokens":313,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T20:01:11.810569+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Apply a reset pulse to an empty AND, OR, or XOR cell and then measure the loop current at the storage inductance; if any residual flux is stored (as the paper's multi-flux DRO does with negative-flux bias), the reverse path is stateful and the clean-reset claim fails. Alternatively, run a Monte Carlo yield simulation over the stated reset timing windows (e.g., AND reset between 6.84 ps before first input and 4.5 ps before clock, XOR between 15.14 ps and 10 ps) and count functional errors; any error at nominal bias would falsify the claimed reliability.","supporting_citations":[{"cited_title":"α-soma: Single flux quantum threshold cell for spiking neural network implementations,","cited_arxiv_id":null,"evidence_quote":"Supplies the validated bidirectional α-cell design that the reset scheme is built on."},{"cited_title":"Margin and yield optimization of single flux quantum logic cells using swarm opti- mization techniques,","cited_arxiv_id":null,"evidence_quote":"Provides the cell-optimization method used to set all component values and margins."},{"cited_title":"Rsfq logic/memory family: a new josephson-junction technology for sub-terahertz-clock-frequency digital systems,","cited_arxiv_id":null,"evidence_quote":"Establishes the RSFQ logic and memory family and the pulse encoding that the reset-modified function builds on."},{"cited_title":"Rsfq/ersfq cell library with improved circuit optimization, timing verification, and test characterization,","cited_arxiv_id":null,"evidence_quote":"Offers an RSFQ/ERSFQ cell library baseline for comparing the complexity of adding reset to individual cells."}],"review_version":1}