{"id":"9fba4350-41aa-4281-a533-ffea06aea187","arxiv_id":"2501.13610","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"A two-queue circular design stores synaptic delays in digital spiking chips with memory proportional to activation sparsity times input size.","lead":"This paper presents a new memory structure, the Shared Circular Delay Queue, for handling synaptic delays in digital neuromorphic chips, and shows it uses less queue memory than existing designs when neuron activity is sparse. The structure was tested on the Seneca accelerator, where the hardware version cut inference latency and energy compared with a software version.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"SCDQ memory-advantage claim rests on an unmeasured and unenforced α; with measured Seneca memory exceeding Loihi's in all four networks, the crossover is not demonstrated.","rationale":"The reader's weakest assumption is exactly the load-bearing point: the claimed memory advantage over ring buffers depends on activation sparsity α being low enough to pass the crossover threshold, and the paper neither reports α per model nor demonstrates on the evaluated networks that the crossover is reached. Table II directly shows that measured total memory on Seneca is larger than on Loihi for all four networks, so the empirical support is absent. I add the observation that α is an average statistic rather than a hard bound, which makes the α-based capacity formula risky as a hardware sizing rule without flow control or a guaranteed spike-rate cap. This does not overturn the paper's theoretical construction, but it reinforces the reader's CONDITIONAL verdict: the design is plausible and the formulas are internally consistent, yet the central memory-advantage claim remains unsubstantiated by the reported measurements. No change to the reader's verdict is needed; the same condition — demonstrating α and total memory under matched configurations — would resolve both concerns.","tokens_in":11085,"tokens_out":9606,"duration_ms":91799,"concrete_test":"Re-run all four networks in PyTorch on the full SHD evaluation set; for every delayed projection, compute the per-timestep activation density (max and average) and the resulting SCDQ capacity α·I·(2D−1). Then map the same models to a single Seneca core with matched precision (or scale Loihi appropriately to 3 cores) and compare total memory. Also instrument the Delay IP RTL with an assertion on PRQ/POQ full conditions; if any overflow occurs over the full test set, the α-based memory formula is not a safe hardware sizing rule and the lossless claim fails.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central scalability claim is SCDQ memory overhead α·I·(2D−1), and the Discussion argues that this beats Loihi's ring buffer only when α≤0.25. However, α (defined in Section II as activation density, 1 meaning every presynaptic neuron fires) is never reported for any of the four evaluated networks. Table II shows total memory on Seneca (3 cores, bfloat16) of 3.38/2.33/2.07/3.36 Mb versus Loihi (1 core, int8) of 1.96/1.48/1.23/1.96 Mb — larger in every case, so the crossover condition is not met empirically. Moreover, in a spiking network α is a data-dependent average, not a deterministic upper bound; the α-based capacity formula assumes a fixed maximum spike rate, but nothing in the SCDQ design enforces such a bound. Without a hard spike-rate cap or backpressure, bursty inputs can overflow the PRQ/POQ, and the fidelity test on only 100 SHD datapoints is too small to bound worst-case bursts. The headline memory advantage is therefore an analytic possibility, not a demonstrated property of the evaluated models or a verified hardware sizing rule.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes the Shared Circular Delay Queue (SCDQ), a two-FIFO circular structure for implementing synaptic delays in digital event-driven neuromorphic accelerators. It derives an analytical memory overhead of α·I·(2D−1) for SCDQ, compares it with the shared delay queue's O(α·I·D²) and with ring-buffer approaches, and reports a hardware implementation integrated into the Seneca processor. The authors evaluate four spiking network models on the SHD benchmark, reporting software/hardware fidelity, energy, latency, memory, and area, and conclude that the Delay IP adds only 2–3% of inference energy while improving latency compared to a software implementation.","tokens_in":11298,"tokens_out":8517,"duration_ms":75258,"significance":"If the SCDQ memory formula holds, the result is valuable: delay memory overhead becomes linear in the number of delay levels and presynaptic neurons, modulated by activation density, rather than quadratic in D. The hardware implementation, including the W V U pruning filter and the SRAM-based queue, is a concrete contribution, and the measured 2–3% energy overhead of the Delay IP is a useful, clearly quantified data point. The fidelity comparison between PyTorch and Seneca is a sound validation step, and the area reduction from flip-flop to SRAM memory (81%) is convincingly reported. However, the broader claims of memory, energy, and latency advantage over existing systems are not yet fully supported by the experiments as presented.","major_comments":[{"comment":"The claim that SCDQ beats Loihi's ring buffer when α≤0.25 is not validated empirically, because α is never reported for the four evaluated networks. The only indirect evidence is the SRAM sizing in Section IV-C: the 2048-word SRAM holds an observed maximum of 1596 events; for the 48-48-20 network with I=48 and D=60, the paper's own formula α·I·(2D−1) gives α≈0.28, just above the crossover threshold. This is consistent with Table II, where total Seneca memory exceeds Loihi's in all four networks. Please report α per model and per layer, and provide a controlled comparison of delay-queue memory only, rather than total core memory.","section":"Section V (Discussion), Table II"},{"comment":"The queue-capacity formula uses α as an average activation density, but a hardware queue must be sized for worst-case occupancy. The SRAM capacity is chosen from an observed maximum over a 100-sample test set; no backpressure, overflow handling, or upper bound on spike rate is described. If a burst exceeds the 2048-event capacity, the SCDQ will either drop events or stall the core, and neither behavior is discussed. The paper should either specify a hard spike-rate cap, provide a worst-case capacity analysis, or describe and validate the overflow policy.","section":"Section III-A, Section IV-C"},{"comment":"The energy and latency comparison with Loihi is not controlled: Loihi runs on 1 core with int8 quantization while Seneca runs on 3 cores with bfloat16. The reported 1.2–1.9× lower energy efficiency and the 'less than 0.5×' latency advantage therefore cannot be attributed to SCDQ versus ring buffers. Please provide a normalized comparison (e.g., per-core energy, energy per event, or a same-resource/same-precision mapping) before claiming that SCDQ improves latency or closes the energy gap.","section":"Section IV-B, Table II"}],"minor_comments":[{"comment":"The text contains 'SCDC' instead of 'SCDQ' and refers to 'Figure ??' for the block diagram; the figure reference should be resolved.","section":"Section III-A"},{"comment":"The Shared Delay Queue formula writes ∑_{d=1}^D(D−d) = ½(D²+D), but the sum from d=1 to D of (D−d) is D(D−1)/2; please correct the indexing or the closed form.","section":"Section II"},{"comment":"The symbol α is called 'activation sparsity' but α=1 denotes every neuron active; this is activation density, not sparsity. The text also contains the typo 'no spasity'.","section":"Section V"},{"comment":"The captions state that activations are shown 'on Seneca, Loihi and PyTorch', but the figures contain only PyTorch and Seneca panels; either add Loihi panels or correct the captions.","section":"Figures 5 and 6"},{"comment":"The 'Consistency against PyTorch' row for PyTorch is trivially 100%; clarify that this is self-consistency and define the consistency metric.","section":"Table I"}],"recommendation":"major_revision","confidential_remarks":"The manuscript would be strengthened by clearly separating analytic scaling claims from measured results. The current title and abstract imply a demonstrated hardware advantage, while the experiments directly support only a 2–3% energy overhead for the Delay IP and a fidelity match; the memory and latency advantages are analytic or conditionally argued. The authors should either add the missing α and queue-utilization measurements, add overflow/backpressure analysis, and perform a controlled comparison, or temper the claims in the abstract and conclusion."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The core idea here is real. SCDQ replaces a cascade of FIFOs with two circular queues that swap at end-of-timestep and let events orbit, which cuts the queue-memory scaling from O(α·I·D²) to O(α·I·D) and, for the first time in this line of work, supports per-synapse delays rather than only axonal delays. The capacity formula α·I·(2D−1) is derived from the queue's own operation, not fitted to measurements, and it checks out. The WVU pruning filter is a sensible zero-skipping optimization, and the fidelity check between PyTorch and the Seneca testbench—while small—is the kind of sanity check that many hardware papers skip. The area savings from moving the queue memory to SRAM are also concrete and well reported.\n\nThe main soft spot is exactly what the stress-test note flags: the memory-advantage claim rests on α, but α is never reported for any of the four evaluated networks. Table II shows Seneca using 3.38/2.33/2.07/3.36 Mb versus Loihi's 1.96/1.48/1.23/1.96 Mb—larger in every case. So the crossover condition α≤0.25 is not met in these experiments. That doesn't make the design wrong, but it makes the headline claim an analytic possibility rather than a demonstrated property. The paper should either report per-model α or soften the claim.\n\nThe cross-platform comparisons are also confounded by 1 core versus 3 cores and int8 versus bfloat16. The authors acknowledge this, which is fair, but it still limits what the energy and latency numbers can support. The latency reduction to roughly half of Loihi's is striking even with more cores, but the energy comparison is not favorable to Seneca and the confound makes it hard to interpret.\n\nThe fidelity test on 100 SHD datapoints is small, and the paper is silent on overflow behavior. Without a hard spike-rate cap or backpressure, the FIFO sizing formula is a steady-state estimate. A bursty input could overflow the queue; that's a limitation worth stating explicitly.\n\nWho is this for: hardware architects and neuromorphic researchers working on delay-parameterized SNNs. The structural contribution and the queue-level analysis are solid, and the empirical gaps are fixable in revision. This deserves a serious referee, and I'd recommend sending it to peer review with a request to report α, bound the overflow risk, and reframe the memory claim as conditional on sparsity rather than demonstrated on the evaluated models.","headline":"SCDQ is a genuine architectural novelty with sound queue-level math, but the paper's headline memory advantage over ring buffers is not demonstrated on its own measurements because activation sparsity α is never reported and measured memory on Seneca exceeds Loihi's in every tested network.","tokens_in":11904,"tokens_out":2027,"would_cite":false,"duration_ms":20462,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A two-FIFO circular queue makes synaptic-delay memory scale with activation sparsity, not network size.","keywords":["spiking neural networks","synaptic delays","neuromorphic hardware","event-driven accelerators","shared circular delay queue","activation sparsity","delay parameterization","digital accelerator memory"],"falsifier":"Compute the average activation density $\\alpha$ of the trained 48-48-20 model on the Spiking Heidelberg Digits test set. If $\\alpha > 0.25$, then the SCDQ stored-event count $\\alpha \\cdot 48 \\cdot (2\\cdot 60-1)$ would exceed the equivalent ring-buffer count for Loihi's configuration, and the claimed memory crossover would not hold for that model.","tokens_in":10889,"feed_emoji":"⚡","tokens_out":5698,"duration_ms":50024,"temperature":0.7,"pith_summary":"The paper introduces Shared Circular Delay Queue (SCDQ), a two-FIFO circular structure for digital spiking accelerators that stores synaptic-delay events. It argues that this structure makes delay memory scale with the network's activation density rather than with network size: overhead is $\\alpha \\cdot I \\cdot (2D-1)$, where $\\alpha$ is the fraction of presynaptic neurons that fire, $I$ is the number of presynaptic neurons, and $D$ is the number of delay levels. That is $O(\\alpha I D)$, compared with $O(\\alpha I D^2)$ for a shared delay queue, and lower than ring-buffer memory below a sparsity threshold. If true, delay-parameterized spiking models, which are already smaller and sparser after training, could run cheaply on event-driven hardware. The paper supports this with measurements on the Seneca platform, where the delay hardware adds only 2–3% of inference energy and about 3% of core area after SRAM optimization.","feed_headline":"A two-buffer queue makes synaptic-delay memory scale with sparsity","feed_subtitle":"SCDQ hardware adds 2–3% energy per inference and could make delay-trained spiking models cheap to run.","key_machinery":"The central object is the Shared Circular Delay Queue (SCDQ): a pair of FIFOs, the pre-processing queue (PRQ) and post-processing queue (POQ), arranged in a loop with a buffer swap triggered by an end-of-timestep event. Each event is tagged with a delay counter and may be forwarded, stored, or both, letting one presynaptic event exit at several different delay steps. The zero-skipping delay-forwarding filter maintains a binary matrix, $WVU$, that records whether any non-zero weight remains for a given presynaptic neuron and delay level, so useless events can be dropped before they consume queue capacity. This combination is the mechanism that turns delay memory from quadratic-in-$D$ scaling into $O(\\alpha I D)$ scaling.","core_discovery":"The central claim is that SCDQ stores delayed synaptic events in two interconnected FIFOs, the pre-processing queue and post-processing queue, which swap buffers at each end-of-timestep. Incoming events carry a delay counter and can orbit the pair, exiting at multiple future timesteps, which supports per-synapse delays rather than only axonal delays. The memory overhead is $\\alpha \\cdot I \\cdot (2D-1)$, scaling as $O(\\alpha I D)$, versus $\\tfrac{1}{2}\\alpha I (D^2+D)$ for a shared delay queue. A pruning filter using a binary $WVU$ matrix drops events whose delayed synapses are all zero, so activation sparsity directly shrinks queue occupancy. Measured on Seneca, the circuit implementation of SCDQ adds 2–3% to inference energy and cuts latency several-fold compared with a software delay queue on the same core.","pith_inferences":["The paper does not report the actual activation density $\\alpha$ of its trained models, so the crossover claims against Loihi and SpiNNaker are conditional; measuring $\\alpha$ per layer would turn them into a testable prediction.","The single-FIFO pointer variant sketched in the paper would reduce memory to $\\alpha \\cdot I \\cdot D$, roughly doubling the advantage; this is a natural next hardware target.","If delay-trained models commonly reach $\\alpha < 0.25$, SCDQ-type structures could become the default delay primitive in edge accelerators, making delay parameterization a standard model knob.","Because SCDQ lets an event exit at several timepoints, it can express per-synapse delay patterns that axonal-only shared queues cannot, which may enable new delay-parameterized model families."],"forward_implications":["Memory for synaptic delays becomes a function of activation sparsity, so training procedures that encourage sparse firing directly reduce hardware cost.","At activation density $\\alpha \\leq 0.25$, SCDQ uses less delay memory than Loihi-style ring buffers at 64 delay steps, and at $\\alpha \\leq 0.5$ less than SpiNNaker-style ring buffers.","Axonal pruning gives larger hardware savings than per-synapse pruning alone, because pruning an entire axon lets events drop from the queue before their maximum delay.","A circuit implementation of SCDQ improves energy per inference by 3.1–3.5× and latency by 3.5–4.3× over a software implementation on the same processor core, with the delay hardware contributing only 2–3% of inference energy.","Sharing an SCDQ across layers mapped to one compute core makes delay memory depend on the number of cores, not the number of layers."],"supporting_citations":[{"why":"Supplies the TrueNorth shared delay queue baseline, its FIFO-cascade structure, and the 16-timestep/256-neuron constraints used for the memory comparison.","marker":"[1]"},{"why":"Supplies the Loihi ring-buffer baseline, including the 64-delay-step and 8-bit-weight configuration used for the memory crossover and the energy/latency comparison.","marker":"[2]"},{"why":"Supplies the SpiNNaker ring-buffer baseline, with 16 timesteps and 16-bit weights, used for the second memory crossover comparison.","marker":"[3]"},{"why":"Supplies the delay parameterization and per-synapse delay pruning technique on which SCDQ's operation and sparsity-dependent memory claims rely.","marker":"[6]"},{"why":"Supplies the Address Event Representation packet format that SCDQ extends with a delay-counter field.","marker":"[11]"},{"why":"Supplies the Seneca neuromorphic platform, its core architecture, and the integration point where the Delay IP is measured.","marker":"[12]"},{"why":"Supplies the Spiking Heidelberg Digits benchmark used to train and test the four network configurations reported in the fidelity and hardware measurements.","marker":"[14]"}],"fun_headline_variants":["Two-FIFO SCDQ scales delay memory with sparsity","SCDQ adds synaptic delays for just 2-3% energy","Sparsity-slashing delay queues for event-driven AI","Double FIFO cuts synaptic-delay memory footprint","Delay memory that follows model sparsity, not size"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The memory advantage over ring buffers depends on the trained models having activation density $\\alpha$ at or below the crossover threshold (0.25 versus Loihi, 0.5 versus SpiNNaker), and the paper does not report $\\alpha$ for its own models.","fun_headline_variants_meta":{"raw":{"variants":["Two-FIFO SCDQ scales delay memory with sparsity","SCDQ adds synaptic delays for just 2-3% energy","Sparsity-slashing delay queues for event-driven AI","Double FIFO cuts synaptic-delay memory footprint","Delay memory that follows model sparsity, not size"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00016,"raw_usage":{"total_tokens":1186,"prompt_tokens":856,"completion_tokens":330,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":472,"completion_tokens_details":{"reasoning_tokens":247}},"tokens_in":472,"tokens_out":330,"duration_ms":3460,"temperature":1.0,"reasoning_tokens":247,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T15:46:23.089806+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Compute the average activation density $\\alpha$ of the trained 48-48-20 model on the Spiking Heidelberg Digits test set. If $\\alpha > 0.25$, then the SCDQ stored-event count $\\alpha \\cdot 48 \\cdot (2\\cdot 60-1)$ would exceed the equivalent ring-buffer count for Loihi's configuration, and the claimed memory crossover would not hold for that model.","supporting_citations":[{"cited_title":"Akopyan, J","cited_arxiv_id":null,"evidence_quote":"Supplies the TrueNorth shared delay queue baseline, its FIFO-cascade structure, and the 16-timestep/256-neuron constraints used for the memory comparison."},{"cited_title":"Davies, N Srinivasa, T-H","cited_arxiv_id":null,"evidence_quote":"Supplies the Loihi ring-buffer baseline, including the 64-delay-step and 8-bit-weight configuration used for the memory crossover and the energy/latency comparison."},{"cited_title":"Khan, D.R","cited_arxiv_id":null,"evidence_quote":"Supplies the SpiNNaker ring-buffer baseline, with 16 timesteps and 16-bit weights, used for the second memory crossover comparison."},{"cited_title":"Pati ˜no-Saucedo, A","cited_arxiv_id":null,"evidence_quote":"Supplies the delay parameterization and per-synapse delay pruning technique on which SCDQ's operation and sparsity-dependent memory claims rely."},{"cited_title":"Lazzaro, J","cited_arxiv_id":null,"evidence_quote":"Supplies the Address Event Representation packet format that SCDQ extends with a delay-counter field."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the Seneca neuromorphic platform, its core architecture, and the integration point where the Delay IP is measured."},{"cited_title":"Cramer, Y Stradmann, J Schemmel, and F","cited_arxiv_id":null,"evidence_quote":"Supplies the Spiking Heidelberg Digits benchmark used to train and test the four network configurations reported in the fidelity and hardware measurements."}],"review_version":1}