{"id":"caa69914-f7b6-48b3-8a46-80d5e9087c0a","arxiv_id":"2501.14947","paper_version":1,"verdict":"REJECT","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A window-based circuit partitioning heuristic with dynamic one-way teleportation reduces EPR pairs versus a static baseline, and a structured QFT distribution uses nm/2 EPR pairs on m processors.","lead":"This paper proposes a window-based graph partitioning algorithm for splitting quantum circuits across multiple processors while minimizing the EPR pairs needed for non-local gates. It also maps circuit QPUs onto a noisy quantum network via an integer program and counts the entanglement cost of running the Quantum Fourier Transform on multiple QPUs.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The network-mapping ILP is the load-bearing flaw: constraints (5)-(8) force G and G' to have equal vertex and edge counts, so the ILP is infeasible for overprovisioned or non-isomorphic physical networks.","rationale":"The reader's weakest assumption is exactly this point, and I agree. I also considered the Section IV.B QFT count, where Equations (1)-(3) give only upper bounds while the text asserts equality, and where the comparison to [40] plus swap gates may be unfair if reversed qubit order can be handled by bookkeeping; those are genuine weaknesses. However, the ILP flaw is more decisive: it is a formal inconsistency in a core advertised contribution and can be demonstrated by a tiny counterexample. The window-based heuristic has some independent support: the numerical tables show consistent reductions over the paper's own baseline, and the recursive KL extension is a reasonable idea. But that evidence does not redeem the ILP section, and the absence of comparison with prior partitioning methods remains. Overall, the paper's central claim as written is not supported; I would keep the reader's REJECT, while noting that the ILP can likely be repaired by moving from bijective constraints to injection or path-embedding constraints.","tokens_in":16333,"tokens_out":16949,"duration_ms":161433,"concrete_test":"Build a minimal instance with physical graph G = C5 (5-cycle) and demand graph G' = P3 (3-node path), with arbitrary positive weights w_i and l_j. Run the ILP (4)-(18) from Section V.A; because |V(G)| is not equal to |V(G')|, constraints (5)-(6) have no solution, and the solver must return infeasible. If it does, the ILP is not a placement optimizer for an overprovisioned data center; a revised formulation allowing unused vertices and edges, or multi-hop routing, would be needed.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The load-bearing defect is in the ILP of Section V.A. Constraints (5)-(8) require every vertex of the physical graph G to be matched to exactly one vertex of the demand graph G', and vice versa, and similarly for every edge of E(G) and E(G'). Feasible solutions therefore exist only when |V(G)|=|V(G')| and |E(G)|=|E(G')|, i.e., when the ILP is computing a graph isomorphism, not an embedding of a partitioned circuit into a larger physical data center. The problem statement in Section V explicitly describes G as the data center's physical QPUs and G' as the QPUs needed by the circuit; if the data center has more QPUs than the circuit uses, or has a topology with a different number of links, the model is infeasible. The paper never states this equal-size restriction, and Equation (9) does not allow a demand edge to be routed over a physical path, so the advertised network-aware placement cannot handle overprovisioned or non-isomorphic networks. The numerical results in Section V.B therefore do not test the claimed placement problem as stated. This is an internal inconsistency between the problem and the formulation, not merely a comparison against a different baseline.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript addresses distributed execution of quantum circuits across multiple QPUs. It proposes a window-based circuit partitioning (WBCP) heuristic that alternates gate teleportation within windows and qubit teleportation between windows, an integer linear program (ILP) for mapping the resulting EPR-pair demand graph onto a physical QPU network, and a structured protocol for distributing the Quantum Fourier Transform, culminating in the claim that an n-qubit QFT across m QPUs can be executed with nm/2 EPR pairs. Numerical results compare WBCP with a static graph-partitioning baseline on QAOA, Quantum Volume, and other circuits.","tokens_in":16536,"tokens_out":13928,"duration_ms":115747,"significance":"If established, the WBCP heuristic and the structured QFT protocol would be useful additions to distributed quantum computing: the dynamic one-way teleportation idea is sensible, the QFT entanglement count is concrete, and the paper honestly notes that not all circuits benefit from windowing. The ILP placement objective is practically motivated. However, as written, the ILP is only a bijective vertex-and-edge mapping, the main empirical improvement is selected from a window-length sweep on the same circuits, and the QFT count is not rigorously verified. These issues currently prevent the paper from supporting its advertised scope.","major_comments":[{"comment":"The constraints in Eqs. (5)-(8) are bijections: Eq. (5) forces every vertex of the physical graph G to be assigned to exactly one vertex of the demand graph G', Eq. (6) forces the converse, and Eqs. (7)-(8) do the same for edges. Feasible solutions therefore exist only when |V(G)|=|V(G')| and |E(G)|=|E(G')|. This contradicts the problem statement in Section V, where G is the data-center network and G' is the subgraph of QPUs needed by the circuit; in an overprovisioned data center, or when the demand graph has a different number of links, the ILP is infeasible. Equation (9) also maps demand edges only onto physical edges, so a demand between two QPUs cannot be routed over a path. The numerical experiments in Section V.B therefore test a permutation problem on equal-size graphs rather than the stated placement problem. The formulation should be revised to allow assignment with slack or dummy nodes and path routing, or the claims should be explicitly restricted to the equal-size isomorphic case.","section":"Section V.A, Eqs. (5)-(8)"},{"comment":"The reported WBCP counts are the minima over swept window lengths l for the same circuits on which the results are reported, since the text states 'to optimize the EPR count, we evaluate various window sizes.' This is post-hoc selection on the evaluation circuits, so the comparison with Algorithm 1 is optimistic and does not establish a predictive improvement. The window length should be treated as a hyperparameter chosen on a validation set, or fixed a priori, and results should be reported as a function of l or as a distribution over instances rather than as the best value found on the test circuits.","section":"Section III.C, Figs. 4-6, Table I"},{"comment":"Equation (3) is derived as an upper bound, but the text immediately summarizes the result as 'the number of EPR pairs required by the described method is nm/2.' The derivation does not show that the bound is tight, and the movement schedule in Algorithm 5 is not detailed enough to verify the count: in particular, step 9 says 'Apply CR gate with l as control in QPU i' without specifying where the target qubit is located, and the second loop refers to the cat-entangler mechanism without stating how its EPR cost is included. The claimed equality therefore needs either a rigorous counting argument with a clear invariant, or a correction to an explicit upper bound.","section":"Section IV.B, Eq. (3) and Algorithm 5"}],"minor_comments":[{"comment":"The factor 2 used for intra-partition edge weights is introduced without justification or sensitivity analysis; because the decision in line 18 also adds the number of qubits moved, the relative scale of these two costs determines the partition choices and should be discussed.","section":"Section III.A, Algorithm 3"},{"comment":"The reported values are single numbers with no indication of the window length used or the spread over random circuit instances, so it is not possible to assess the stability of the WBCP improvement.","section":"Table I"},{"comment":"The derivation assumes m is even, but the abstract and the concluding summary state the result for an arbitrary number of QPUs without this parity restriction; the statement should be qualified to even m or the odd-m extension should be given.","section":"Section IV.B"},{"comment":"Several axis labels and legend entries are missing or ambiguous: the legend of Fig. 8 does not identify which distribution the beta values refer to, Fig. 9 has no axis labels, and the number of random trials used to produce the averages is not stated.","section":"Section V.B, Figs. 8-9"},{"comment":"References [26], [39], and [52] all refer to the same 'Generalized GHZ states and distributed quantum computing' paper with different formatting; they should be consolidated.","section":"References"},{"comment":"The statement that any two-qubit gate can be decomposed into a CNOT gate and single-qubit rotations is imprecise; a general two-qubit gate requires up to three CNOTs, although this does not affect the subsequent arguments.","section":"Section II"}],"recommendation":"major_revision","confidential_remarks":"To the editor: the ILP issue in Section V.A is the most serious technical problem; if the authors restrict the paper to equal-size complete networks, the contribution shrinks but may still be publishable. The WBCP validation issue is fixable with a proper train/validation split. I do not think rejection is required, but the authors should be asked to rework the ILP formulation and to provide a rigorous derivation or clear upper-bound statement for the QFT count."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Two things to know before you spend time on this. First, the window-based circuit partitioning heuristic (Algorithm 3) is a real new combination: it uses dynamic one-way qubit teleportation, history-weighted edge costs, and a tunable lookahead, and it is not in the cited prior work. On the paper's own baseline (Algorithm 1), it consistently reduces EPR counts across QAOA, quantum volume, and the circuits from [49]. The authors also note that some circuits do not benefit, which is honest. Second, the ILP in Section V.A is not a working formulation of the problem it states. Constraints (5)-(8) require a bijection between V(G) and V(G') and between E(G) and E(G'), so feasible solutions exist only when the physical and demand graphs have equal vertex and edge counts. That means the ILP can only solve a graph-isomorphism-style mapping, not the network-aware placement of a small circuit into a larger data center described in the text. This is a load-bearing flaw, not a side issue.\n\nThe QFT section gives a concrete, checkable count: nm/2 EPR pairs for m QPUs, with a swap-free implementation. The comparison to a generalized [40] adds n swaps to that baseline, which is a defensible accounting choice, though it makes the 'improvement' narrower than the text implies.\n\nThe soft spots, in order of severity: (1) the ILP issue above; (2) the window length is swept on the test circuits and the best value reported, which is post-hoc selection and inflates the measured gain; (3) no comparison to any of the prior partitioning methods cited in Section I, so the reader cannot tell whether WBCP is better than the state of the art, only better than the paper's own baseline; (4) the ILP numerical results in V.B do not exercise the claimed problem because the graphs appear to be the same size.\n\nThe paper is not a waste of time. The heuristic is a reasonable engineering idea, and the QFT count is a useful data point for distributed quantum computing. But the central claims as stated are not supported. Refer a revised version: fix the ILP, evaluate the window length honestly (or use a fixed rule), and benchmark against at least one existing partitioner. A serious referee should engage with it; a serious reader should not take the abstract at face value.","headline":"The window-based partitioning heuristic is a genuine new combination and the QFT count is concrete, but the ILP mapping is broken for real networks and the numerical evidence is overstated.","tokens_in":17130,"tokens_out":3104,"would_cite":false,"duration_ms":27042,"reading_group":"maybe","serious_thinker":"no","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Window-based circuit partitioning cuts EPR pair counts across QPUs, with an exact nm/2 cost for distributed QFT.","keywords":["distributed quantum computing","circuit partitioning","EPR pairs","quantum teleportation","graph partitioning","quantum Fourier transform","integer linear programming","quantum data center"],"falsifier":"Run Algorithm 5 for an 8-qubit QFT on 4 QPUs and count the EPR pairs consumed; the paper's formula $nm/2$ predicts 16, so any count different from 16 would refute the central QFT claim. As a separate check, feed the Section V.A ILP a demand graph with 2 QPUs and a physical graph with 3 QPUs and observe that constraints (5)-(6) force an infeasible assignment.","tokens_in":16045,"feed_emoji":"🔗","tokens_out":10255,"duration_ms":76333,"temperature":0.7,"pith_summary":"The paper tries to make distributed quantum computing cheaper by reducing the number of entangled EPR pairs needed to run a circuit across several quantum processing units (QPUs). Its central proposal is a window-based circuit partitioning algorithm that allows qubits to move between QPUs while the circuit runs, combining qubit teleportation and gate teleportation, and it reports large EPR savings on QAOA, Quantum Volume, and benchmark circuits. On the network side, it formulates an integer linear program that maps the communication demands of a partitioned circuit onto a physical QPU network so that noisy, lossy links are used as little as possible. For the Quantum Fourier Transform, the paper exploits the circuit's structure to obtain a concrete entanglement budget: an n-qubit QFT run on m QPUs consumes $nm/2$ EPR pairs, which is lower than the $nm/2 + n/2$ cost of generalizing an earlier two-processor protocol.","feed_headline":"QFT on many QPUs needs just nm/2 EPR pairs","feed_subtitle":"New algorithm also cuts EPR demand for QAOA and Quantum Volume across multiple QPUs.","key_machinery":"The load-bearing object is the window-based circuit partitioning (WBCP) algorithm, which turns a circuit into a sequence of graphs whose vertices are qubits and whose edge weights count CNOT gates, then partitions each window using the Kernighan-Lin heuristic or a multilevel partitioner; between windows, qubits may be teleported in one direction without returning. A second load-bearing piece is the QFT movement schedule: each qubit tours a fixed sequence of QPUs while controlled rotations are applied, which makes the final swap gates unnecessary and yields the EPR-pair count $nm/2$. A third piece is the integer linear program that maps the abstract demand graph $G'$ of a partitioned circuit onto the physical QPU graph $G$, minimizing the weighted sum of link infidelity times demand, with a linearized quadratic consistency constraint.","core_discovery":"The paper's central claim is that letting qubit assignments change during circuit execution, rather than fixing each qubit to one QPU for the whole run, reduces the EPR-pair cost of distributed quantum circuits. The window-based algorithm divides the circuit into sub-circuits, builds a weighted graph per window whose edges count CNOT gates, partitions that graph with a graph-partitioning heuristic, and allows qubit teleportation between windows; it also weights edges according to previous partitions to discourage unnecessary movement. The authors claim this beats the static edge-cut baseline on QAOA, Quantum Volume, and many benchmark circuits, while acknowledging that shallow circuits such as MCMTV gain nothing. For QFT, they claim an exact count: an n-qubit QFT divided across m QPUs requires $nm/2$ EPR pairs under their protocol, with no end-of-circuit swap gates needed, compared to $nm/2 + n/2$ for the natural generalization of the prior two-processor method.","pith_inferences":["The $nm/2$ formula for distributed QFT suggests a potential lower bound for any teleportation-based scheme that must move each qubit across all other blocks; testing that bound would clarify whether the schedule is optimal among all distributed implementations.","The ILP as written requires the demand graph and physical graph to have the same number of vertices and edges, so it does not directly handle data centers with more QPUs or spare links than a circuit needs; a relaxation with dummy nodes or slack constraints would be needed.","The window length is swept exhaustively, but an adaptive rule that sets the window from circuit locality or entanglement-rate information could remove that tuning step.","The multi-QPU QFT analysis assumes m even and n divisible by m; extending to odd m or unbalanced block sizes is a natural next test."],"forward_implications":["For an n-qubit QFT across m QPUs, the described method consumes exactly $nm/2$ EPR pairs, and no swap gates are needed at the end of the circuit.","This beats the generalized earlier protocol, which costs $nm/2 + n/2$ EPR pairs when the final swaps are included.","On QAOA and Quantum Volume circuits, the window-based algorithm uses fewer EPR pairs than the static edge-cut baseline, with the gap widening as the number of QPUs grows.","The network ILP lowers the weighted entanglement cost relative to random placement, and the improvement increases when both link infidelities and EPR demands are more skewed.","Shallow circuits like MCMTV do not benefit from windowing; the gain depends on circuit depth and structure."],"supporting_citations":[{"why":"Defines quantum state teleportation, the primitive used to move qubits between QPUs between windows.","marker":"[41]"},{"why":"Defines gate teleportation, the method used to implement non-local CNOT gates within a window.","marker":"[42]"},{"why":"Supplies the local-search graph partitioning heuristic used inside the window-based algorithm.","marker":"[44]"},{"why":"Supplies the multilevel graph partitioner used as an alternative to local search when partitioning the window graphs.","marker":"[45]"},{"why":"Provides the earlier two-processor QFT construction that this paper generalizes to m QPUs and uses as its baseline (n/2 EPR pairs without swaps, nm/2 + n/2 with swaps).","marker":"[40]"},{"why":"Defines the QAOA circuit family used in the window-size and EPR-count comparisons.","marker":"[47]"},{"why":"Defines the Quantum Volume circuit family used to benchmark the algorithms across multiple partitions.","marker":"[48]"},{"why":"Provides the benchmark circuits (Qram, swap test, KNN, multiplier, square root, QFT, qugan) used in Table I.","marker":"[49]"},{"why":"Supplies the circuit compiler and toolchain used to generate and transpile the test circuits.","marker":"[50]"},{"why":"Motivates the ILP by describing a quantum data center with heterogeneous link fidelities and costs.","marker":"[21]"}],"fun_headline_variants":["QFT across m QPUs: just nm/2 EPR pairs, no swap gates","Adaptive qubit mapping cuts EPR pairs for distributed QFT","Distributed QFT needs only nm/2 EPR pairs with mid-run moves","Letting qubits jump QPUs mid-circuit reduces EPR cost for QFT","QFT split among m QPUs requires nm/2 EPR pairs, not more"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The network-mapping optimization assumes the number of physical QPUs and links exactly matches the number of QPUs and links the circuit demands, so real data centers with extra processors or spare links make it infeasible as written.","fun_headline_variants_meta":{"raw":{"variants":["QFT across m QPUs: just nm/2 EPR pairs, no swap gates","Adaptive qubit mapping cuts EPR pairs for distributed QFT","Distributed QFT needs only nm/2 EPR pairs with mid-run moves","Letting qubits jump QPUs mid-circuit reduces EPR cost for QFT","QFT split among m QPUs requires nm/2 EPR pairs, not more"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00084,"raw_usage":{"total_tokens":3608,"prompt_tokens":838,"completion_tokens":2770,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":454,"completion_tokens_details":{"reasoning_tokens":2661}},"tokens_in":454,"tokens_out":2770,"duration_ms":18074,"temperature":1.0,"reasoning_tokens":2661,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T14:47:23.104496+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run Algorithm 5 for an 8-qubit QFT on 4 QPUs and count the EPR pairs consumed; the paper's formula $nm/2$ predicts 16, so any count different from 16 would refute the central QFT claim. As a separate check, feed the Section V.A ILP a demand graph with 2 QPUs and a physical graph with 3 QPUs and observe that constraints (5)-(6) force an infeasible assignment.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines quantum state teleportation, the primitive used to move qubits between QPUs between windows."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines gate teleportation, the method used to implement non-local CNOT gates within a window."},{"cited_title":"Escofet, A","cited_arxiv_id":null,"evidence_quote":"Supplies the local-search graph partitioning heuristic used inside the window-based algorithm."},{"cited_title":"Pastor, P","cited_arxiv_id":null,"evidence_quote":"Supplies the multilevel graph partitioner used as an alternative to local search when partitioning the window graphs."},{"cited_title":"G Sundaram, H","cited_arxiv_id":null,"evidence_quote":"Provides the earlier two-processor QFT construction that this paper generalizes to m QPUs and uses as its baseline (n/2 EPR pairs without swaps, nm/2 + n/2 with swaps)."},{"cited_title":"As discussed, the algorithm is very sensi- tive to the chosen window size","cited_arxiv_id":null,"evidence_quote":"Defines the QAOA circuit family used in the window-size and EPR-count comparisons."},{"cited_title":"Im- perfect distributed quantum phase estimation,","cited_arxiv_id":null,"evidence_quote":"Defines the Quantum Volume circuit family used to benchmark the algorithms across multiple partitions."},{"cited_title":"Gottesman and I","cited_arxiv_id":null,"evidence_quote":"Provides the benchmark circuits (Qram, swap test, KNN, multiplier, square root, QFT, qugan) used in Table I."},{"cited_title":"Eisert, K","cited_arxiv_id":null,"evidence_quote":"Supplies the circuit compiler and toolchain used to generate and transpile the test circuits."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Motivates the ILP by describing a quantum data center with heterogeneous link fidelities and costs."}],"review_version":1}